1902e6eb8SRob Clark #ifndef A2XX_XML 2902e6eb8SRob Clark #define A2XX_XML 3902e6eb8SRob Clark 4902e6eb8SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5902e6eb8SRob Clark 6902e6eb8SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 722ba8b6bSRob Clark http://github.com/freedreno/envytools/ 822ba8b6bSRob Clark git clone https://github.com/freedreno/envytools.git 9902e6eb8SRob Clark 10902e6eb8SRob Clark The rules-ng-ng source files this header was generated from are: 118217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 12a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 132d3584ebSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 14a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) 15a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) 16a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) 17a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) 188217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19902e6eb8SRob Clark 202d3584ebSRob Clark Copyright (C) 2013-2015 by the following authors: 21902e6eb8SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 22a2272e48SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 23902e6eb8SRob Clark 24902e6eb8SRob Clark Permission is hereby granted, free of charge, to any person obtaining 25902e6eb8SRob Clark a copy of this software and associated documentation files (the 26902e6eb8SRob Clark "Software"), to deal in the Software without restriction, including 27902e6eb8SRob Clark without limitation the rights to use, copy, modify, merge, publish, 28902e6eb8SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 29902e6eb8SRob Clark permit persons to whom the Software is furnished to do so, subject to 30902e6eb8SRob Clark the following conditions: 31902e6eb8SRob Clark 32902e6eb8SRob Clark The above copyright notice and this permission notice (including the 33902e6eb8SRob Clark next paragraph) shall be included in all copies or substantial 34902e6eb8SRob Clark portions of the Software. 35902e6eb8SRob Clark 36902e6eb8SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37902e6eb8SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 38902e6eb8SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 39902e6eb8SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 40902e6eb8SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 41902e6eb8SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 42902e6eb8SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 43902e6eb8SRob Clark */ 44902e6eb8SRob Clark 45902e6eb8SRob Clark 46902e6eb8SRob Clark enum a2xx_rb_dither_type { 47902e6eb8SRob Clark DITHER_PIXEL = 0, 48902e6eb8SRob Clark DITHER_SUBPIXEL = 1, 49902e6eb8SRob Clark }; 50902e6eb8SRob Clark 51902e6eb8SRob Clark enum a2xx_colorformatx { 52902e6eb8SRob Clark COLORX_4_4_4_4 = 0, 53902e6eb8SRob Clark COLORX_1_5_5_5 = 1, 54902e6eb8SRob Clark COLORX_5_6_5 = 2, 55902e6eb8SRob Clark COLORX_8 = 3, 56902e6eb8SRob Clark COLORX_8_8 = 4, 57902e6eb8SRob Clark COLORX_8_8_8_8 = 5, 58902e6eb8SRob Clark COLORX_S8_8_8_8 = 6, 59902e6eb8SRob Clark COLORX_16_FLOAT = 7, 60902e6eb8SRob Clark COLORX_16_16_FLOAT = 8, 61902e6eb8SRob Clark COLORX_16_16_16_16_FLOAT = 9, 62902e6eb8SRob Clark COLORX_32_FLOAT = 10, 63902e6eb8SRob Clark COLORX_32_32_FLOAT = 11, 64902e6eb8SRob Clark COLORX_32_32_32_32_FLOAT = 12, 65902e6eb8SRob Clark COLORX_2_3_3 = 13, 66902e6eb8SRob Clark COLORX_8_8_8 = 14, 67902e6eb8SRob Clark }; 68902e6eb8SRob Clark 69902e6eb8SRob Clark enum a2xx_sq_surfaceformat { 70902e6eb8SRob Clark FMT_1_REVERSE = 0, 71902e6eb8SRob Clark FMT_1 = 1, 72902e6eb8SRob Clark FMT_8 = 2, 73902e6eb8SRob Clark FMT_1_5_5_5 = 3, 74902e6eb8SRob Clark FMT_5_6_5 = 4, 75902e6eb8SRob Clark FMT_6_5_5 = 5, 76902e6eb8SRob Clark FMT_8_8_8_8 = 6, 77902e6eb8SRob Clark FMT_2_10_10_10 = 7, 78902e6eb8SRob Clark FMT_8_A = 8, 79902e6eb8SRob Clark FMT_8_B = 9, 80902e6eb8SRob Clark FMT_8_8 = 10, 81902e6eb8SRob Clark FMT_Cr_Y1_Cb_Y0 = 11, 82902e6eb8SRob Clark FMT_Y1_Cr_Y0_Cb = 12, 83902e6eb8SRob Clark FMT_5_5_5_1 = 13, 84902e6eb8SRob Clark FMT_8_8_8_8_A = 14, 85902e6eb8SRob Clark FMT_4_4_4_4 = 15, 86902e6eb8SRob Clark FMT_10_11_11 = 16, 87902e6eb8SRob Clark FMT_11_11_10 = 17, 88902e6eb8SRob Clark FMT_DXT1 = 18, 89902e6eb8SRob Clark FMT_DXT2_3 = 19, 90902e6eb8SRob Clark FMT_DXT4_5 = 20, 91902e6eb8SRob Clark FMT_24_8 = 22, 92902e6eb8SRob Clark FMT_24_8_FLOAT = 23, 93902e6eb8SRob Clark FMT_16 = 24, 94902e6eb8SRob Clark FMT_16_16 = 25, 95902e6eb8SRob Clark FMT_16_16_16_16 = 26, 96902e6eb8SRob Clark FMT_16_EXPAND = 27, 97902e6eb8SRob Clark FMT_16_16_EXPAND = 28, 98902e6eb8SRob Clark FMT_16_16_16_16_EXPAND = 29, 99902e6eb8SRob Clark FMT_16_FLOAT = 30, 100902e6eb8SRob Clark FMT_16_16_FLOAT = 31, 101902e6eb8SRob Clark FMT_16_16_16_16_FLOAT = 32, 102902e6eb8SRob Clark FMT_32 = 33, 103902e6eb8SRob Clark FMT_32_32 = 34, 104902e6eb8SRob Clark FMT_32_32_32_32 = 35, 105902e6eb8SRob Clark FMT_32_FLOAT = 36, 106902e6eb8SRob Clark FMT_32_32_FLOAT = 37, 107902e6eb8SRob Clark FMT_32_32_32_32_FLOAT = 38, 108902e6eb8SRob Clark FMT_32_AS_8 = 39, 109902e6eb8SRob Clark FMT_32_AS_8_8 = 40, 110902e6eb8SRob Clark FMT_16_MPEG = 41, 111902e6eb8SRob Clark FMT_16_16_MPEG = 42, 112902e6eb8SRob Clark FMT_8_INTERLACED = 43, 113902e6eb8SRob Clark FMT_32_AS_8_INTERLACED = 44, 114902e6eb8SRob Clark FMT_32_AS_8_8_INTERLACED = 45, 115902e6eb8SRob Clark FMT_16_INTERLACED = 46, 116902e6eb8SRob Clark FMT_16_MPEG_INTERLACED = 47, 117902e6eb8SRob Clark FMT_16_16_MPEG_INTERLACED = 48, 118902e6eb8SRob Clark FMT_DXN = 49, 119902e6eb8SRob Clark FMT_8_8_8_8_AS_16_16_16_16 = 50, 120902e6eb8SRob Clark FMT_DXT1_AS_16_16_16_16 = 51, 121902e6eb8SRob Clark FMT_DXT2_3_AS_16_16_16_16 = 52, 122902e6eb8SRob Clark FMT_DXT4_5_AS_16_16_16_16 = 53, 123902e6eb8SRob Clark FMT_2_10_10_10_AS_16_16_16_16 = 54, 124902e6eb8SRob Clark FMT_10_11_11_AS_16_16_16_16 = 55, 125902e6eb8SRob Clark FMT_11_11_10_AS_16_16_16_16 = 56, 126902e6eb8SRob Clark FMT_32_32_32_FLOAT = 57, 127902e6eb8SRob Clark FMT_DXT3A = 58, 128902e6eb8SRob Clark FMT_DXT5A = 59, 129902e6eb8SRob Clark FMT_CTX1 = 60, 130902e6eb8SRob Clark FMT_DXT3A_AS_1_1_1_1 = 61, 131902e6eb8SRob Clark }; 132902e6eb8SRob Clark 133902e6eb8SRob Clark enum a2xx_sq_ps_vtx_mode { 134902e6eb8SRob Clark POSITION_1_VECTOR = 0, 135902e6eb8SRob Clark POSITION_2_VECTORS_UNUSED = 1, 136902e6eb8SRob Clark POSITION_2_VECTORS_SPRITE = 2, 137902e6eb8SRob Clark POSITION_2_VECTORS_EDGE = 3, 138902e6eb8SRob Clark POSITION_2_VECTORS_KILL = 4, 139902e6eb8SRob Clark POSITION_2_VECTORS_SPRITE_KILL = 5, 140902e6eb8SRob Clark POSITION_2_VECTORS_EDGE_KILL = 6, 141902e6eb8SRob Clark MULTIPASS = 7, 142902e6eb8SRob Clark }; 143902e6eb8SRob Clark 144902e6eb8SRob Clark enum a2xx_sq_sample_cntl { 145902e6eb8SRob Clark CENTROIDS_ONLY = 0, 146902e6eb8SRob Clark CENTERS_ONLY = 1, 147902e6eb8SRob Clark CENTROIDS_AND_CENTERS = 2, 148902e6eb8SRob Clark }; 149902e6eb8SRob Clark 150902e6eb8SRob Clark enum a2xx_dx_clip_space { 151902e6eb8SRob Clark DXCLIP_OPENGL = 0, 152902e6eb8SRob Clark DXCLIP_DIRECTX = 1, 153902e6eb8SRob Clark }; 154902e6eb8SRob Clark 155902e6eb8SRob Clark enum a2xx_pa_su_sc_polymode { 156902e6eb8SRob Clark POLY_DISABLED = 0, 157902e6eb8SRob Clark POLY_DUALMODE = 1, 158902e6eb8SRob Clark }; 159902e6eb8SRob Clark 160902e6eb8SRob Clark enum a2xx_rb_edram_mode { 161902e6eb8SRob Clark EDRAM_NOP = 0, 162902e6eb8SRob Clark COLOR_DEPTH = 4, 163902e6eb8SRob Clark DEPTH_ONLY = 5, 164902e6eb8SRob Clark EDRAM_COPY = 6, 165902e6eb8SRob Clark }; 166902e6eb8SRob Clark 167902e6eb8SRob Clark enum a2xx_pa_sc_pattern_bit_order { 168902e6eb8SRob Clark LITTLE = 0, 169902e6eb8SRob Clark BIG = 1, 170902e6eb8SRob Clark }; 171902e6eb8SRob Clark 172902e6eb8SRob Clark enum a2xx_pa_sc_auto_reset_cntl { 173902e6eb8SRob Clark NEVER = 0, 174902e6eb8SRob Clark EACH_PRIMITIVE = 1, 175902e6eb8SRob Clark EACH_PACKET = 2, 176902e6eb8SRob Clark }; 177902e6eb8SRob Clark 178902e6eb8SRob Clark enum a2xx_pa_pixcenter { 179902e6eb8SRob Clark PIXCENTER_D3D = 0, 180902e6eb8SRob Clark PIXCENTER_OGL = 1, 181902e6eb8SRob Clark }; 182902e6eb8SRob Clark 183902e6eb8SRob Clark enum a2xx_pa_roundmode { 184902e6eb8SRob Clark TRUNCATE = 0, 185902e6eb8SRob Clark ROUND = 1, 186902e6eb8SRob Clark ROUNDTOEVEN = 2, 187902e6eb8SRob Clark ROUNDTOODD = 3, 188902e6eb8SRob Clark }; 189902e6eb8SRob Clark 190902e6eb8SRob Clark enum a2xx_pa_quantmode { 191902e6eb8SRob Clark ONE_SIXTEENTH = 0, 192902e6eb8SRob Clark ONE_EIGTH = 1, 193902e6eb8SRob Clark ONE_QUARTER = 2, 194902e6eb8SRob Clark ONE_HALF = 3, 195902e6eb8SRob Clark ONE = 4, 196902e6eb8SRob Clark }; 197902e6eb8SRob Clark 198902e6eb8SRob Clark enum a2xx_rb_copy_sample_select { 199902e6eb8SRob Clark SAMPLE_0 = 0, 200902e6eb8SRob Clark SAMPLE_1 = 1, 201902e6eb8SRob Clark SAMPLE_2 = 2, 202902e6eb8SRob Clark SAMPLE_3 = 3, 203902e6eb8SRob Clark SAMPLE_01 = 4, 204902e6eb8SRob Clark SAMPLE_23 = 5, 205902e6eb8SRob Clark SAMPLE_0123 = 6, 206902e6eb8SRob Clark }; 207902e6eb8SRob Clark 20889301471SRob Clark enum a2xx_rb_blend_opcode { 20989301471SRob Clark BLEND_DST_PLUS_SRC = 0, 21089301471SRob Clark BLEND_SRC_MINUS_DST = 1, 21189301471SRob Clark BLEND_MIN_DST_SRC = 2, 21289301471SRob Clark BLEND_MAX_DST_SRC = 3, 21389301471SRob Clark BLEND_DST_MINUS_SRC = 4, 21489301471SRob Clark BLEND_DST_PLUS_SRC_BIAS = 5, 21589301471SRob Clark }; 21689301471SRob Clark 217facb4f4eSRob Clark enum adreno_mmu_clnt_beh { 218facb4f4eSRob Clark BEH_NEVR = 0, 219facb4f4eSRob Clark BEH_TRAN_RNG = 1, 220facb4f4eSRob Clark BEH_TRAN_FLT = 2, 221facb4f4eSRob Clark }; 222facb4f4eSRob Clark 223902e6eb8SRob Clark enum sq_tex_clamp { 224902e6eb8SRob Clark SQ_TEX_WRAP = 0, 225902e6eb8SRob Clark SQ_TEX_MIRROR = 1, 226902e6eb8SRob Clark SQ_TEX_CLAMP_LAST_TEXEL = 2, 227902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 228902e6eb8SRob Clark SQ_TEX_CLAMP_HALF_BORDER = 4, 229902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 230902e6eb8SRob Clark SQ_TEX_CLAMP_BORDER = 6, 231902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_BORDER = 7, 232902e6eb8SRob Clark }; 233902e6eb8SRob Clark 234902e6eb8SRob Clark enum sq_tex_swiz { 235902e6eb8SRob Clark SQ_TEX_X = 0, 236902e6eb8SRob Clark SQ_TEX_Y = 1, 237902e6eb8SRob Clark SQ_TEX_Z = 2, 238902e6eb8SRob Clark SQ_TEX_W = 3, 239902e6eb8SRob Clark SQ_TEX_ZERO = 4, 240902e6eb8SRob Clark SQ_TEX_ONE = 5, 241902e6eb8SRob Clark }; 242902e6eb8SRob Clark 243902e6eb8SRob Clark enum sq_tex_filter { 244902e6eb8SRob Clark SQ_TEX_FILTER_POINT = 0, 245902e6eb8SRob Clark SQ_TEX_FILTER_BILINEAR = 1, 246902e6eb8SRob Clark SQ_TEX_FILTER_BICUBIC = 2, 247902e6eb8SRob Clark }; 248902e6eb8SRob Clark 249902e6eb8SRob Clark #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 250902e6eb8SRob Clark 251902e6eb8SRob Clark #define REG_A2XX_RBBM_CNTL 0x0000003b 252902e6eb8SRob Clark 253902e6eb8SRob Clark #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 254902e6eb8SRob Clark 255902e6eb8SRob Clark #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 256902e6eb8SRob Clark 257902e6eb8SRob Clark #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 258902e6eb8SRob Clark 259facb4f4eSRob Clark #define REG_A2XX_MH_MMU_CONFIG 0x00000040 260facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 261facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 262facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 263facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 264facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 265facb4f4eSRob Clark { 266facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 267facb4f4eSRob Clark } 268facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 269facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 270facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 271facb4f4eSRob Clark { 272facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 273facb4f4eSRob Clark } 274facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 275facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 276facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 277facb4f4eSRob Clark { 278facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 279facb4f4eSRob Clark } 280facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 281facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 282facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 283facb4f4eSRob Clark { 284facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 285facb4f4eSRob Clark } 286facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 287facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 288facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 289facb4f4eSRob Clark { 290facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 291facb4f4eSRob Clark } 292facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 293facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 294facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 295facb4f4eSRob Clark { 296facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 297facb4f4eSRob Clark } 298facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 299facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 300facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 301facb4f4eSRob Clark { 302facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 303facb4f4eSRob Clark } 304facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 305facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 306facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 307facb4f4eSRob Clark { 308facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 309facb4f4eSRob Clark } 310facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 311facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 312facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 313facb4f4eSRob Clark { 314facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 315facb4f4eSRob Clark } 316facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 317facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 318facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 319facb4f4eSRob Clark { 320facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 321facb4f4eSRob Clark } 322facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 323facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 324facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 325facb4f4eSRob Clark { 326facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 327facb4f4eSRob Clark } 328facb4f4eSRob Clark 329facb4f4eSRob Clark #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 330facb4f4eSRob Clark 331facb4f4eSRob Clark #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 332facb4f4eSRob Clark 333facb4f4eSRob Clark #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 334facb4f4eSRob Clark 335facb4f4eSRob Clark #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 336facb4f4eSRob Clark 337facb4f4eSRob Clark #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 338facb4f4eSRob Clark 339facb4f4eSRob Clark #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 340facb4f4eSRob Clark 341facb4f4eSRob Clark #define REG_A2XX_MH_MMU_MPU_END 0x00000047 342facb4f4eSRob Clark 343facb4f4eSRob Clark #define REG_A2XX_NQWAIT_UNTIL 0x00000394 344facb4f4eSRob Clark 345902e6eb8SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 346902e6eb8SRob Clark 347902e6eb8SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 348902e6eb8SRob Clark 349902e6eb8SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 350902e6eb8SRob Clark 351902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG 0x0000039b 352902e6eb8SRob Clark 353902e6eb8SRob Clark #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 354902e6eb8SRob Clark 355902e6eb8SRob Clark #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 356902e6eb8SRob Clark 357902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 358902e6eb8SRob Clark 359902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 360902e6eb8SRob Clark 361902e6eb8SRob Clark #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 362902e6eb8SRob Clark 363902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 364902e6eb8SRob Clark 365902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 366902e6eb8SRob Clark 367902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_ACK 0x000003b6 368902e6eb8SRob Clark 369902e6eb8SRob Clark #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 370902e6eb8SRob Clark 371902e6eb8SRob Clark #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 372902e6eb8SRob Clark 373902e6eb8SRob Clark #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 374902e6eb8SRob Clark 375902e6eb8SRob Clark #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 376902e6eb8SRob Clark 377902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 378902e6eb8SRob Clark 379902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 380902e6eb8SRob Clark 381902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 382902e6eb8SRob Clark 383902e6eb8SRob Clark #define REG_A2XX_RBBM_STATUS 0x000005d0 384902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 385902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 386902e6eb8SRob Clark static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 387902e6eb8SRob Clark { 388902e6eb8SRob Clark return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 389902e6eb8SRob Clark } 390902e6eb8SRob Clark #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 391902e6eb8SRob Clark #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 392902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 393902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 394902e6eb8SRob Clark #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 395902e6eb8SRob Clark #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 396902e6eb8SRob Clark #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 397902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 398902e6eb8SRob Clark #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 399902e6eb8SRob Clark #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 400902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 401902e6eb8SRob Clark #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 402902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 403902e6eb8SRob Clark #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 404902e6eb8SRob Clark #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 405902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 406902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 407902e6eb8SRob Clark #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 408902e6eb8SRob Clark #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 409902e6eb8SRob Clark 41022ba8b6bSRob Clark #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 41122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 41222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 41322ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 41422ba8b6bSRob Clark { 41522ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 41622ba8b6bSRob Clark } 41722ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 41822ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 41922ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 42022ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 42122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 42222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 42322ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 42422ba8b6bSRob Clark { 42522ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 42622ba8b6bSRob Clark } 42722ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 42822ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 42922ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 43022ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 43122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 43222ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 43322ba8b6bSRob Clark { 43422ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 43522ba8b6bSRob Clark } 43622ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 43722ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 43822ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 43922ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 44022ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 44122ba8b6bSRob Clark 442902e6eb8SRob Clark #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 443902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 444902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 445902e6eb8SRob Clark static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 446902e6eb8SRob Clark { 447902e6eb8SRob Clark return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 448902e6eb8SRob Clark } 449902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 450902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 451902e6eb8SRob Clark static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 452902e6eb8SRob Clark { 453902e6eb8SRob Clark return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 454902e6eb8SRob Clark } 455902e6eb8SRob Clark 456902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 457902e6eb8SRob Clark 458902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 459902e6eb8SRob Clark 460902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 461902e6eb8SRob Clark 462902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 463902e6eb8SRob Clark 464902e6eb8SRob Clark #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 465902e6eb8SRob Clark 466902e6eb8SRob Clark #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 467902e6eb8SRob Clark 468902e6eb8SRob Clark #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 469902e6eb8SRob Clark 470902e6eb8SRob Clark #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 471902e6eb8SRob Clark 472902e6eb8SRob Clark #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 473902e6eb8SRob Clark 474902e6eb8SRob Clark #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 475902e6eb8SRob Clark 476902e6eb8SRob Clark #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 477902e6eb8SRob Clark 478902e6eb8SRob Clark #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 479902e6eb8SRob Clark 480902e6eb8SRob Clark #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 481902e6eb8SRob Clark 482902e6eb8SRob Clark #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 483902e6eb8SRob Clark 484902e6eb8SRob Clark #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 485902e6eb8SRob Clark 486902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 487902e6eb8SRob Clark 488902e6eb8SRob Clark #define REG_A2XX_SQ_INT_CNTL 0x00000d34 489902e6eb8SRob Clark 490902e6eb8SRob Clark #define REG_A2XX_SQ_INT_STATUS 0x00000d35 491902e6eb8SRob Clark 492902e6eb8SRob Clark #define REG_A2XX_SQ_INT_ACK 0x00000d36 493902e6eb8SRob Clark 494902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 495902e6eb8SRob Clark 496902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 497902e6eb8SRob Clark 498902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 499902e6eb8SRob Clark 500902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 501902e6eb8SRob Clark 502902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 503902e6eb8SRob Clark 504902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 505902e6eb8SRob Clark 506902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 507902e6eb8SRob Clark 508902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 509902e6eb8SRob Clark 510902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 511902e6eb8SRob Clark 512902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 513902e6eb8SRob Clark 514902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 515902e6eb8SRob Clark 516902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 517902e6eb8SRob Clark 518902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 519902e6eb8SRob Clark 520902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 521902e6eb8SRob Clark 522902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 523902e6eb8SRob Clark 524902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 525902e6eb8SRob Clark 526902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 527902e6eb8SRob Clark 528902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 529902e6eb8SRob Clark 530902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 531902e6eb8SRob Clark 532902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 533902e6eb8SRob Clark 534902e6eb8SRob Clark #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 535902e6eb8SRob Clark #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 536902e6eb8SRob Clark 537902e6eb8SRob Clark #define REG_A2XX_TP0_CHICKEN 0x00000e1e 538902e6eb8SRob Clark 539902e6eb8SRob Clark #define REG_A2XX_RB_BC_CONTROL 0x00000f01 540902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 541902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 542902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 543902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 544902e6eb8SRob Clark { 545902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 546902e6eb8SRob Clark } 547902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 548902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 549902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 550902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 551902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 552902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 553902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 554902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 555902e6eb8SRob Clark { 556902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 557902e6eb8SRob Clark } 558902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 559902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 560902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 561902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 562902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 563902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 564902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 565902e6eb8SRob Clark { 566902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 567902e6eb8SRob Clark } 568902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 569902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 570902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 571902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 572902e6eb8SRob Clark { 573902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 574902e6eb8SRob Clark } 575902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 576902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 577902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 578902e6eb8SRob Clark { 579902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 580902e6eb8SRob Clark } 581902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 582902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 583902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 584902e6eb8SRob Clark 585902e6eb8SRob Clark #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 586902e6eb8SRob Clark 587902e6eb8SRob Clark #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 588902e6eb8SRob Clark 589902e6eb8SRob Clark #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 590902e6eb8SRob Clark 591902e6eb8SRob Clark #define REG_A2XX_RB_SURFACE_INFO 0x00002000 592902e6eb8SRob Clark 593902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_INFO 0x00002001 594902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 595902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 596902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 597902e6eb8SRob Clark { 598902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 599902e6eb8SRob Clark } 600902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 601902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 602902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 603902e6eb8SRob Clark { 604902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 605902e6eb8SRob Clark } 606902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 607902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 608902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 609902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 610902e6eb8SRob Clark { 611902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 612902e6eb8SRob Clark } 613902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 614902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 615902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 616902e6eb8SRob Clark { 617902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 618902e6eb8SRob Clark } 619902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 620902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 621902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 622902e6eb8SRob Clark { 623902e6eb8SRob Clark return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 624902e6eb8SRob Clark } 625902e6eb8SRob Clark 626902e6eb8SRob Clark #define REG_A2XX_RB_DEPTH_INFO 0x00002002 627902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 628902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 629902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 630902e6eb8SRob Clark { 631902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 632902e6eb8SRob Clark } 633902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 634902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 635902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 636902e6eb8SRob Clark { 637902e6eb8SRob Clark return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 638902e6eb8SRob Clark } 639902e6eb8SRob Clark 640902e6eb8SRob Clark #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 641902e6eb8SRob Clark 642902e6eb8SRob Clark #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 643902e6eb8SRob Clark 644902e6eb8SRob Clark #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 645902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 646902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 647902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 648902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 649902e6eb8SRob Clark { 650902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 651902e6eb8SRob Clark } 652902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 653902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 654902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 655902e6eb8SRob Clark { 656902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 657902e6eb8SRob Clark } 658902e6eb8SRob Clark 659902e6eb8SRob Clark #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 660902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 661902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 662902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 663902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 664902e6eb8SRob Clark { 665902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 666902e6eb8SRob Clark } 667902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 668902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 669902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 670902e6eb8SRob Clark { 671902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 672902e6eb8SRob Clark } 673902e6eb8SRob Clark 674902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 675902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 676902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 677902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 678902e6eb8SRob Clark { 679902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 680902e6eb8SRob Clark } 681902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 682902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 683902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 684902e6eb8SRob Clark { 685902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 686902e6eb8SRob Clark } 687902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 688902e6eb8SRob Clark 689902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 690902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 691902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 692902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 693902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 694902e6eb8SRob Clark { 695902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 696902e6eb8SRob Clark } 697902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 698902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 699902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 700902e6eb8SRob Clark { 701902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 702902e6eb8SRob Clark } 703902e6eb8SRob Clark 704902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 705902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 706902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 707902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 708902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 709902e6eb8SRob Clark { 710902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 711902e6eb8SRob Clark } 712902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 713902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 714902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 715902e6eb8SRob Clark { 716902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 717902e6eb8SRob Clark } 718902e6eb8SRob Clark 719902e6eb8SRob Clark #define REG_A2XX_UNKNOWN_2010 0x00002010 720902e6eb8SRob Clark 721902e6eb8SRob Clark #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 722902e6eb8SRob Clark 723902e6eb8SRob Clark #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 724902e6eb8SRob Clark 725902e6eb8SRob Clark #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 726902e6eb8SRob Clark 727902e6eb8SRob Clark #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 728902e6eb8SRob Clark 729902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_MASK 0x00002104 730902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 731902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 732902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 733902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 734902e6eb8SRob Clark 735902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_RED 0x00002105 736902e6eb8SRob Clark 737902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_GREEN 0x00002106 738902e6eb8SRob Clark 739902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_BLUE 0x00002107 740902e6eb8SRob Clark 741902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 742902e6eb8SRob Clark 743902e6eb8SRob Clark #define REG_A2XX_RB_FOG_COLOR 0x00002109 744902e6eb8SRob Clark 745902e6eb8SRob Clark #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 746902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 747902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 748902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 749902e6eb8SRob Clark { 750902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 751902e6eb8SRob Clark } 752902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 753902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 754902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 755902e6eb8SRob Clark { 756902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 757902e6eb8SRob Clark } 758902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 759902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 760902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 761902e6eb8SRob Clark { 762902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 763902e6eb8SRob Clark } 764902e6eb8SRob Clark 765902e6eb8SRob Clark #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 766902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 767902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 768902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 769902e6eb8SRob Clark { 770902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 771902e6eb8SRob Clark } 772902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 773902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 774902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 775902e6eb8SRob Clark { 776902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 777902e6eb8SRob Clark } 778902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 779902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 780902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 781902e6eb8SRob Clark { 782902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 783902e6eb8SRob Clark } 784902e6eb8SRob Clark 785902e6eb8SRob Clark #define REG_A2XX_RB_ALPHA_REF 0x0000210e 786902e6eb8SRob Clark 787902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 788902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 789902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 790902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 791902e6eb8SRob Clark { 792902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 793902e6eb8SRob Clark } 794902e6eb8SRob Clark 795902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 796902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 797902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 798902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 799902e6eb8SRob Clark { 800902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 801902e6eb8SRob Clark } 802902e6eb8SRob Clark 803902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 804902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 805902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 806902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 807902e6eb8SRob Clark { 808902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 809902e6eb8SRob Clark } 810902e6eb8SRob Clark 811902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 812902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 813902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 814902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 815902e6eb8SRob Clark { 816902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 817902e6eb8SRob Clark } 818902e6eb8SRob Clark 819902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 820902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 821902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 822902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 823902e6eb8SRob Clark { 824902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 825902e6eb8SRob Clark } 826902e6eb8SRob Clark 827902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 828902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 829902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 830902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 831902e6eb8SRob Clark { 832902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 833902e6eb8SRob Clark } 834902e6eb8SRob Clark 835902e6eb8SRob Clark #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 836902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 837902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 838902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 839902e6eb8SRob Clark { 840902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 841902e6eb8SRob Clark } 842902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 843902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 844902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 845902e6eb8SRob Clark { 846902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 847902e6eb8SRob Clark } 848902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 849902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 850902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 851902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 852902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 853902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 854902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 855902e6eb8SRob Clark { 856902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 857902e6eb8SRob Clark } 858902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 859902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 860902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 861902e6eb8SRob Clark { 862902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 863902e6eb8SRob Clark } 864902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 865902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 866902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 867902e6eb8SRob Clark { 868902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 869902e6eb8SRob Clark } 870902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 871902e6eb8SRob Clark 872902e6eb8SRob Clark #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 873902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 874902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 875902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 876902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 877902e6eb8SRob Clark static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 878902e6eb8SRob Clark { 879902e6eb8SRob Clark return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 880902e6eb8SRob Clark } 881902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 882902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 883902e6eb8SRob Clark static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 884902e6eb8SRob Clark { 885902e6eb8SRob Clark return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 886902e6eb8SRob Clark } 887902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 888902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 889902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 890902e6eb8SRob Clark 891902e6eb8SRob Clark #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 892902e6eb8SRob Clark 893902e6eb8SRob Clark #define REG_A2XX_SQ_WRAPPING_0 0x00002183 894902e6eb8SRob Clark 895902e6eb8SRob Clark #define REG_A2XX_SQ_WRAPPING_1 0x00002184 896902e6eb8SRob Clark 897902e6eb8SRob Clark #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 898902e6eb8SRob Clark 899902e6eb8SRob Clark #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 900902e6eb8SRob Clark 901facb4f4eSRob Clark #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 902facb4f4eSRob Clark 903facb4f4eSRob Clark #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 90489301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 90589301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 90689301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 90789301471SRob Clark { 90889301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 90989301471SRob Clark } 91089301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 91189301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 91289301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 91389301471SRob Clark { 91489301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 91589301471SRob Clark } 91689301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 91789301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 91889301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 91989301471SRob Clark { 92089301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 92189301471SRob Clark } 92289301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 92389301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 92489301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 92589301471SRob Clark { 92689301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 92789301471SRob Clark } 92889301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 92989301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 93089301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 931bc00ae02SRob Clark #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 932bc00ae02SRob Clark #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 933bc00ae02SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 93489301471SRob Clark { 935bc00ae02SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 93689301471SRob Clark } 937facb4f4eSRob Clark 938facb4f4eSRob Clark #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 939facb4f4eSRob Clark 940902e6eb8SRob Clark #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 941902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 942902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 943902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 944902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 945902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 946902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 947902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 948902e6eb8SRob Clark { 949902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 950902e6eb8SRob Clark } 951902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 952902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 953902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 954902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 955902e6eb8SRob Clark { 956902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 957902e6eb8SRob Clark } 958902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 959902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 960902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 961902e6eb8SRob Clark { 962902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 963902e6eb8SRob Clark } 964902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 965902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 966902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 967902e6eb8SRob Clark { 968902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 969902e6eb8SRob Clark } 970902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 971902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 972902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 973902e6eb8SRob Clark { 974902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 975902e6eb8SRob Clark } 976902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 977902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 978902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 979902e6eb8SRob Clark { 980902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 981902e6eb8SRob Clark } 982902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 983902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 984902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 985902e6eb8SRob Clark { 986902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 987902e6eb8SRob Clark } 988902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 989902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 990902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 991902e6eb8SRob Clark { 992902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 993902e6eb8SRob Clark } 994902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 995902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 996902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 997902e6eb8SRob Clark { 998902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 999902e6eb8SRob Clark } 1000902e6eb8SRob Clark 1001902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 1002902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 1003902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 1004902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 1005902e6eb8SRob Clark { 1006902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 1007902e6eb8SRob Clark } 1008902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 1009902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 101089301471SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 1011902e6eb8SRob Clark { 1012902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 1013902e6eb8SRob Clark } 1014902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 1015902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 1016902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 1017902e6eb8SRob Clark { 1018902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 1019902e6eb8SRob Clark } 1020902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 1021902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 1022902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 1023902e6eb8SRob Clark { 1024902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 1025902e6eb8SRob Clark } 1026902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 1027902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 102889301471SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 1029902e6eb8SRob Clark { 1030902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 1031902e6eb8SRob Clark } 1032902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 1033902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 1034902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 1035902e6eb8SRob Clark { 1036902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 1037902e6eb8SRob Clark } 1038902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 1039902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 1040902e6eb8SRob Clark 1041902e6eb8SRob Clark #define REG_A2XX_RB_COLORCONTROL 0x00002202 1042902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 1043902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 1044902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 1045902e6eb8SRob Clark { 1046902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 1047902e6eb8SRob Clark } 1048902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 1049902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 1050902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 1051902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 1052902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 1053902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 1054902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 1055902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 1056902e6eb8SRob Clark { 1057902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 1058902e6eb8SRob Clark } 1059902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 1060902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 1061902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1062902e6eb8SRob Clark { 1063902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 1064902e6eb8SRob Clark } 1065902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 1066902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 1067902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 1068902e6eb8SRob Clark { 1069902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 1070902e6eb8SRob Clark } 1071902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 1072902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 1073902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 1074902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 1075902e6eb8SRob Clark { 1076902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 1077902e6eb8SRob Clark } 1078902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 1079902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 1080902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 1081902e6eb8SRob Clark { 1082902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 1083902e6eb8SRob Clark } 1084902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 1085902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 1086902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 1087902e6eb8SRob Clark { 1088902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 1089902e6eb8SRob Clark } 1090902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 1091902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 1092902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 1093902e6eb8SRob Clark { 1094902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 1095902e6eb8SRob Clark } 1096902e6eb8SRob Clark 1097902e6eb8SRob Clark #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 1098902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 1099902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 1100902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 1101902e6eb8SRob Clark { 1102902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 1103902e6eb8SRob Clark } 1104902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 1105902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 1106902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 1107902e6eb8SRob Clark { 1108902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 1109902e6eb8SRob Clark } 1110902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 1111902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 1112902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 1113902e6eb8SRob Clark { 1114902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 1115902e6eb8SRob Clark } 1116902e6eb8SRob Clark 1117902e6eb8SRob Clark #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 1118902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 1119902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 1120902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 1121902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 1122902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 1123902e6eb8SRob Clark { 1124902e6eb8SRob Clark return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 1125902e6eb8SRob Clark } 1126902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 1127902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 1128902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1129902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1130902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1131902e6eb8SRob Clark 1132902e6eb8SRob Clark #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1133902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1134902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1135902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1136902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1137902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1138902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1139902e6eb8SRob Clark { 1140902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1141902e6eb8SRob Clark } 1142902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1143902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1144902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1145902e6eb8SRob Clark { 1146902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1147902e6eb8SRob Clark } 1148902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1149902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1150902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1151902e6eb8SRob Clark { 1152902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1153902e6eb8SRob Clark } 1154902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1155902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1156902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1157902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1158902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1159902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1160902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1161902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1162902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1163902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1164902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1165902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1166902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1167902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1168902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1169902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1170902e6eb8SRob Clark 1171902e6eb8SRob Clark #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1172902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1173902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1174902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1175902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1176902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1177902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1178902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1179902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1180902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1181902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1182902e6eb8SRob Clark 1183902e6eb8SRob Clark #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1184902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1185902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1186902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1187902e6eb8SRob Clark { 1188902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1189902e6eb8SRob Clark } 1190902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1191902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1192902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1193902e6eb8SRob Clark { 1194902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1195902e6eb8SRob Clark } 1196902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1197902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1198902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1199902e6eb8SRob Clark { 1200902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1201902e6eb8SRob Clark } 1202902e6eb8SRob Clark 1203902e6eb8SRob Clark #define REG_A2XX_RB_MODECONTROL 0x00002208 1204902e6eb8SRob Clark #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1205902e6eb8SRob Clark #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1206902e6eb8SRob Clark static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1207902e6eb8SRob Clark { 1208902e6eb8SRob Clark return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1209902e6eb8SRob Clark } 1210902e6eb8SRob Clark 1211902e6eb8SRob Clark #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1212902e6eb8SRob Clark 1213902e6eb8SRob Clark #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1214902e6eb8SRob Clark 1215902e6eb8SRob Clark #define REG_A2XX_CLEAR_COLOR 0x0000220b 1216902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1217902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1218902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1219902e6eb8SRob Clark { 1220902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1221902e6eb8SRob Clark } 1222902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1223902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1224902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1225902e6eb8SRob Clark { 1226902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1227902e6eb8SRob Clark } 1228902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1229902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1230902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1231902e6eb8SRob Clark { 1232902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1233902e6eb8SRob Clark } 1234902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1235902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1236902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1237902e6eb8SRob Clark { 1238902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1239902e6eb8SRob Clark } 1240902e6eb8SRob Clark 1241902e6eb8SRob Clark #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1242902e6eb8SRob Clark 1243902e6eb8SRob Clark #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1244902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1245902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1246902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1247902e6eb8SRob Clark { 1248bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1249902e6eb8SRob Clark } 1250902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1251902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1252902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1253902e6eb8SRob Clark { 1254bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1255902e6eb8SRob Clark } 1256902e6eb8SRob Clark 1257902e6eb8SRob Clark #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1258902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1259902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1260902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1261902e6eb8SRob Clark { 1262bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1263902e6eb8SRob Clark } 1264902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1265902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1266902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1267902e6eb8SRob Clark { 1268bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1269902e6eb8SRob Clark } 1270902e6eb8SRob Clark 1271902e6eb8SRob Clark #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1272902e6eb8SRob Clark #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1273902e6eb8SRob Clark #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1274902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1275902e6eb8SRob Clark { 1276bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1277902e6eb8SRob Clark } 1278902e6eb8SRob Clark 1279902e6eb8SRob Clark #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1280902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1281902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1282902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1283902e6eb8SRob Clark { 1284902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1285902e6eb8SRob Clark } 1286902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1287902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1288902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1289902e6eb8SRob Clark { 1290902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1291902e6eb8SRob Clark } 1292902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1293902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1294902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1295902e6eb8SRob Clark { 1296902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1297902e6eb8SRob Clark } 1298902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1299902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1300902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1301902e6eb8SRob Clark { 1302902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1303902e6eb8SRob Clark } 1304902e6eb8SRob Clark 1305902e6eb8SRob Clark #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1306902e6eb8SRob Clark 1307902e6eb8SRob Clark #define REG_A2XX_VGT_ENHANCE 0x00002294 1308902e6eb8SRob Clark 1309902e6eb8SRob Clark #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1310902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1311902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1312902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1313902e6eb8SRob Clark { 1314902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1315902e6eb8SRob Clark } 1316902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1317902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1318902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1319902e6eb8SRob Clark 1320902e6eb8SRob Clark #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1321902e6eb8SRob Clark 1322902e6eb8SRob Clark #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1323902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1324902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1325902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1326902e6eb8SRob Clark { 1327902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1328902e6eb8SRob Clark } 1329902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1330902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1331902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1332902e6eb8SRob Clark { 1333902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1334902e6eb8SRob Clark } 1335902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1336902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1337902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1338902e6eb8SRob Clark { 1339902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1340902e6eb8SRob Clark } 1341902e6eb8SRob Clark 1342902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1343902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1344902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1345902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1346902e6eb8SRob Clark { 1347902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1348902e6eb8SRob Clark } 1349902e6eb8SRob Clark 1350902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1351902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1352902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1353902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1354902e6eb8SRob Clark { 1355902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1356902e6eb8SRob Clark } 1357902e6eb8SRob Clark 1358902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1359902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1360902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1361902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1362902e6eb8SRob Clark { 1363902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1364902e6eb8SRob Clark } 1365902e6eb8SRob Clark 1366902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1367902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1368902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1369902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1370902e6eb8SRob Clark { 1371902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1372902e6eb8SRob Clark } 1373902e6eb8SRob Clark 1374902e6eb8SRob Clark #define REG_A2XX_SQ_VS_CONST 0x00002307 1375902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1376902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1377902e6eb8SRob Clark static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1378902e6eb8SRob Clark { 1379902e6eb8SRob Clark return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1380902e6eb8SRob Clark } 1381902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1382902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1383902e6eb8SRob Clark static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1384902e6eb8SRob Clark { 1385902e6eb8SRob Clark return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1386902e6eb8SRob Clark } 1387902e6eb8SRob Clark 1388902e6eb8SRob Clark #define REG_A2XX_SQ_PS_CONST 0x00002308 1389902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1390902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1391902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1392902e6eb8SRob Clark { 1393902e6eb8SRob Clark return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1394902e6eb8SRob Clark } 1395902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1396902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1397902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1398902e6eb8SRob Clark { 1399902e6eb8SRob Clark return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1400902e6eb8SRob Clark } 1401902e6eb8SRob Clark 1402902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1403902e6eb8SRob Clark 1404902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1405902e6eb8SRob Clark 1406902e6eb8SRob Clark #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1407902e6eb8SRob Clark 1408902e6eb8SRob Clark #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1409902e6eb8SRob Clark 1410902e6eb8SRob Clark #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1411902e6eb8SRob Clark 1412902e6eb8SRob Clark #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1413902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1414902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1415902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1416902e6eb8SRob Clark { 1417902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1418902e6eb8SRob Clark } 1419902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1420902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1421902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1422902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1423902e6eb8SRob Clark { 1424902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1425902e6eb8SRob Clark } 1426902e6eb8SRob Clark 1427902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1428902e6eb8SRob Clark 1429902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1430902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1431902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1432902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1433902e6eb8SRob Clark { 1434902e6eb8SRob Clark return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1435902e6eb8SRob Clark } 1436902e6eb8SRob Clark 1437902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1438902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1439902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1440902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1441902e6eb8SRob Clark { 1442902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1443902e6eb8SRob Clark } 1444902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1445902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1446902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1447902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1448902e6eb8SRob Clark { 1449902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1450902e6eb8SRob Clark } 1451902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1452902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1453902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1454902e6eb8SRob Clark { 1455902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1456902e6eb8SRob Clark } 1457902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1458902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1459902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1460902e6eb8SRob Clark { 1461902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1462902e6eb8SRob Clark } 1463902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1464902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1465902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1466902e6eb8SRob Clark { 1467902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1468902e6eb8SRob Clark } 1469902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1470902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1471902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1472902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1473902e6eb8SRob Clark 1474902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1475902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1476902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1477902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1478902e6eb8SRob Clark { 1479902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1480902e6eb8SRob Clark } 1481902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1482902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1483902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1484902e6eb8SRob Clark { 1485902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1486902e6eb8SRob Clark } 1487902e6eb8SRob Clark 1488902e6eb8SRob Clark #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1489902e6eb8SRob Clark 1490902e6eb8SRob Clark #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1491902e6eb8SRob Clark 1492902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1493902e6eb8SRob Clark 1494902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1495902e6eb8SRob Clark 1496902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1497902e6eb8SRob Clark 1498902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1499902e6eb8SRob Clark 1500902e6eb8SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1501902e6eb8SRob Clark 1502902e6eb8SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1503902e6eb8SRob Clark 1504902e6eb8SRob Clark #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1505902e6eb8SRob Clark 1506902e6eb8SRob Clark #define REG_A2XX_SQ_FETCH_0 0x00004800 1507902e6eb8SRob Clark 1508902e6eb8SRob Clark #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1509902e6eb8SRob Clark 1510902e6eb8SRob Clark #define REG_A2XX_SQ_CF_LOOP 0x00004908 1511902e6eb8SRob Clark 1512902e6eb8SRob Clark #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1513902e6eb8SRob Clark 1514902e6eb8SRob Clark #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1515902e6eb8SRob Clark 1516902e6eb8SRob Clark #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1517902e6eb8SRob Clark 1518902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_0 0x00000000 1519902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1520902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1521902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1522902e6eb8SRob Clark { 1523902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1524902e6eb8SRob Clark } 1525902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1526902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1527902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1528902e6eb8SRob Clark { 1529902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1530902e6eb8SRob Clark } 1531902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1532902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1533902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1534902e6eb8SRob Clark { 1535902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1536902e6eb8SRob Clark } 1537902e6eb8SRob Clark #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1538902e6eb8SRob Clark #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1539902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1540902e6eb8SRob Clark { 1541902e6eb8SRob Clark return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1542902e6eb8SRob Clark } 1543902e6eb8SRob Clark 1544902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_1 0x00000001 1545902e6eb8SRob Clark 1546902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_2 0x00000002 1547902e6eb8SRob Clark #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1548902e6eb8SRob Clark #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1549902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1550902e6eb8SRob Clark { 1551902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1552902e6eb8SRob Clark } 1553902e6eb8SRob Clark #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1554902e6eb8SRob Clark #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1555902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1556902e6eb8SRob Clark { 1557902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1558902e6eb8SRob Clark } 1559902e6eb8SRob Clark 1560902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_3 0x00000003 1561902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1562902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1563902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1564902e6eb8SRob Clark { 1565902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1566902e6eb8SRob Clark } 1567902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1568902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1569902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1570902e6eb8SRob Clark { 1571902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1572902e6eb8SRob Clark } 1573902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1574902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1575902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1576902e6eb8SRob Clark { 1577902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1578902e6eb8SRob Clark } 1579902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1580902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1581902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1582902e6eb8SRob Clark { 1583902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1584902e6eb8SRob Clark } 1585902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1586902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1587902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1588902e6eb8SRob Clark { 1589902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1590902e6eb8SRob Clark } 1591902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1592902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1593902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1594902e6eb8SRob Clark { 1595902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1596902e6eb8SRob Clark } 1597902e6eb8SRob Clark 1598902e6eb8SRob Clark 1599902e6eb8SRob Clark #endif /* A2XX_XML */ 1600