1902e6eb8SRob Clark #ifndef A2XX_XML 2902e6eb8SRob Clark #define A2XX_XML 3902e6eb8SRob Clark 4902e6eb8SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5902e6eb8SRob Clark 6902e6eb8SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 722ba8b6bSRob Clark http://github.com/freedreno/envytools/ 822ba8b6bSRob Clark git clone https://github.com/freedreno/envytools.git 9902e6eb8SRob Clark 10902e6eb8SRob Clark The rules-ng-ng source files this header was generated from are: 11902e6eb8SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 12902e6eb8SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 1322ba8b6bSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 14902e6eb8SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 1522ba8b6bSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 1622ba8b6bSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 17902e6eb8SRob Clark 18902e6eb8SRob Clark Copyright (C) 2013 by the following authors: 19902e6eb8SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 20902e6eb8SRob Clark 21902e6eb8SRob Clark Permission is hereby granted, free of charge, to any person obtaining 22902e6eb8SRob Clark a copy of this software and associated documentation files (the 23902e6eb8SRob Clark "Software"), to deal in the Software without restriction, including 24902e6eb8SRob Clark without limitation the rights to use, copy, modify, merge, publish, 25902e6eb8SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 26902e6eb8SRob Clark permit persons to whom the Software is furnished to do so, subject to 27902e6eb8SRob Clark the following conditions: 28902e6eb8SRob Clark 29902e6eb8SRob Clark The above copyright notice and this permission notice (including the 30902e6eb8SRob Clark next paragraph) shall be included in all copies or substantial 31902e6eb8SRob Clark portions of the Software. 32902e6eb8SRob Clark 33902e6eb8SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34902e6eb8SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 35902e6eb8SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 36902e6eb8SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 37902e6eb8SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 38902e6eb8SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 39902e6eb8SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 40902e6eb8SRob Clark */ 41902e6eb8SRob Clark 42902e6eb8SRob Clark 43902e6eb8SRob Clark enum a2xx_rb_dither_type { 44902e6eb8SRob Clark DITHER_PIXEL = 0, 45902e6eb8SRob Clark DITHER_SUBPIXEL = 1, 46902e6eb8SRob Clark }; 47902e6eb8SRob Clark 48902e6eb8SRob Clark enum a2xx_colorformatx { 49902e6eb8SRob Clark COLORX_4_4_4_4 = 0, 50902e6eb8SRob Clark COLORX_1_5_5_5 = 1, 51902e6eb8SRob Clark COLORX_5_6_5 = 2, 52902e6eb8SRob Clark COLORX_8 = 3, 53902e6eb8SRob Clark COLORX_8_8 = 4, 54902e6eb8SRob Clark COLORX_8_8_8_8 = 5, 55902e6eb8SRob Clark COLORX_S8_8_8_8 = 6, 56902e6eb8SRob Clark COLORX_16_FLOAT = 7, 57902e6eb8SRob Clark COLORX_16_16_FLOAT = 8, 58902e6eb8SRob Clark COLORX_16_16_16_16_FLOAT = 9, 59902e6eb8SRob Clark COLORX_32_FLOAT = 10, 60902e6eb8SRob Clark COLORX_32_32_FLOAT = 11, 61902e6eb8SRob Clark COLORX_32_32_32_32_FLOAT = 12, 62902e6eb8SRob Clark COLORX_2_3_3 = 13, 63902e6eb8SRob Clark COLORX_8_8_8 = 14, 64902e6eb8SRob Clark }; 65902e6eb8SRob Clark 66902e6eb8SRob Clark enum a2xx_sq_surfaceformat { 67902e6eb8SRob Clark FMT_1_REVERSE = 0, 68902e6eb8SRob Clark FMT_1 = 1, 69902e6eb8SRob Clark FMT_8 = 2, 70902e6eb8SRob Clark FMT_1_5_5_5 = 3, 71902e6eb8SRob Clark FMT_5_6_5 = 4, 72902e6eb8SRob Clark FMT_6_5_5 = 5, 73902e6eb8SRob Clark FMT_8_8_8_8 = 6, 74902e6eb8SRob Clark FMT_2_10_10_10 = 7, 75902e6eb8SRob Clark FMT_8_A = 8, 76902e6eb8SRob Clark FMT_8_B = 9, 77902e6eb8SRob Clark FMT_8_8 = 10, 78902e6eb8SRob Clark FMT_Cr_Y1_Cb_Y0 = 11, 79902e6eb8SRob Clark FMT_Y1_Cr_Y0_Cb = 12, 80902e6eb8SRob Clark FMT_5_5_5_1 = 13, 81902e6eb8SRob Clark FMT_8_8_8_8_A = 14, 82902e6eb8SRob Clark FMT_4_4_4_4 = 15, 83902e6eb8SRob Clark FMT_10_11_11 = 16, 84902e6eb8SRob Clark FMT_11_11_10 = 17, 85902e6eb8SRob Clark FMT_DXT1 = 18, 86902e6eb8SRob Clark FMT_DXT2_3 = 19, 87902e6eb8SRob Clark FMT_DXT4_5 = 20, 88902e6eb8SRob Clark FMT_24_8 = 22, 89902e6eb8SRob Clark FMT_24_8_FLOAT = 23, 90902e6eb8SRob Clark FMT_16 = 24, 91902e6eb8SRob Clark FMT_16_16 = 25, 92902e6eb8SRob Clark FMT_16_16_16_16 = 26, 93902e6eb8SRob Clark FMT_16_EXPAND = 27, 94902e6eb8SRob Clark FMT_16_16_EXPAND = 28, 95902e6eb8SRob Clark FMT_16_16_16_16_EXPAND = 29, 96902e6eb8SRob Clark FMT_16_FLOAT = 30, 97902e6eb8SRob Clark FMT_16_16_FLOAT = 31, 98902e6eb8SRob Clark FMT_16_16_16_16_FLOAT = 32, 99902e6eb8SRob Clark FMT_32 = 33, 100902e6eb8SRob Clark FMT_32_32 = 34, 101902e6eb8SRob Clark FMT_32_32_32_32 = 35, 102902e6eb8SRob Clark FMT_32_FLOAT = 36, 103902e6eb8SRob Clark FMT_32_32_FLOAT = 37, 104902e6eb8SRob Clark FMT_32_32_32_32_FLOAT = 38, 105902e6eb8SRob Clark FMT_32_AS_8 = 39, 106902e6eb8SRob Clark FMT_32_AS_8_8 = 40, 107902e6eb8SRob Clark FMT_16_MPEG = 41, 108902e6eb8SRob Clark FMT_16_16_MPEG = 42, 109902e6eb8SRob Clark FMT_8_INTERLACED = 43, 110902e6eb8SRob Clark FMT_32_AS_8_INTERLACED = 44, 111902e6eb8SRob Clark FMT_32_AS_8_8_INTERLACED = 45, 112902e6eb8SRob Clark FMT_16_INTERLACED = 46, 113902e6eb8SRob Clark FMT_16_MPEG_INTERLACED = 47, 114902e6eb8SRob Clark FMT_16_16_MPEG_INTERLACED = 48, 115902e6eb8SRob Clark FMT_DXN = 49, 116902e6eb8SRob Clark FMT_8_8_8_8_AS_16_16_16_16 = 50, 117902e6eb8SRob Clark FMT_DXT1_AS_16_16_16_16 = 51, 118902e6eb8SRob Clark FMT_DXT2_3_AS_16_16_16_16 = 52, 119902e6eb8SRob Clark FMT_DXT4_5_AS_16_16_16_16 = 53, 120902e6eb8SRob Clark FMT_2_10_10_10_AS_16_16_16_16 = 54, 121902e6eb8SRob Clark FMT_10_11_11_AS_16_16_16_16 = 55, 122902e6eb8SRob Clark FMT_11_11_10_AS_16_16_16_16 = 56, 123902e6eb8SRob Clark FMT_32_32_32_FLOAT = 57, 124902e6eb8SRob Clark FMT_DXT3A = 58, 125902e6eb8SRob Clark FMT_DXT5A = 59, 126902e6eb8SRob Clark FMT_CTX1 = 60, 127902e6eb8SRob Clark FMT_DXT3A_AS_1_1_1_1 = 61, 128902e6eb8SRob Clark }; 129902e6eb8SRob Clark 130902e6eb8SRob Clark enum a2xx_sq_ps_vtx_mode { 131902e6eb8SRob Clark POSITION_1_VECTOR = 0, 132902e6eb8SRob Clark POSITION_2_VECTORS_UNUSED = 1, 133902e6eb8SRob Clark POSITION_2_VECTORS_SPRITE = 2, 134902e6eb8SRob Clark POSITION_2_VECTORS_EDGE = 3, 135902e6eb8SRob Clark POSITION_2_VECTORS_KILL = 4, 136902e6eb8SRob Clark POSITION_2_VECTORS_SPRITE_KILL = 5, 137902e6eb8SRob Clark POSITION_2_VECTORS_EDGE_KILL = 6, 138902e6eb8SRob Clark MULTIPASS = 7, 139902e6eb8SRob Clark }; 140902e6eb8SRob Clark 141902e6eb8SRob Clark enum a2xx_sq_sample_cntl { 142902e6eb8SRob Clark CENTROIDS_ONLY = 0, 143902e6eb8SRob Clark CENTERS_ONLY = 1, 144902e6eb8SRob Clark CENTROIDS_AND_CENTERS = 2, 145902e6eb8SRob Clark }; 146902e6eb8SRob Clark 147902e6eb8SRob Clark enum a2xx_dx_clip_space { 148902e6eb8SRob Clark DXCLIP_OPENGL = 0, 149902e6eb8SRob Clark DXCLIP_DIRECTX = 1, 150902e6eb8SRob Clark }; 151902e6eb8SRob Clark 152902e6eb8SRob Clark enum a2xx_pa_su_sc_polymode { 153902e6eb8SRob Clark POLY_DISABLED = 0, 154902e6eb8SRob Clark POLY_DUALMODE = 1, 155902e6eb8SRob Clark }; 156902e6eb8SRob Clark 157902e6eb8SRob Clark enum a2xx_rb_edram_mode { 158902e6eb8SRob Clark EDRAM_NOP = 0, 159902e6eb8SRob Clark COLOR_DEPTH = 4, 160902e6eb8SRob Clark DEPTH_ONLY = 5, 161902e6eb8SRob Clark EDRAM_COPY = 6, 162902e6eb8SRob Clark }; 163902e6eb8SRob Clark 164902e6eb8SRob Clark enum a2xx_pa_sc_pattern_bit_order { 165902e6eb8SRob Clark LITTLE = 0, 166902e6eb8SRob Clark BIG = 1, 167902e6eb8SRob Clark }; 168902e6eb8SRob Clark 169902e6eb8SRob Clark enum a2xx_pa_sc_auto_reset_cntl { 170902e6eb8SRob Clark NEVER = 0, 171902e6eb8SRob Clark EACH_PRIMITIVE = 1, 172902e6eb8SRob Clark EACH_PACKET = 2, 173902e6eb8SRob Clark }; 174902e6eb8SRob Clark 175902e6eb8SRob Clark enum a2xx_pa_pixcenter { 176902e6eb8SRob Clark PIXCENTER_D3D = 0, 177902e6eb8SRob Clark PIXCENTER_OGL = 1, 178902e6eb8SRob Clark }; 179902e6eb8SRob Clark 180902e6eb8SRob Clark enum a2xx_pa_roundmode { 181902e6eb8SRob Clark TRUNCATE = 0, 182902e6eb8SRob Clark ROUND = 1, 183902e6eb8SRob Clark ROUNDTOEVEN = 2, 184902e6eb8SRob Clark ROUNDTOODD = 3, 185902e6eb8SRob Clark }; 186902e6eb8SRob Clark 187902e6eb8SRob Clark enum a2xx_pa_quantmode { 188902e6eb8SRob Clark ONE_SIXTEENTH = 0, 189902e6eb8SRob Clark ONE_EIGTH = 1, 190902e6eb8SRob Clark ONE_QUARTER = 2, 191902e6eb8SRob Clark ONE_HALF = 3, 192902e6eb8SRob Clark ONE = 4, 193902e6eb8SRob Clark }; 194902e6eb8SRob Clark 195902e6eb8SRob Clark enum a2xx_rb_copy_sample_select { 196902e6eb8SRob Clark SAMPLE_0 = 0, 197902e6eb8SRob Clark SAMPLE_1 = 1, 198902e6eb8SRob Clark SAMPLE_2 = 2, 199902e6eb8SRob Clark SAMPLE_3 = 3, 200902e6eb8SRob Clark SAMPLE_01 = 4, 201902e6eb8SRob Clark SAMPLE_23 = 5, 202902e6eb8SRob Clark SAMPLE_0123 = 6, 203902e6eb8SRob Clark }; 204902e6eb8SRob Clark 205902e6eb8SRob Clark enum sq_tex_clamp { 206902e6eb8SRob Clark SQ_TEX_WRAP = 0, 207902e6eb8SRob Clark SQ_TEX_MIRROR = 1, 208902e6eb8SRob Clark SQ_TEX_CLAMP_LAST_TEXEL = 2, 209902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 210902e6eb8SRob Clark SQ_TEX_CLAMP_HALF_BORDER = 4, 211902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 212902e6eb8SRob Clark SQ_TEX_CLAMP_BORDER = 6, 213902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_BORDER = 7, 214902e6eb8SRob Clark }; 215902e6eb8SRob Clark 216902e6eb8SRob Clark enum sq_tex_swiz { 217902e6eb8SRob Clark SQ_TEX_X = 0, 218902e6eb8SRob Clark SQ_TEX_Y = 1, 219902e6eb8SRob Clark SQ_TEX_Z = 2, 220902e6eb8SRob Clark SQ_TEX_W = 3, 221902e6eb8SRob Clark SQ_TEX_ZERO = 4, 222902e6eb8SRob Clark SQ_TEX_ONE = 5, 223902e6eb8SRob Clark }; 224902e6eb8SRob Clark 225902e6eb8SRob Clark enum sq_tex_filter { 226902e6eb8SRob Clark SQ_TEX_FILTER_POINT = 0, 227902e6eb8SRob Clark SQ_TEX_FILTER_BILINEAR = 1, 228902e6eb8SRob Clark SQ_TEX_FILTER_BICUBIC = 2, 229902e6eb8SRob Clark }; 230902e6eb8SRob Clark 231902e6eb8SRob Clark #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 232902e6eb8SRob Clark 233902e6eb8SRob Clark #define REG_A2XX_RBBM_CNTL 0x0000003b 234902e6eb8SRob Clark 235902e6eb8SRob Clark #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 236902e6eb8SRob Clark 237902e6eb8SRob Clark #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 238902e6eb8SRob Clark 239902e6eb8SRob Clark #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 240902e6eb8SRob Clark 241902e6eb8SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 242902e6eb8SRob Clark 243902e6eb8SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 244902e6eb8SRob Clark 245902e6eb8SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 246902e6eb8SRob Clark 247902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG 0x0000039b 248902e6eb8SRob Clark 249902e6eb8SRob Clark #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 250902e6eb8SRob Clark 251902e6eb8SRob Clark #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 252902e6eb8SRob Clark 253902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 254902e6eb8SRob Clark 255902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 256902e6eb8SRob Clark 257902e6eb8SRob Clark #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 258902e6eb8SRob Clark 259902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 260902e6eb8SRob Clark 261902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 262902e6eb8SRob Clark 263902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_ACK 0x000003b6 264902e6eb8SRob Clark 265902e6eb8SRob Clark #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 266902e6eb8SRob Clark 267902e6eb8SRob Clark #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 268902e6eb8SRob Clark 269902e6eb8SRob Clark #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 270902e6eb8SRob Clark 271902e6eb8SRob Clark #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 272902e6eb8SRob Clark 273902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 274902e6eb8SRob Clark 275902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 276902e6eb8SRob Clark 277902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 278902e6eb8SRob Clark 279902e6eb8SRob Clark #define REG_A2XX_CP_ST_BASE 0x0000044d 280902e6eb8SRob Clark 281902e6eb8SRob Clark #define REG_A2XX_CP_ST_BUFSZ 0x0000044e 282902e6eb8SRob Clark 283902e6eb8SRob Clark #define REG_A2XX_CP_IB1_BASE 0x00000458 284902e6eb8SRob Clark 285902e6eb8SRob Clark #define REG_A2XX_CP_IB1_BUFSZ 0x00000459 286902e6eb8SRob Clark 287902e6eb8SRob Clark #define REG_A2XX_CP_IB2_BASE 0x0000045a 288902e6eb8SRob Clark 289902e6eb8SRob Clark #define REG_A2XX_CP_IB2_BUFSZ 0x0000045b 290902e6eb8SRob Clark 291902e6eb8SRob Clark #define REG_A2XX_CP_STAT 0x0000047f 292902e6eb8SRob Clark 293902e6eb8SRob Clark #define REG_A2XX_RBBM_STATUS 0x000005d0 294902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 295902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 296902e6eb8SRob Clark static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 297902e6eb8SRob Clark { 298902e6eb8SRob Clark return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 299902e6eb8SRob Clark } 300902e6eb8SRob Clark #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 301902e6eb8SRob Clark #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 302902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 303902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 304902e6eb8SRob Clark #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 305902e6eb8SRob Clark #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 306902e6eb8SRob Clark #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 307902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 308902e6eb8SRob Clark #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 309902e6eb8SRob Clark #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 310902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 311902e6eb8SRob Clark #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 312902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 313902e6eb8SRob Clark #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 314902e6eb8SRob Clark #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 315902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 316902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 317902e6eb8SRob Clark #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 318902e6eb8SRob Clark #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 319902e6eb8SRob Clark 32022ba8b6bSRob Clark #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 32122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 32222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 32322ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 32422ba8b6bSRob Clark { 32522ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 32622ba8b6bSRob Clark } 32722ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 32822ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 32922ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 33022ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 33122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 33222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 33322ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 33422ba8b6bSRob Clark { 33522ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 33622ba8b6bSRob Clark } 33722ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 33822ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 33922ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 34022ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 34122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 34222ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 34322ba8b6bSRob Clark { 34422ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 34522ba8b6bSRob Clark } 34622ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 34722ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 34822ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 34922ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 35022ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 35122ba8b6bSRob Clark 352902e6eb8SRob Clark #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 353902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 354902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 355902e6eb8SRob Clark static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 356902e6eb8SRob Clark { 357902e6eb8SRob Clark return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 358902e6eb8SRob Clark } 359902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 360902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 361902e6eb8SRob Clark static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 362902e6eb8SRob Clark { 363902e6eb8SRob Clark return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 364902e6eb8SRob Clark } 365902e6eb8SRob Clark 366902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 367902e6eb8SRob Clark 368902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 369902e6eb8SRob Clark 370902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 371902e6eb8SRob Clark 372902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 373902e6eb8SRob Clark 374902e6eb8SRob Clark #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 375902e6eb8SRob Clark 376902e6eb8SRob Clark #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 377902e6eb8SRob Clark 378902e6eb8SRob Clark #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 379902e6eb8SRob Clark 380902e6eb8SRob Clark #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 381902e6eb8SRob Clark 382902e6eb8SRob Clark #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 383902e6eb8SRob Clark 384902e6eb8SRob Clark #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 385902e6eb8SRob Clark 386902e6eb8SRob Clark #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 387902e6eb8SRob Clark 388902e6eb8SRob Clark #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 389902e6eb8SRob Clark 390902e6eb8SRob Clark #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 391902e6eb8SRob Clark 392902e6eb8SRob Clark #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 393902e6eb8SRob Clark 394902e6eb8SRob Clark #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 395902e6eb8SRob Clark 396902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 397902e6eb8SRob Clark 398902e6eb8SRob Clark #define REG_A2XX_SQ_INT_CNTL 0x00000d34 399902e6eb8SRob Clark 400902e6eb8SRob Clark #define REG_A2XX_SQ_INT_STATUS 0x00000d35 401902e6eb8SRob Clark 402902e6eb8SRob Clark #define REG_A2XX_SQ_INT_ACK 0x00000d36 403902e6eb8SRob Clark 404902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 405902e6eb8SRob Clark 406902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 407902e6eb8SRob Clark 408902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 409902e6eb8SRob Clark 410902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 411902e6eb8SRob Clark 412902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 413902e6eb8SRob Clark 414902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 415902e6eb8SRob Clark 416902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 417902e6eb8SRob Clark 418902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 419902e6eb8SRob Clark 420902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 421902e6eb8SRob Clark 422902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 423902e6eb8SRob Clark 424902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 425902e6eb8SRob Clark 426902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 427902e6eb8SRob Clark 428902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 429902e6eb8SRob Clark 430902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 431902e6eb8SRob Clark 432902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 433902e6eb8SRob Clark 434902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 435902e6eb8SRob Clark 436902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 437902e6eb8SRob Clark 438902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 439902e6eb8SRob Clark 440902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 441902e6eb8SRob Clark 442902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 443902e6eb8SRob Clark 444902e6eb8SRob Clark #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 445902e6eb8SRob Clark #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 446902e6eb8SRob Clark 447902e6eb8SRob Clark #define REG_A2XX_TP0_CHICKEN 0x00000e1e 448902e6eb8SRob Clark 449902e6eb8SRob Clark #define REG_A2XX_RB_BC_CONTROL 0x00000f01 450902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 451902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 452902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 453902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 454902e6eb8SRob Clark { 455902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 456902e6eb8SRob Clark } 457902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 458902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 459902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 460902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 461902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 462902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 463902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 464902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 465902e6eb8SRob Clark { 466902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 467902e6eb8SRob Clark } 468902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 469902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 470902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 471902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 472902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 473902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 474902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 475902e6eb8SRob Clark { 476902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 477902e6eb8SRob Clark } 478902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 479902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 480902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 481902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 482902e6eb8SRob Clark { 483902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 484902e6eb8SRob Clark } 485902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 486902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 487902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 488902e6eb8SRob Clark { 489902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 490902e6eb8SRob Clark } 491902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 492902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 493902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 494902e6eb8SRob Clark 495902e6eb8SRob Clark #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 496902e6eb8SRob Clark 497902e6eb8SRob Clark #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 498902e6eb8SRob Clark 499902e6eb8SRob Clark #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 500902e6eb8SRob Clark 501902e6eb8SRob Clark #define REG_A2XX_RB_SURFACE_INFO 0x00002000 502902e6eb8SRob Clark 503902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_INFO 0x00002001 504902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 505902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 506902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 507902e6eb8SRob Clark { 508902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 509902e6eb8SRob Clark } 510902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 511902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 512902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 513902e6eb8SRob Clark { 514902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 515902e6eb8SRob Clark } 516902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 517902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 518902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 519902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 520902e6eb8SRob Clark { 521902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 522902e6eb8SRob Clark } 523902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 524902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 525902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 526902e6eb8SRob Clark { 527902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 528902e6eb8SRob Clark } 529902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 530902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 531902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 532902e6eb8SRob Clark { 533902e6eb8SRob Clark return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 534902e6eb8SRob Clark } 535902e6eb8SRob Clark 536902e6eb8SRob Clark #define REG_A2XX_RB_DEPTH_INFO 0x00002002 537902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 538902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 539902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 540902e6eb8SRob Clark { 541902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 542902e6eb8SRob Clark } 543902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 544902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 545902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 546902e6eb8SRob Clark { 547902e6eb8SRob Clark return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 548902e6eb8SRob Clark } 549902e6eb8SRob Clark 550902e6eb8SRob Clark #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 551902e6eb8SRob Clark 552902e6eb8SRob Clark #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 553902e6eb8SRob Clark 554902e6eb8SRob Clark #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 555902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 556902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 557902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 558902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 559902e6eb8SRob Clark { 560902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 561902e6eb8SRob Clark } 562902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 563902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 564902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 565902e6eb8SRob Clark { 566902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 567902e6eb8SRob Clark } 568902e6eb8SRob Clark 569902e6eb8SRob Clark #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 570902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 571902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 572902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 573902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 574902e6eb8SRob Clark { 575902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 576902e6eb8SRob Clark } 577902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 578902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 579902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 580902e6eb8SRob Clark { 581902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 582902e6eb8SRob Clark } 583902e6eb8SRob Clark 584902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 585902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 586902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 587902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 588902e6eb8SRob Clark { 589902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 590902e6eb8SRob Clark } 591902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 592902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 593902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 594902e6eb8SRob Clark { 595902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 596902e6eb8SRob Clark } 597902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 598902e6eb8SRob Clark 599902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 600902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 601902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 602902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 603902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 604902e6eb8SRob Clark { 605902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 606902e6eb8SRob Clark } 607902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 608902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 609902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 610902e6eb8SRob Clark { 611902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 612902e6eb8SRob Clark } 613902e6eb8SRob Clark 614902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 615902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 616902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 617902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 618902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 619902e6eb8SRob Clark { 620902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 621902e6eb8SRob Clark } 622902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 623902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 624902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 625902e6eb8SRob Clark { 626902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 627902e6eb8SRob Clark } 628902e6eb8SRob Clark 629902e6eb8SRob Clark #define REG_A2XX_UNKNOWN_2010 0x00002010 630902e6eb8SRob Clark 631902e6eb8SRob Clark #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 632902e6eb8SRob Clark 633902e6eb8SRob Clark #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 634902e6eb8SRob Clark 635902e6eb8SRob Clark #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 636902e6eb8SRob Clark 637902e6eb8SRob Clark #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 638902e6eb8SRob Clark 639902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_MASK 0x00002104 640902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 641902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 642902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 643902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 644902e6eb8SRob Clark 645902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_RED 0x00002105 646902e6eb8SRob Clark 647902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_GREEN 0x00002106 648902e6eb8SRob Clark 649902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_BLUE 0x00002107 650902e6eb8SRob Clark 651902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 652902e6eb8SRob Clark 653902e6eb8SRob Clark #define REG_A2XX_RB_FOG_COLOR 0x00002109 654902e6eb8SRob Clark 655902e6eb8SRob Clark #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 656902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 657902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 658902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 659902e6eb8SRob Clark { 660902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 661902e6eb8SRob Clark } 662902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 663902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 664902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 665902e6eb8SRob Clark { 666902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 667902e6eb8SRob Clark } 668902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 669902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 670902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 671902e6eb8SRob Clark { 672902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 673902e6eb8SRob Clark } 674902e6eb8SRob Clark 675902e6eb8SRob Clark #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 676902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 677902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 678902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 679902e6eb8SRob Clark { 680902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 681902e6eb8SRob Clark } 682902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 683902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 684902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 685902e6eb8SRob Clark { 686902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 687902e6eb8SRob Clark } 688902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 689902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 690902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 691902e6eb8SRob Clark { 692902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 693902e6eb8SRob Clark } 694902e6eb8SRob Clark 695902e6eb8SRob Clark #define REG_A2XX_RB_ALPHA_REF 0x0000210e 696902e6eb8SRob Clark 697902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 698902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 699902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 700902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 701902e6eb8SRob Clark { 702902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 703902e6eb8SRob Clark } 704902e6eb8SRob Clark 705902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 706902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 707902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 708902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 709902e6eb8SRob Clark { 710902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 711902e6eb8SRob Clark } 712902e6eb8SRob Clark 713902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 714902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 715902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 716902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 717902e6eb8SRob Clark { 718902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 719902e6eb8SRob Clark } 720902e6eb8SRob Clark 721902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 722902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 723902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 724902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 725902e6eb8SRob Clark { 726902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 727902e6eb8SRob Clark } 728902e6eb8SRob Clark 729902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 730902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 731902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 732902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 733902e6eb8SRob Clark { 734902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 735902e6eb8SRob Clark } 736902e6eb8SRob Clark 737902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 738902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 739902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 740902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 741902e6eb8SRob Clark { 742902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 743902e6eb8SRob Clark } 744902e6eb8SRob Clark 745902e6eb8SRob Clark #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 746902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 747902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 748902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 749902e6eb8SRob Clark { 750902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 751902e6eb8SRob Clark } 752902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 753902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 754902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 755902e6eb8SRob Clark { 756902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 757902e6eb8SRob Clark } 758902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 759902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 760902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 761902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 762902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 763902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 764902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 765902e6eb8SRob Clark { 766902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 767902e6eb8SRob Clark } 768902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 769902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 770902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 771902e6eb8SRob Clark { 772902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 773902e6eb8SRob Clark } 774902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 775902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 776902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 777902e6eb8SRob Clark { 778902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 779902e6eb8SRob Clark } 780902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 781902e6eb8SRob Clark 782902e6eb8SRob Clark #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 783902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 784902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 785902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 786902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 787902e6eb8SRob Clark static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 788902e6eb8SRob Clark { 789902e6eb8SRob Clark return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 790902e6eb8SRob Clark } 791902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 792902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 793902e6eb8SRob Clark static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 794902e6eb8SRob Clark { 795902e6eb8SRob Clark return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 796902e6eb8SRob Clark } 797902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 798902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 799902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 800902e6eb8SRob Clark 801902e6eb8SRob Clark #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 802902e6eb8SRob Clark 803902e6eb8SRob Clark #define REG_A2XX_SQ_WRAPPING_0 0x00002183 804902e6eb8SRob Clark 805902e6eb8SRob Clark #define REG_A2XX_SQ_WRAPPING_1 0x00002184 806902e6eb8SRob Clark 807902e6eb8SRob Clark #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 808902e6eb8SRob Clark 809902e6eb8SRob Clark #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 810902e6eb8SRob Clark 811902e6eb8SRob Clark #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 812902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 813902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 814902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 815902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 816902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 817902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 818902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 819902e6eb8SRob Clark { 820902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 821902e6eb8SRob Clark } 822902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 823902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 824902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 825902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 826902e6eb8SRob Clark { 827902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 828902e6eb8SRob Clark } 829902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 830902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 831902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 832902e6eb8SRob Clark { 833902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 834902e6eb8SRob Clark } 835902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 836902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 837902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 838902e6eb8SRob Clark { 839902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 840902e6eb8SRob Clark } 841902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 842902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 843902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 844902e6eb8SRob Clark { 845902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 846902e6eb8SRob Clark } 847902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 848902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 849902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 850902e6eb8SRob Clark { 851902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 852902e6eb8SRob Clark } 853902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 854902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 855902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 856902e6eb8SRob Clark { 857902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 858902e6eb8SRob Clark } 859902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 860902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 861902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 862902e6eb8SRob Clark { 863902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 864902e6eb8SRob Clark } 865902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 866902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 867902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 868902e6eb8SRob Clark { 869902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 870902e6eb8SRob Clark } 871902e6eb8SRob Clark 872902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 873902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 874902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 875902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 876902e6eb8SRob Clark { 877902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 878902e6eb8SRob Clark } 879902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 880902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 881902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val) 882902e6eb8SRob Clark { 883902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 884902e6eb8SRob Clark } 885902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 886902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 887902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 888902e6eb8SRob Clark { 889902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 890902e6eb8SRob Clark } 891902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 892902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 893902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 894902e6eb8SRob Clark { 895902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 896902e6eb8SRob Clark } 897902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 898902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 899902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val) 900902e6eb8SRob Clark { 901902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 902902e6eb8SRob Clark } 903902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 904902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 905902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 906902e6eb8SRob Clark { 907902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 908902e6eb8SRob Clark } 909902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 910902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 911902e6eb8SRob Clark 912902e6eb8SRob Clark #define REG_A2XX_RB_COLORCONTROL 0x00002202 913902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 914902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 915902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 916902e6eb8SRob Clark { 917902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 918902e6eb8SRob Clark } 919902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 920902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 921902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 922902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 923902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 924902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 925902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 926902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 927902e6eb8SRob Clark { 928902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 929902e6eb8SRob Clark } 930902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 931902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 932902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 933902e6eb8SRob Clark { 934902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 935902e6eb8SRob Clark } 936902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 937902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 938902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 939902e6eb8SRob Clark { 940902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 941902e6eb8SRob Clark } 942902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 943902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 944902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 945902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 946902e6eb8SRob Clark { 947902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 948902e6eb8SRob Clark } 949902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 950902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 951902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 952902e6eb8SRob Clark { 953902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 954902e6eb8SRob Clark } 955902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 956902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 957902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 958902e6eb8SRob Clark { 959902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 960902e6eb8SRob Clark } 961902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 962902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 963902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 964902e6eb8SRob Clark { 965902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 966902e6eb8SRob Clark } 967902e6eb8SRob Clark 968902e6eb8SRob Clark #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 969902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 970902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 971902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 972902e6eb8SRob Clark { 973902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 974902e6eb8SRob Clark } 975902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 976902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 977902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 978902e6eb8SRob Clark { 979902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 980902e6eb8SRob Clark } 981902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 982902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 983902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 984902e6eb8SRob Clark { 985902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 986902e6eb8SRob Clark } 987902e6eb8SRob Clark 988902e6eb8SRob Clark #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 989902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 990902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 991902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 992902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 993902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 994902e6eb8SRob Clark { 995902e6eb8SRob Clark return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 996902e6eb8SRob Clark } 997902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 998902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 999902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1000902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1001902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1002902e6eb8SRob Clark 1003902e6eb8SRob Clark #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1004902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1005902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1006902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1007902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1008902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1009902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1010902e6eb8SRob Clark { 1011902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1012902e6eb8SRob Clark } 1013902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1014902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1015902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1016902e6eb8SRob Clark { 1017902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1018902e6eb8SRob Clark } 1019902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1020902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1021902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1022902e6eb8SRob Clark { 1023902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1024902e6eb8SRob Clark } 1025902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1026902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1027902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1028902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1029902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1030902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1031902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1032902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1033902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1034902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1035902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1036902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1037902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1038902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1039902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1040902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1041902e6eb8SRob Clark 1042902e6eb8SRob Clark #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1043902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1044902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1045902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1046902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1047902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1048902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1049902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1050902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1051902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1052902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1053902e6eb8SRob Clark 1054902e6eb8SRob Clark #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1055902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1056902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1057902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1058902e6eb8SRob Clark { 1059902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1060902e6eb8SRob Clark } 1061902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1062902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1063902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1064902e6eb8SRob Clark { 1065902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1066902e6eb8SRob Clark } 1067902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1068902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1069902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1070902e6eb8SRob Clark { 1071902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1072902e6eb8SRob Clark } 1073902e6eb8SRob Clark 1074902e6eb8SRob Clark #define REG_A2XX_RB_MODECONTROL 0x00002208 1075902e6eb8SRob Clark #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1076902e6eb8SRob Clark #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1077902e6eb8SRob Clark static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1078902e6eb8SRob Clark { 1079902e6eb8SRob Clark return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1080902e6eb8SRob Clark } 1081902e6eb8SRob Clark 1082902e6eb8SRob Clark #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1083902e6eb8SRob Clark 1084902e6eb8SRob Clark #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1085902e6eb8SRob Clark 1086902e6eb8SRob Clark #define REG_A2XX_CLEAR_COLOR 0x0000220b 1087902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1088902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1089902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1090902e6eb8SRob Clark { 1091902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1092902e6eb8SRob Clark } 1093902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1094902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1095902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1096902e6eb8SRob Clark { 1097902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1098902e6eb8SRob Clark } 1099902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1100902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1101902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1102902e6eb8SRob Clark { 1103902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1104902e6eb8SRob Clark } 1105902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1106902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1107902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1108902e6eb8SRob Clark { 1109902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1110902e6eb8SRob Clark } 1111902e6eb8SRob Clark 1112902e6eb8SRob Clark #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1113902e6eb8SRob Clark 1114902e6eb8SRob Clark #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1115902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1116902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1117902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1118902e6eb8SRob Clark { 1119902e6eb8SRob Clark return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1120902e6eb8SRob Clark } 1121902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1122902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1123902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1124902e6eb8SRob Clark { 1125902e6eb8SRob Clark return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1126902e6eb8SRob Clark } 1127902e6eb8SRob Clark 1128902e6eb8SRob Clark #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1129902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1130902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1131902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1132902e6eb8SRob Clark { 1133902e6eb8SRob Clark return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1134902e6eb8SRob Clark } 1135902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1136902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1137902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1138902e6eb8SRob Clark { 1139902e6eb8SRob Clark return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1140902e6eb8SRob Clark } 1141902e6eb8SRob Clark 1142902e6eb8SRob Clark #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1143902e6eb8SRob Clark #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1144902e6eb8SRob Clark #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1145902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1146902e6eb8SRob Clark { 1147902e6eb8SRob Clark return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1148902e6eb8SRob Clark } 1149902e6eb8SRob Clark 1150902e6eb8SRob Clark #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1151902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1152902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1153902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1154902e6eb8SRob Clark { 1155902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1156902e6eb8SRob Clark } 1157902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1158902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1159902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1160902e6eb8SRob Clark { 1161902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1162902e6eb8SRob Clark } 1163902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1164902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1165902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1166902e6eb8SRob Clark { 1167902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1168902e6eb8SRob Clark } 1169902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1170902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1171902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1172902e6eb8SRob Clark { 1173902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1174902e6eb8SRob Clark } 1175902e6eb8SRob Clark 1176902e6eb8SRob Clark #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1177902e6eb8SRob Clark 1178902e6eb8SRob Clark #define REG_A2XX_VGT_ENHANCE 0x00002294 1179902e6eb8SRob Clark 1180902e6eb8SRob Clark #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1181902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1182902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1183902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1184902e6eb8SRob Clark { 1185902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1186902e6eb8SRob Clark } 1187902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1188902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1189902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1190902e6eb8SRob Clark 1191902e6eb8SRob Clark #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1192902e6eb8SRob Clark 1193902e6eb8SRob Clark #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1194902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1195902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1196902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1197902e6eb8SRob Clark { 1198902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1199902e6eb8SRob Clark } 1200902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1201902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1202902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1203902e6eb8SRob Clark { 1204902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1205902e6eb8SRob Clark } 1206902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1207902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1208902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1209902e6eb8SRob Clark { 1210902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1211902e6eb8SRob Clark } 1212902e6eb8SRob Clark 1213902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1214902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1215902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1216902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1217902e6eb8SRob Clark { 1218902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1219902e6eb8SRob Clark } 1220902e6eb8SRob Clark 1221902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1222902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1223902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1224902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1225902e6eb8SRob Clark { 1226902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1227902e6eb8SRob Clark } 1228902e6eb8SRob Clark 1229902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1230902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1231902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1232902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1233902e6eb8SRob Clark { 1234902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1235902e6eb8SRob Clark } 1236902e6eb8SRob Clark 1237902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1238902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1239902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1240902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1241902e6eb8SRob Clark { 1242902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1243902e6eb8SRob Clark } 1244902e6eb8SRob Clark 1245902e6eb8SRob Clark #define REG_A2XX_SQ_VS_CONST 0x00002307 1246902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1247902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1248902e6eb8SRob Clark static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1249902e6eb8SRob Clark { 1250902e6eb8SRob Clark return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1251902e6eb8SRob Clark } 1252902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1253902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1254902e6eb8SRob Clark static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1255902e6eb8SRob Clark { 1256902e6eb8SRob Clark return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1257902e6eb8SRob Clark } 1258902e6eb8SRob Clark 1259902e6eb8SRob Clark #define REG_A2XX_SQ_PS_CONST 0x00002308 1260902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1261902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1262902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1263902e6eb8SRob Clark { 1264902e6eb8SRob Clark return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1265902e6eb8SRob Clark } 1266902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1267902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1268902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1269902e6eb8SRob Clark { 1270902e6eb8SRob Clark return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1271902e6eb8SRob Clark } 1272902e6eb8SRob Clark 1273902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1274902e6eb8SRob Clark 1275902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1276902e6eb8SRob Clark 1277902e6eb8SRob Clark #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1278902e6eb8SRob Clark 1279902e6eb8SRob Clark #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1280902e6eb8SRob Clark 1281902e6eb8SRob Clark #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1282902e6eb8SRob Clark 1283902e6eb8SRob Clark #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1284902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1285902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1286902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1287902e6eb8SRob Clark { 1288902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1289902e6eb8SRob Clark } 1290902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1291902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1292902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1293902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1294902e6eb8SRob Clark { 1295902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1296902e6eb8SRob Clark } 1297902e6eb8SRob Clark 1298902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1299902e6eb8SRob Clark 1300902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1301902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1302902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1303902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1304902e6eb8SRob Clark { 1305902e6eb8SRob Clark return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1306902e6eb8SRob Clark } 1307902e6eb8SRob Clark 1308902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1309902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1310902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1311902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1312902e6eb8SRob Clark { 1313902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1314902e6eb8SRob Clark } 1315902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1316902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1317902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1318902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1319902e6eb8SRob Clark { 1320902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1321902e6eb8SRob Clark } 1322902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1323902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1324902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1325902e6eb8SRob Clark { 1326902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1327902e6eb8SRob Clark } 1328902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1329902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1330902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1331902e6eb8SRob Clark { 1332902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1333902e6eb8SRob Clark } 1334902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1335902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1336902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1337902e6eb8SRob Clark { 1338902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1339902e6eb8SRob Clark } 1340902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1341902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1342902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1343902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1344902e6eb8SRob Clark 1345902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1346902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1347902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1348902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1349902e6eb8SRob Clark { 1350902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1351902e6eb8SRob Clark } 1352902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1353902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1354902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1355902e6eb8SRob Clark { 1356902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1357902e6eb8SRob Clark } 1358902e6eb8SRob Clark 1359902e6eb8SRob Clark #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1360902e6eb8SRob Clark 1361902e6eb8SRob Clark #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1362902e6eb8SRob Clark 1363902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1364902e6eb8SRob Clark 1365902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1366902e6eb8SRob Clark 1367902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1368902e6eb8SRob Clark 1369902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1370902e6eb8SRob Clark 1371902e6eb8SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1372902e6eb8SRob Clark 1373902e6eb8SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1374902e6eb8SRob Clark 1375902e6eb8SRob Clark #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1376902e6eb8SRob Clark 1377902e6eb8SRob Clark #define REG_A2XX_SQ_FETCH_0 0x00004800 1378902e6eb8SRob Clark 1379902e6eb8SRob Clark #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1380902e6eb8SRob Clark 1381902e6eb8SRob Clark #define REG_A2XX_SQ_CF_LOOP 0x00004908 1382902e6eb8SRob Clark 1383902e6eb8SRob Clark #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1384902e6eb8SRob Clark 1385902e6eb8SRob Clark #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1386902e6eb8SRob Clark 1387902e6eb8SRob Clark #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1388902e6eb8SRob Clark 1389902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_0 0x00000000 1390902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1391902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1392902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1393902e6eb8SRob Clark { 1394902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1395902e6eb8SRob Clark } 1396902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1397902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1398902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1399902e6eb8SRob Clark { 1400902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1401902e6eb8SRob Clark } 1402902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1403902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1404902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1405902e6eb8SRob Clark { 1406902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1407902e6eb8SRob Clark } 1408902e6eb8SRob Clark #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1409902e6eb8SRob Clark #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1410902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1411902e6eb8SRob Clark { 1412902e6eb8SRob Clark return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1413902e6eb8SRob Clark } 1414902e6eb8SRob Clark 1415902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_1 0x00000001 1416902e6eb8SRob Clark 1417902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_2 0x00000002 1418902e6eb8SRob Clark #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1419902e6eb8SRob Clark #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1420902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1421902e6eb8SRob Clark { 1422902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1423902e6eb8SRob Clark } 1424902e6eb8SRob Clark #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1425902e6eb8SRob Clark #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1426902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1427902e6eb8SRob Clark { 1428902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1429902e6eb8SRob Clark } 1430902e6eb8SRob Clark 1431902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_3 0x00000003 1432902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1433902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1434902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1435902e6eb8SRob Clark { 1436902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1437902e6eb8SRob Clark } 1438902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1439902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1440902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1441902e6eb8SRob Clark { 1442902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1443902e6eb8SRob Clark } 1444902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1445902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1446902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1447902e6eb8SRob Clark { 1448902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1449902e6eb8SRob Clark } 1450902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1451902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1452902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1453902e6eb8SRob Clark { 1454902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1455902e6eb8SRob Clark } 1456902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1457902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1458902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1459902e6eb8SRob Clark { 1460902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1461902e6eb8SRob Clark } 1462902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1463902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1464902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1465902e6eb8SRob Clark { 1466902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1467902e6eb8SRob Clark } 1468902e6eb8SRob Clark 1469902e6eb8SRob Clark 1470902e6eb8SRob Clark #endif /* A2XX_XML */ 1471