1# SPDX-License-Identifier: GPL-2.0 2ccflags-y := -I $(srctree)/$(src) 3ccflags-y += -I $(srctree)/$(src)/disp/dpu1 4ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi 5ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp 6 7msm-y := \ 8 adreno/adreno_device.o \ 9 adreno/adreno_gpu.o \ 10 adreno/a2xx_gpu.o \ 11 adreno/a3xx_gpu.o \ 12 adreno/a4xx_gpu.o \ 13 adreno/a5xx_gpu.o \ 14 adreno/a5xx_power.o \ 15 adreno/a5xx_preempt.o \ 16 adreno/a6xx_gpu.o \ 17 adreno/a6xx_gmu.o \ 18 adreno/a6xx_hfi.o \ 19 20msm-$(CONFIG_DRM_MSM_HDMI) += \ 21 hdmi/hdmi.o \ 22 hdmi/hdmi_audio.o \ 23 hdmi/hdmi_bridge.o \ 24 hdmi/hdmi_hpd.o \ 25 hdmi/hdmi_i2c.o \ 26 hdmi/hdmi_phy.o \ 27 hdmi/hdmi_phy_8960.o \ 28 hdmi/hdmi_phy_8996.o \ 29 hdmi/hdmi_phy_8x60.o \ 30 hdmi/hdmi_phy_8x74.o \ 31 hdmi/hdmi_pll_8960.o \ 32 33msm-$(CONFIG_DRM_MSM_MDP4) += \ 34 disp/mdp4/mdp4_crtc.o \ 35 disp/mdp4/mdp4_dsi_encoder.o \ 36 disp/mdp4/mdp4_dtv_encoder.o \ 37 disp/mdp4/mdp4_lcdc_encoder.o \ 38 disp/mdp4/mdp4_lvds_connector.o \ 39 disp/mdp4/mdp4_lvds_pll.o \ 40 disp/mdp4/mdp4_irq.o \ 41 disp/mdp4/mdp4_kms.o \ 42 disp/mdp4/mdp4_plane.o \ 43 44msm-$(CONFIG_DRM_MSM_MDP5) += \ 45 disp/mdp5/mdp5_cfg.o \ 46 disp/mdp5/mdp5_cmd_encoder.o \ 47 disp/mdp5/mdp5_ctl.o \ 48 disp/mdp5/mdp5_crtc.o \ 49 disp/mdp5/mdp5_encoder.o \ 50 disp/mdp5/mdp5_irq.o \ 51 disp/mdp5/mdp5_kms.o \ 52 disp/mdp5/mdp5_pipe.o \ 53 disp/mdp5/mdp5_mixer.o \ 54 disp/mdp5/mdp5_plane.o \ 55 disp/mdp5/mdp5_smp.o \ 56 57msm-$(CONFIG_DRM_MSM_DPU) += \ 58 disp/dpu1/dpu_core_perf.o \ 59 disp/dpu1/dpu_crtc.o \ 60 disp/dpu1/dpu_encoder.o \ 61 disp/dpu1/dpu_encoder_phys_cmd.o \ 62 disp/dpu1/dpu_encoder_phys_vid.o \ 63 disp/dpu1/dpu_encoder_phys_wb.o \ 64 disp/dpu1/dpu_formats.o \ 65 disp/dpu1/dpu_hw_catalog.o \ 66 disp/dpu1/dpu_hw_ctl.o \ 67 disp/dpu1/dpu_hw_dsc.o \ 68 disp/dpu1/dpu_hw_interrupts.o \ 69 disp/dpu1/dpu_hw_intf.o \ 70 disp/dpu1/dpu_hw_lm.o \ 71 disp/dpu1/dpu_hw_pingpong.o \ 72 disp/dpu1/dpu_hw_sspp.o \ 73 disp/dpu1/dpu_hw_dspp.o \ 74 disp/dpu1/dpu_hw_merge3d.o \ 75 disp/dpu1/dpu_hw_top.o \ 76 disp/dpu1/dpu_hw_util.o \ 77 disp/dpu1/dpu_hw_vbif.o \ 78 disp/dpu1/dpu_hw_wb.o \ 79 disp/dpu1/dpu_kms.o \ 80 disp/dpu1/dpu_plane.o \ 81 disp/dpu1/dpu_rm.o \ 82 disp/dpu1/dpu_vbif.o \ 83 disp/dpu1/dpu_writeback.o 84 85msm-$(CONFIG_DRM_MSM_MDSS) += \ 86 msm_mdss.o \ 87 88msm-y += \ 89 disp/mdp_format.o \ 90 disp/mdp_kms.o \ 91 disp/msm_disp_snapshot.o \ 92 disp/msm_disp_snapshot_util.o \ 93 msm_atomic.o \ 94 msm_atomic_tracepoints.o \ 95 msm_debugfs.o \ 96 msm_drv.o \ 97 msm_fb.o \ 98 msm_fence.o \ 99 msm_gem.o \ 100 msm_gem_prime.o \ 101 msm_gem_shrinker.o \ 102 msm_gem_submit.o \ 103 msm_gem_vma.o \ 104 msm_gpu.o \ 105 msm_gpu_devfreq.o \ 106 msm_io_utils.o \ 107 msm_iommu.o \ 108 msm_perf.o \ 109 msm_rd.o \ 110 msm_ringbuffer.o \ 111 msm_submitqueue.o \ 112 msm_gpu_tracepoints.o \ 113 msm_gpummu.o 114 115msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \ 116 dp/dp_debug.o 117 118msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o 119 120msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ 121 dp/dp_catalog.o \ 122 dp/dp_ctrl.o \ 123 dp/dp_display.o \ 124 dp/dp_drm.o \ 125 dp/dp_hpd.o \ 126 dp/dp_link.o \ 127 dp/dp_panel.o \ 128 dp/dp_parser.o \ 129 dp/dp_power.o \ 130 dp/dp_audio.o 131 132msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o 133 134msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o 135 136msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ 137 dsi/dsi_cfg.o \ 138 dsi/dsi_host.o \ 139 dsi/dsi_manager.o \ 140 dsi/phy/dsi_phy.o 141 142msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o 143msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o 144msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o 145msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o 146msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o 147msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o 148 149obj-$(CONFIG_DRM_MSM) += msm.o 150