1# SPDX-License-Identifier: GPL-2.0 2ccflags-y := -Idrivers/gpu/drm/msm 3ccflags-y += -Idrivers/gpu/drm/msm/disp/dpu1 4ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi 5 6msm-y := \ 7 adreno/adreno_device.o \ 8 adreno/adreno_gpu.o \ 9 adreno/a3xx_gpu.o \ 10 adreno/a4xx_gpu.o \ 11 adreno/a5xx_gpu.o \ 12 adreno/a5xx_power.o \ 13 adreno/a5xx_preempt.o \ 14 adreno/a6xx_gpu.o \ 15 adreno/a6xx_gmu.o \ 16 adreno/a6xx_hfi.o \ 17 hdmi/hdmi.o \ 18 hdmi/hdmi_audio.o \ 19 hdmi/hdmi_bridge.o \ 20 hdmi/hdmi_connector.o \ 21 hdmi/hdmi_i2c.o \ 22 hdmi/hdmi_phy.o \ 23 hdmi/hdmi_phy_8960.o \ 24 hdmi/hdmi_phy_8x60.o \ 25 hdmi/hdmi_phy_8x74.o \ 26 edp/edp.o \ 27 edp/edp_aux.o \ 28 edp/edp_bridge.o \ 29 edp/edp_connector.o \ 30 edp/edp_ctrl.o \ 31 edp/edp_phy.o \ 32 disp/mdp_format.o \ 33 disp/mdp_kms.o \ 34 disp/mdp4/mdp4_crtc.o \ 35 disp/mdp4/mdp4_dtv_encoder.o \ 36 disp/mdp4/mdp4_lcdc_encoder.o \ 37 disp/mdp4/mdp4_lvds_connector.o \ 38 disp/mdp4/mdp4_irq.o \ 39 disp/mdp4/mdp4_kms.o \ 40 disp/mdp4/mdp4_plane.o \ 41 disp/mdp5/mdp5_cfg.o \ 42 disp/mdp5/mdp5_ctl.o \ 43 disp/mdp5/mdp5_crtc.o \ 44 disp/mdp5/mdp5_encoder.o \ 45 disp/mdp5/mdp5_irq.o \ 46 disp/mdp5/mdp5_mdss.o \ 47 disp/mdp5/mdp5_kms.o \ 48 disp/mdp5/mdp5_pipe.o \ 49 disp/mdp5/mdp5_mixer.o \ 50 disp/mdp5/mdp5_plane.o \ 51 disp/mdp5/mdp5_smp.o \ 52 disp/dpu1/dpu_core_irq.o \ 53 disp/dpu1/dpu_core_perf.o \ 54 disp/dpu1/dpu_crtc.o \ 55 disp/dpu1/dpu_encoder.o \ 56 disp/dpu1/dpu_encoder_phys_cmd.o \ 57 disp/dpu1/dpu_encoder_phys_vid.o \ 58 disp/dpu1/dpu_formats.o \ 59 disp/dpu1/dpu_hw_blk.o \ 60 disp/dpu1/dpu_hw_catalog.o \ 61 disp/dpu1/dpu_hw_cdm.o \ 62 disp/dpu1/dpu_hw_ctl.o \ 63 disp/dpu1/dpu_hw_interrupts.o \ 64 disp/dpu1/dpu_hw_intf.o \ 65 disp/dpu1/dpu_hw_lm.o \ 66 disp/dpu1/dpu_hw_pingpong.o \ 67 disp/dpu1/dpu_hw_sspp.o \ 68 disp/dpu1/dpu_hw_top.o \ 69 disp/dpu1/dpu_hw_util.o \ 70 disp/dpu1/dpu_hw_vbif.o \ 71 disp/dpu1/dpu_io_util.o \ 72 disp/dpu1/dpu_irq.o \ 73 disp/dpu1/dpu_kms.o \ 74 disp/dpu1/dpu_mdss.o \ 75 disp/dpu1/dpu_plane.o \ 76 disp/dpu1/dpu_power_handle.o \ 77 disp/dpu1/dpu_rm.o \ 78 disp/dpu1/dpu_vbif.o \ 79 msm_atomic.o \ 80 msm_debugfs.o \ 81 msm_drv.o \ 82 msm_fb.o \ 83 msm_fence.o \ 84 msm_gem.o \ 85 msm_gem_prime.o \ 86 msm_gem_shrinker.o \ 87 msm_gem_submit.o \ 88 msm_gem_vma.o \ 89 msm_gpu.o \ 90 msm_iommu.o \ 91 msm_perf.o \ 92 msm_rd.o \ 93 msm_ringbuffer.o \ 94 msm_submitqueue.o 95 96msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \ 97 disp/dpu1/dpu_dbg.o 98 99msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o 100msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o 101msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o 102msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_phy_8996.o 103 104msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o 105 106msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ 107 disp/mdp4/mdp4_dsi_encoder.o \ 108 dsi/dsi_cfg.o \ 109 dsi/dsi_host.o \ 110 dsi/dsi_manager.o \ 111 dsi/phy/dsi_phy.o \ 112 disp/mdp5/mdp5_cmd_encoder.o 113 114msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o 115msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o 116msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o 117msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o 118msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o 119 120ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y) 121msm-y += dsi/pll/dsi_pll.o 122msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o 123msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o 124msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o 125msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o 126endif 127 128obj-$(CONFIG_DRM_MSM) += msm.o 129