1 /* 2 * Copyright 2010 Matt Turner. 3 * Copyright 2012 Red Hat 4 * 5 * This file is subject to the terms and conditions of the GNU General 6 * Public License version 2. See the file COPYING in the main 7 * directory of this archive for more details. 8 * 9 * Authors: Matthew Garrett 10 * Matt Turner 11 * Dave Airlie 12 */ 13 14 #include <linux/delay.h> 15 16 #include <drm/drmP.h> 17 #include <drm/drm_crtc_helper.h> 18 #include <drm/drm_plane_helper.h> 19 20 #include "mgag200_drv.h" 21 22 #define MGAG200_LUT_SIZE 256 23 24 /* 25 * This file contains setup code for the CRTC. 26 */ 27 28 static void mga_crtc_load_lut(struct drm_crtc *crtc) 29 { 30 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 31 struct drm_device *dev = crtc->dev; 32 struct mga_device *mdev = dev->dev_private; 33 struct drm_framebuffer *fb = crtc->primary->fb; 34 int i; 35 36 if (!crtc->enabled) 37 return; 38 39 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 40 41 if (fb && fb->bits_per_pixel == 16) { 42 int inc = (fb->depth == 15) ? 8 : 4; 43 u8 r, b; 44 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) { 45 if (fb->depth == 16) { 46 if (i > (MGAG200_LUT_SIZE >> 1)) { 47 r = b = 0; 48 } else { 49 r = mga_crtc->lut_r[i << 1]; 50 b = mga_crtc->lut_b[i << 1]; 51 } 52 } else { 53 r = mga_crtc->lut_r[i]; 54 b = mga_crtc->lut_b[i]; 55 } 56 /* VGA registers */ 57 WREG8(DAC_INDEX + MGA1064_COL_PAL, r); 58 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]); 59 WREG8(DAC_INDEX + MGA1064_COL_PAL, b); 60 } 61 return; 62 } 63 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 64 /* VGA registers */ 65 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]); 66 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]); 67 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]); 68 } 69 } 70 71 static inline void mga_wait_vsync(struct mga_device *mdev) 72 { 73 unsigned long timeout = jiffies + HZ/10; 74 unsigned int status = 0; 75 76 do { 77 status = RREG32(MGAREG_Status); 78 } while ((status & 0x08) && time_before(jiffies, timeout)); 79 timeout = jiffies + HZ/10; 80 status = 0; 81 do { 82 status = RREG32(MGAREG_Status); 83 } while (!(status & 0x08) && time_before(jiffies, timeout)); 84 } 85 86 static inline void mga_wait_busy(struct mga_device *mdev) 87 { 88 unsigned long timeout = jiffies + HZ; 89 unsigned int status = 0; 90 do { 91 status = RREG8(MGAREG_Status + 2); 92 } while ((status & 0x01) && time_before(jiffies, timeout)); 93 } 94 95 /* 96 * The core passes the desired mode to the CRTC code to see whether any 97 * CRTC-specific modifications need to be made to it. We're in a position 98 * to just pass that straight through, so this does nothing 99 */ 100 static bool mga_crtc_mode_fixup(struct drm_crtc *crtc, 101 const struct drm_display_mode *mode, 102 struct drm_display_mode *adjusted_mode) 103 { 104 return true; 105 } 106 107 #define P_ARRAY_SIZE 9 108 109 static int mga_g200se_set_plls(struct mga_device *mdev, long clock) 110 { 111 unsigned int vcomax, vcomin, pllreffreq; 112 unsigned int delta, tmpdelta, permitteddelta; 113 unsigned int testp, testm, testn; 114 unsigned int p, m, n; 115 unsigned int computed; 116 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1}; 117 unsigned int fvv; 118 unsigned int i; 119 120 if (mdev->unique_rev_id <= 0x03) { 121 122 m = n = p = 0; 123 vcomax = 320000; 124 vcomin = 160000; 125 pllreffreq = 25000; 126 127 delta = 0xffffffff; 128 permitteddelta = clock * 5 / 1000; 129 130 for (testp = 8; testp > 0; testp /= 2) { 131 if (clock * testp > vcomax) 132 continue; 133 if (clock * testp < vcomin) 134 continue; 135 136 for (testn = 17; testn < 256; testn++) { 137 for (testm = 1; testm < 32; testm++) { 138 computed = (pllreffreq * testn) / 139 (testm * testp); 140 if (computed > clock) 141 tmpdelta = computed - clock; 142 else 143 tmpdelta = clock - computed; 144 if (tmpdelta < delta) { 145 delta = tmpdelta; 146 m = testm - 1; 147 n = testn - 1; 148 p = testp - 1; 149 } 150 } 151 } 152 } 153 } else { 154 155 156 m = n = p = 0; 157 vcomax = 1600000; 158 vcomin = 800000; 159 pllreffreq = 25000; 160 161 if (clock < 25000) 162 clock = 25000; 163 164 clock = clock * 2; 165 166 delta = 0xFFFFFFFF; 167 /* Permited delta is 0.5% as VESA Specification */ 168 permitteddelta = clock * 5 / 1000; 169 170 for (i = 0 ; i < P_ARRAY_SIZE ; i++) { 171 testp = pvalues_e4[i]; 172 173 if ((clock * testp) > vcomax) 174 continue; 175 if ((clock * testp) < vcomin) 176 continue; 177 178 for (testn = 50; testn <= 256; testn++) { 179 for (testm = 1; testm <= 32; testm++) { 180 computed = (pllreffreq * testn) / 181 (testm * testp); 182 if (computed > clock) 183 tmpdelta = computed - clock; 184 else 185 tmpdelta = clock - computed; 186 187 if (tmpdelta < delta) { 188 delta = tmpdelta; 189 m = testm - 1; 190 n = testn - 1; 191 p = testp - 1; 192 } 193 } 194 } 195 } 196 197 fvv = pllreffreq * testn / testm; 198 fvv = (fvv - 800000) / 50000; 199 200 if (fvv > 15) 201 fvv = 15; 202 203 p |= (fvv << 4); 204 m |= 0x80; 205 206 clock = clock / 2; 207 } 208 209 if (delta > permitteddelta) { 210 printk(KERN_WARNING "PLL delta too large\n"); 211 return 1; 212 } 213 214 WREG_DAC(MGA1064_PIX_PLLC_M, m); 215 WREG_DAC(MGA1064_PIX_PLLC_N, n); 216 WREG_DAC(MGA1064_PIX_PLLC_P, p); 217 return 0; 218 } 219 220 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock) 221 { 222 unsigned int vcomax, vcomin, pllreffreq; 223 unsigned int delta, tmpdelta; 224 unsigned int testp, testm, testn, testp2; 225 unsigned int p, m, n; 226 unsigned int computed; 227 int i, j, tmpcount, vcount; 228 bool pll_locked = false; 229 u8 tmp; 230 231 m = n = p = 0; 232 233 delta = 0xffffffff; 234 235 if (mdev->type == G200_EW3) { 236 237 vcomax = 800000; 238 vcomin = 400000; 239 pllreffreq = 25000; 240 241 for (testp = 1; testp < 8; testp++) { 242 for (testp2 = 1; testp2 < 8; testp2++) { 243 if (testp < testp2) 244 continue; 245 if ((clock * testp * testp2) > vcomax) 246 continue; 247 if ((clock * testp * testp2) < vcomin) 248 continue; 249 for (testm = 1; testm < 26; testm++) { 250 for (testn = 32; testn < 2048 ; testn++) { 251 computed = (pllreffreq * testn) / 252 (testm * testp * testp2); 253 if (computed > clock) 254 tmpdelta = computed - clock; 255 else 256 tmpdelta = clock - computed; 257 if (tmpdelta < delta) { 258 delta = tmpdelta; 259 m = ((testn & 0x100) >> 1) | 260 (testm); 261 n = (testn & 0xFF); 262 p = ((testn & 0x600) >> 3) | 263 (testp2 << 3) | 264 (testp); 265 } 266 } 267 } 268 } 269 } 270 } else { 271 272 vcomax = 550000; 273 vcomin = 150000; 274 pllreffreq = 48000; 275 276 for (testp = 1; testp < 9; testp++) { 277 if (clock * testp > vcomax) 278 continue; 279 if (clock * testp < vcomin) 280 continue; 281 282 for (testm = 1; testm < 17; testm++) { 283 for (testn = 1; testn < 151; testn++) { 284 computed = (pllreffreq * testn) / 285 (testm * testp); 286 if (computed > clock) 287 tmpdelta = computed - clock; 288 else 289 tmpdelta = clock - computed; 290 if (tmpdelta < delta) { 291 delta = tmpdelta; 292 n = testn - 1; 293 m = (testm - 1) | 294 ((n >> 1) & 0x80); 295 p = testp - 1; 296 } 297 } 298 } 299 } 300 } 301 302 for (i = 0; i <= 32 && pll_locked == false; i++) { 303 if (i > 0) { 304 WREG8(MGAREG_CRTC_INDEX, 0x1e); 305 tmp = RREG8(MGAREG_CRTC_DATA); 306 if (tmp < 0xff) 307 WREG8(MGAREG_CRTC_DATA, tmp+1); 308 } 309 310 /* set pixclkdis to 1 */ 311 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 312 tmp = RREG8(DAC_DATA); 313 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 314 WREG8(DAC_DATA, tmp); 315 316 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 317 tmp = RREG8(DAC_DATA); 318 tmp |= MGA1064_REMHEADCTL_CLKDIS; 319 WREG8(DAC_DATA, tmp); 320 321 /* select PLL Set C */ 322 tmp = RREG8(MGAREG_MEM_MISC_READ); 323 tmp |= 0x3 << 2; 324 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 325 326 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 327 tmp = RREG8(DAC_DATA); 328 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80; 329 WREG8(DAC_DATA, tmp); 330 331 udelay(500); 332 333 /* reset the PLL */ 334 WREG8(DAC_INDEX, MGA1064_VREF_CTL); 335 tmp = RREG8(DAC_DATA); 336 tmp &= ~0x04; 337 WREG8(DAC_DATA, tmp); 338 339 udelay(50); 340 341 /* program pixel pll register */ 342 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n); 343 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m); 344 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p); 345 346 udelay(50); 347 348 /* turn pll on */ 349 WREG8(DAC_INDEX, MGA1064_VREF_CTL); 350 tmp = RREG8(DAC_DATA); 351 tmp |= 0x04; 352 WREG_DAC(MGA1064_VREF_CTL, tmp); 353 354 udelay(500); 355 356 /* select the pixel pll */ 357 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 358 tmp = RREG8(DAC_DATA); 359 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 360 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 361 WREG8(DAC_DATA, tmp); 362 363 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 364 tmp = RREG8(DAC_DATA); 365 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK; 366 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL; 367 WREG8(DAC_DATA, tmp); 368 369 /* reset dotclock rate bit */ 370 WREG8(MGAREG_SEQ_INDEX, 1); 371 tmp = RREG8(MGAREG_SEQ_DATA); 372 tmp &= ~0x8; 373 WREG8(MGAREG_SEQ_DATA, tmp); 374 375 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 376 tmp = RREG8(DAC_DATA); 377 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 378 WREG8(DAC_DATA, tmp); 379 380 vcount = RREG8(MGAREG_VCOUNT); 381 382 for (j = 0; j < 30 && pll_locked == false; j++) { 383 tmpcount = RREG8(MGAREG_VCOUNT); 384 if (tmpcount < vcount) 385 vcount = 0; 386 if ((tmpcount - vcount) > 2) 387 pll_locked = true; 388 else 389 udelay(5); 390 } 391 } 392 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 393 tmp = RREG8(DAC_DATA); 394 tmp &= ~MGA1064_REMHEADCTL_CLKDIS; 395 WREG_DAC(MGA1064_REMHEADCTL, tmp); 396 return 0; 397 } 398 399 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock) 400 { 401 unsigned int vcomax, vcomin, pllreffreq; 402 unsigned int delta, tmpdelta; 403 unsigned int testp, testm, testn; 404 unsigned int p, m, n; 405 unsigned int computed; 406 u8 tmp; 407 408 m = n = p = 0; 409 vcomax = 550000; 410 vcomin = 150000; 411 pllreffreq = 50000; 412 413 delta = 0xffffffff; 414 415 for (testp = 16; testp > 0; testp--) { 416 if (clock * testp > vcomax) 417 continue; 418 if (clock * testp < vcomin) 419 continue; 420 421 for (testn = 1; testn < 257; testn++) { 422 for (testm = 1; testm < 17; testm++) { 423 computed = (pllreffreq * testn) / 424 (testm * testp); 425 if (computed > clock) 426 tmpdelta = computed - clock; 427 else 428 tmpdelta = clock - computed; 429 if (tmpdelta < delta) { 430 delta = tmpdelta; 431 n = testn - 1; 432 m = testm - 1; 433 p = testp - 1; 434 } 435 } 436 } 437 } 438 439 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 440 tmp = RREG8(DAC_DATA); 441 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 442 WREG8(DAC_DATA, tmp); 443 444 tmp = RREG8(MGAREG_MEM_MISC_READ); 445 tmp |= 0x3 << 2; 446 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 447 448 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 449 tmp = RREG8(DAC_DATA); 450 WREG8(DAC_DATA, tmp & ~0x40); 451 452 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 453 tmp = RREG8(DAC_DATA); 454 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 455 WREG8(DAC_DATA, tmp); 456 457 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m); 458 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n); 459 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p); 460 461 udelay(50); 462 463 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 464 tmp = RREG8(DAC_DATA); 465 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 466 WREG8(DAC_DATA, tmp); 467 468 udelay(500); 469 470 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 471 tmp = RREG8(DAC_DATA); 472 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 473 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 474 WREG8(DAC_DATA, tmp); 475 476 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 477 tmp = RREG8(DAC_DATA); 478 WREG8(DAC_DATA, tmp | 0x40); 479 480 tmp = RREG8(MGAREG_MEM_MISC_READ); 481 tmp |= (0x3 << 2); 482 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 483 484 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 485 tmp = RREG8(DAC_DATA); 486 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 487 WREG8(DAC_DATA, tmp); 488 489 return 0; 490 } 491 492 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock) 493 { 494 unsigned int vcomax, vcomin, pllreffreq; 495 unsigned int delta, tmpdelta; 496 unsigned int testp, testm, testn; 497 unsigned int p, m, n; 498 unsigned int computed; 499 int i, j, tmpcount, vcount; 500 u8 tmp; 501 bool pll_locked = false; 502 503 m = n = p = 0; 504 vcomax = 800000; 505 vcomin = 400000; 506 pllreffreq = 33333; 507 508 delta = 0xffffffff; 509 510 for (testp = 16; testp > 0; testp >>= 1) { 511 if (clock * testp > vcomax) 512 continue; 513 if (clock * testp < vcomin) 514 continue; 515 516 for (testm = 1; testm < 33; testm++) { 517 for (testn = 17; testn < 257; testn++) { 518 computed = (pllreffreq * testn) / 519 (testm * testp); 520 if (computed > clock) 521 tmpdelta = computed - clock; 522 else 523 tmpdelta = clock - computed; 524 if (tmpdelta < delta) { 525 delta = tmpdelta; 526 n = testn - 1; 527 m = (testm - 1); 528 p = testp - 1; 529 } 530 if ((clock * testp) >= 600000) 531 p |= 0x80; 532 } 533 } 534 } 535 for (i = 0; i <= 32 && pll_locked == false; i++) { 536 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 537 tmp = RREG8(DAC_DATA); 538 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 539 WREG8(DAC_DATA, tmp); 540 541 tmp = RREG8(MGAREG_MEM_MISC_READ); 542 tmp |= 0x3 << 2; 543 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 544 545 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 546 tmp = RREG8(DAC_DATA); 547 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 548 WREG8(DAC_DATA, tmp); 549 550 udelay(500); 551 552 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m); 553 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n); 554 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p); 555 556 udelay(500); 557 558 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 559 tmp = RREG8(DAC_DATA); 560 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 561 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 562 WREG8(DAC_DATA, tmp); 563 564 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 565 tmp = RREG8(DAC_DATA); 566 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 567 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 568 WREG8(DAC_DATA, tmp); 569 570 vcount = RREG8(MGAREG_VCOUNT); 571 572 for (j = 0; j < 30 && pll_locked == false; j++) { 573 tmpcount = RREG8(MGAREG_VCOUNT); 574 if (tmpcount < vcount) 575 vcount = 0; 576 if ((tmpcount - vcount) > 2) 577 pll_locked = true; 578 else 579 udelay(5); 580 } 581 } 582 583 return 0; 584 } 585 586 static int mga_g200er_set_plls(struct mga_device *mdev, long clock) 587 { 588 unsigned int vcomax, vcomin, pllreffreq; 589 unsigned int delta, tmpdelta; 590 int testr, testn, testm, testo; 591 unsigned int p, m, n; 592 unsigned int computed, vco; 593 int tmp; 594 const unsigned int m_div_val[] = { 1, 2, 4, 8 }; 595 596 m = n = p = 0; 597 vcomax = 1488000; 598 vcomin = 1056000; 599 pllreffreq = 48000; 600 601 delta = 0xffffffff; 602 603 for (testr = 0; testr < 4; testr++) { 604 if (delta == 0) 605 break; 606 for (testn = 5; testn < 129; testn++) { 607 if (delta == 0) 608 break; 609 for (testm = 3; testm >= 0; testm--) { 610 if (delta == 0) 611 break; 612 for (testo = 5; testo < 33; testo++) { 613 vco = pllreffreq * (testn + 1) / 614 (testr + 1); 615 if (vco < vcomin) 616 continue; 617 if (vco > vcomax) 618 continue; 619 computed = vco / (m_div_val[testm] * (testo + 1)); 620 if (computed > clock) 621 tmpdelta = computed - clock; 622 else 623 tmpdelta = clock - computed; 624 if (tmpdelta < delta) { 625 delta = tmpdelta; 626 m = testm | (testo << 3); 627 n = testn; 628 p = testr | (testr << 3); 629 } 630 } 631 } 632 } 633 } 634 635 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 636 tmp = RREG8(DAC_DATA); 637 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 638 WREG8(DAC_DATA, tmp); 639 640 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 641 tmp = RREG8(DAC_DATA); 642 tmp |= MGA1064_REMHEADCTL_CLKDIS; 643 WREG8(DAC_DATA, tmp); 644 645 tmp = RREG8(MGAREG_MEM_MISC_READ); 646 tmp |= (0x3<<2) | 0xc0; 647 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 648 649 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 650 tmp = RREG8(DAC_DATA); 651 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 652 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 653 WREG8(DAC_DATA, tmp); 654 655 udelay(500); 656 657 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n); 658 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m); 659 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p); 660 661 udelay(50); 662 663 return 0; 664 } 665 666 static int mga_crtc_set_plls(struct mga_device *mdev, long clock) 667 { 668 switch(mdev->type) { 669 case G200_SE_A: 670 case G200_SE_B: 671 return mga_g200se_set_plls(mdev, clock); 672 break; 673 case G200_WB: 674 case G200_EW3: 675 return mga_g200wb_set_plls(mdev, clock); 676 break; 677 case G200_EV: 678 return mga_g200ev_set_plls(mdev, clock); 679 break; 680 case G200_EH: 681 return mga_g200eh_set_plls(mdev, clock); 682 break; 683 case G200_ER: 684 return mga_g200er_set_plls(mdev, clock); 685 break; 686 } 687 return 0; 688 } 689 690 static void mga_g200wb_prepare(struct drm_crtc *crtc) 691 { 692 struct mga_device *mdev = crtc->dev->dev_private; 693 u8 tmp; 694 int iter_max; 695 696 /* 1- The first step is to warn the BMC of an upcoming mode change. 697 * We are putting the misc<0> to output.*/ 698 699 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); 700 tmp = RREG8(DAC_DATA); 701 tmp |= 0x10; 702 WREG_DAC(MGA1064_GEN_IO_CTL, tmp); 703 704 /* we are putting a 1 on the misc<0> line */ 705 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 706 tmp = RREG8(DAC_DATA); 707 tmp |= 0x10; 708 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 709 710 /* 2- Second step to mask and further scan request 711 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) 712 */ 713 WREG8(DAC_INDEX, MGA1064_SPAREREG); 714 tmp = RREG8(DAC_DATA); 715 tmp |= 0x80; 716 WREG_DAC(MGA1064_SPAREREG, tmp); 717 718 /* 3a- the third step is to verifu if there is an active scan 719 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) 720 */ 721 iter_max = 300; 722 while (!(tmp & 0x1) && iter_max) { 723 WREG8(DAC_INDEX, MGA1064_SPAREREG); 724 tmp = RREG8(DAC_DATA); 725 udelay(1000); 726 iter_max--; 727 } 728 729 /* 3b- this step occurs only if the remove is actually scanning 730 * we are waiting for the end of the frame which is a 1 on 731 * remvsyncsts (XSPAREREG<1>) 732 */ 733 if (iter_max) { 734 iter_max = 300; 735 while ((tmp & 0x2) && iter_max) { 736 WREG8(DAC_INDEX, MGA1064_SPAREREG); 737 tmp = RREG8(DAC_DATA); 738 udelay(1000); 739 iter_max--; 740 } 741 } 742 } 743 744 static void mga_g200wb_commit(struct drm_crtc *crtc) 745 { 746 u8 tmp; 747 struct mga_device *mdev = crtc->dev->dev_private; 748 749 /* 1- The first step is to ensure that the vrsten and hrsten are set */ 750 WREG8(MGAREG_CRTCEXT_INDEX, 1); 751 tmp = RREG8(MGAREG_CRTCEXT_DATA); 752 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); 753 754 /* 2- second step is to assert the rstlvl2 */ 755 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 756 tmp = RREG8(DAC_DATA); 757 tmp |= 0x8; 758 WREG8(DAC_DATA, tmp); 759 760 /* wait 10 us */ 761 udelay(10); 762 763 /* 3- deassert rstlvl2 */ 764 tmp &= ~0x08; 765 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 766 WREG8(DAC_DATA, tmp); 767 768 /* 4- remove mask of scan request */ 769 WREG8(DAC_INDEX, MGA1064_SPAREREG); 770 tmp = RREG8(DAC_DATA); 771 tmp &= ~0x80; 772 WREG8(DAC_DATA, tmp); 773 774 /* 5- put back a 0 on the misc<0> line */ 775 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 776 tmp = RREG8(DAC_DATA); 777 tmp &= ~0x10; 778 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 779 } 780 781 /* 782 This is how the framebuffer base address is stored in g200 cards: 783 * Assume @offset is the gpu_addr variable of the framebuffer object 784 * Then addr is the number of _pixels_ (not bytes) from the start of 785 VRAM to the first pixel we want to display. (divided by 2 for 32bit 786 framebuffers) 787 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 788 addr<20> -> CRTCEXT0<6> 789 addr<19-16> -> CRTCEXT0<3-0> 790 addr<15-8> -> CRTCC<7-0> 791 addr<7-0> -> CRTCD<7-0> 792 CRTCEXT0 has to be programmed last to trigger an update and make the 793 new addr variable take effect. 794 */ 795 static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset) 796 { 797 struct mga_device *mdev = crtc->dev->dev_private; 798 u32 addr; 799 int count; 800 u8 crtcext0; 801 802 while (RREG8(0x1fda) & 0x08); 803 while (!(RREG8(0x1fda) & 0x08)); 804 805 count = RREG8(MGAREG_VCOUNT) + 2; 806 while (RREG8(MGAREG_VCOUNT) < count); 807 808 WREG8(MGAREG_CRTCEXT_INDEX, 0); 809 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA); 810 crtcext0 &= 0xB0; 811 addr = offset / 8; 812 /* Can't store addresses any higher than that... 813 but we also don't have more than 16MB of memory, so it should be fine. */ 814 WARN_ON(addr > 0x1fffff); 815 crtcext0 |= (!!(addr & (1<<20)))<<6; 816 WREG_CRT(0x0d, (u8)(addr & 0xff)); 817 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff); 818 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0); 819 } 820 821 822 /* ast is different - we will force move buffers out of VRAM */ 823 static int mga_crtc_do_set_base(struct drm_crtc *crtc, 824 struct drm_framebuffer *fb, 825 int x, int y, int atomic) 826 { 827 struct mga_device *mdev = crtc->dev->dev_private; 828 struct drm_gem_object *obj; 829 struct mga_framebuffer *mga_fb; 830 struct mgag200_bo *bo; 831 int ret; 832 u64 gpu_addr; 833 834 /* push the previous fb to system ram */ 835 if (!atomic && fb) { 836 mga_fb = to_mga_framebuffer(fb); 837 obj = mga_fb->obj; 838 bo = gem_to_mga_bo(obj); 839 ret = mgag200_bo_reserve(bo, false); 840 if (ret) 841 return ret; 842 mgag200_bo_push_sysram(bo); 843 mgag200_bo_unreserve(bo); 844 } 845 846 mga_fb = to_mga_framebuffer(crtc->primary->fb); 847 obj = mga_fb->obj; 848 bo = gem_to_mga_bo(obj); 849 850 ret = mgag200_bo_reserve(bo, false); 851 if (ret) 852 return ret; 853 854 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 855 if (ret) { 856 mgag200_bo_unreserve(bo); 857 return ret; 858 } 859 860 if (&mdev->mfbdev->mfb == mga_fb) { 861 /* if pushing console in kmap it */ 862 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); 863 if (ret) 864 DRM_ERROR("failed to kmap fbcon\n"); 865 866 } 867 mgag200_bo_unreserve(bo); 868 869 mga_set_start_address(crtc, (u32)gpu_addr); 870 871 return 0; 872 } 873 874 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 875 struct drm_framebuffer *old_fb) 876 { 877 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0); 878 } 879 880 static int mga_crtc_mode_set(struct drm_crtc *crtc, 881 struct drm_display_mode *mode, 882 struct drm_display_mode *adjusted_mode, 883 int x, int y, struct drm_framebuffer *old_fb) 884 { 885 struct drm_device *dev = crtc->dev; 886 struct mga_device *mdev = dev->dev_private; 887 int hdisplay, hsyncstart, hsyncend, htotal; 888 int vdisplay, vsyncstart, vsyncend, vtotal; 889 int pitch; 890 int option = 0, option2 = 0; 891 int i; 892 unsigned char misc = 0; 893 unsigned char ext_vga[6]; 894 u8 bppshift; 895 896 static unsigned char dacvalue[] = { 897 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, 898 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, 899 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, 900 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, 901 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 902 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, 903 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, 904 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, 905 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, 906 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 907 }; 908 909 bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1]; 910 911 switch (mdev->type) { 912 case G200_SE_A: 913 case G200_SE_B: 914 dacvalue[MGA1064_VREF_CTL] = 0x03; 915 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 916 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | 917 MGA1064_MISC_CTL_VGA8 | 918 MGA1064_MISC_CTL_DAC_RAM_CS; 919 if (mdev->has_sdram) 920 option = 0x40049120; 921 else 922 option = 0x4004d120; 923 option2 = 0x00008000; 924 break; 925 case G200_WB: 926 case G200_EW3: 927 dacvalue[MGA1064_VREF_CTL] = 0x07; 928 option = 0x41049120; 929 option2 = 0x0000b000; 930 break; 931 case G200_EV: 932 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 933 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 934 MGA1064_MISC_CTL_DAC_RAM_CS; 935 option = 0x00000120; 936 option2 = 0x0000b000; 937 break; 938 case G200_EH: 939 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 940 MGA1064_MISC_CTL_DAC_RAM_CS; 941 option = 0x00000120; 942 option2 = 0x0000b000; 943 break; 944 case G200_ER: 945 break; 946 } 947 948 switch (crtc->primary->fb->bits_per_pixel) { 949 case 8: 950 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits; 951 break; 952 case 16: 953 if (crtc->primary->fb->depth == 15) 954 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits; 955 else 956 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits; 957 break; 958 case 24: 959 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits; 960 break; 961 case 32: 962 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits; 963 break; 964 } 965 966 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 967 misc |= 0x40; 968 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 969 misc |= 0x80; 970 971 972 for (i = 0; i < sizeof(dacvalue); i++) { 973 if ((i <= 0x17) || 974 (i == 0x1b) || 975 (i == 0x1c) || 976 ((i >= 0x1f) && (i <= 0x29)) || 977 ((i >= 0x30) && (i <= 0x37))) 978 continue; 979 if (IS_G200_SE(mdev) && 980 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) 981 continue; 982 if ((mdev->type == G200_EV || 983 mdev->type == G200_WB || 984 mdev->type == G200_EH || 985 mdev->type == G200_EW3) && 986 (i >= 0x44) && (i <= 0x4e)) 987 continue; 988 989 WREG_DAC(i, dacvalue[i]); 990 } 991 992 if (mdev->type == G200_ER) 993 WREG_DAC(0x90, 0); 994 995 if (option) 996 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option); 997 if (option2) 998 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2); 999 1000 WREG_SEQ(2, 0xf); 1001 WREG_SEQ(3, 0); 1002 WREG_SEQ(4, 0xe); 1003 1004 pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8); 1005 if (crtc->primary->fb->bits_per_pixel == 24) 1006 pitch = (pitch * 3) >> (4 - bppshift); 1007 else 1008 pitch = pitch >> (4 - bppshift); 1009 1010 hdisplay = mode->hdisplay / 8 - 1; 1011 hsyncstart = mode->hsync_start / 8 - 1; 1012 hsyncend = mode->hsync_end / 8 - 1; 1013 htotal = mode->htotal / 8 - 1; 1014 1015 /* Work around hardware quirk */ 1016 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 1017 htotal++; 1018 1019 vdisplay = mode->vdisplay - 1; 1020 vsyncstart = mode->vsync_start - 1; 1021 vsyncend = mode->vsync_end - 1; 1022 vtotal = mode->vtotal - 2; 1023 1024 WREG_GFX(0, 0); 1025 WREG_GFX(1, 0); 1026 WREG_GFX(2, 0); 1027 WREG_GFX(3, 0); 1028 WREG_GFX(4, 0); 1029 WREG_GFX(5, 0x40); 1030 WREG_GFX(6, 0x5); 1031 WREG_GFX(7, 0xf); 1032 WREG_GFX(8, 0xf); 1033 1034 WREG_CRT(0, htotal - 4); 1035 WREG_CRT(1, hdisplay); 1036 WREG_CRT(2, hdisplay); 1037 WREG_CRT(3, (htotal & 0x1F) | 0x80); 1038 WREG_CRT(4, hsyncstart); 1039 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 1040 WREG_CRT(6, vtotal & 0xFF); 1041 WREG_CRT(7, ((vtotal & 0x100) >> 8) | 1042 ((vdisplay & 0x100) >> 7) | 1043 ((vsyncstart & 0x100) >> 6) | 1044 ((vdisplay & 0x100) >> 5) | 1045 ((vdisplay & 0x100) >> 4) | /* linecomp */ 1046 ((vtotal & 0x200) >> 4)| 1047 ((vdisplay & 0x200) >> 3) | 1048 ((vsyncstart & 0x200) >> 2)); 1049 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 1050 ((vdisplay & 0x200) >> 3)); 1051 WREG_CRT(10, 0); 1052 WREG_CRT(11, 0); 1053 WREG_CRT(12, 0); 1054 WREG_CRT(13, 0); 1055 WREG_CRT(14, 0); 1056 WREG_CRT(15, 0); 1057 WREG_CRT(16, vsyncstart & 0xFF); 1058 WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 1059 WREG_CRT(18, vdisplay & 0xFF); 1060 WREG_CRT(19, pitch & 0xFF); 1061 WREG_CRT(20, 0); 1062 WREG_CRT(21, vdisplay & 0xFF); 1063 WREG_CRT(22, (vtotal + 1) & 0xFF); 1064 WREG_CRT(23, 0xc3); 1065 WREG_CRT(24, vdisplay & 0xFF); 1066 1067 ext_vga[0] = 0; 1068 ext_vga[5] = 0; 1069 1070 /* TODO interlace */ 1071 1072 ext_vga[0] |= (pitch & 0x300) >> 4; 1073 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) | 1074 ((hdisplay & 0x100) >> 7) | 1075 ((hsyncstart & 0x100) >> 6) | 1076 (htotal & 0x40); 1077 ext_vga[2] = ((vtotal & 0xc00) >> 10) | 1078 ((vdisplay & 0x400) >> 8) | 1079 ((vdisplay & 0xc00) >> 7) | 1080 ((vsyncstart & 0xc00) >> 5) | 1081 ((vdisplay & 0x400) >> 3); 1082 if (crtc->primary->fb->bits_per_pixel == 24) 1083 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80; 1084 else 1085 ext_vga[3] = ((1 << bppshift) - 1) | 0x80; 1086 ext_vga[4] = 0; 1087 if (mdev->type == G200_WB || mdev->type == G200_EW3) 1088 ext_vga[1] |= 0x88; 1089 1090 /* Set pixel clocks */ 1091 misc = 0x2d; 1092 WREG8(MGA_MISC_OUT, misc); 1093 1094 mga_crtc_set_plls(mdev, mode->clock); 1095 1096 for (i = 0; i < 6; i++) { 1097 WREG_ECRT(i, ext_vga[i]); 1098 } 1099 1100 if (mdev->type == G200_ER) 1101 WREG_ECRT(0x24, 0x5); 1102 1103 if (mdev->type == G200_EW3) 1104 WREG_ECRT(0x34, 0x5); 1105 1106 if (mdev->type == G200_EV) { 1107 WREG_ECRT(6, 0); 1108 } 1109 1110 WREG_ECRT(0, ext_vga[0]); 1111 /* Enable mga pixel clock */ 1112 misc = 0x2d; 1113 1114 WREG8(MGA_MISC_OUT, misc); 1115 1116 if (adjusted_mode) 1117 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode)); 1118 1119 mga_crtc_do_set_base(crtc, old_fb, x, y, 0); 1120 1121 /* reset tagfifo */ 1122 if (mdev->type == G200_ER) { 1123 u32 mem_ctl = RREG32(MGAREG_MEMCTL); 1124 u8 seq1; 1125 1126 /* screen off */ 1127 WREG8(MGAREG_SEQ_INDEX, 0x01); 1128 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20; 1129 WREG8(MGAREG_SEQ_DATA, seq1); 1130 1131 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000); 1132 udelay(1000); 1133 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000); 1134 1135 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20); 1136 } 1137 1138 1139 if (IS_G200_SE(mdev)) { 1140 if (mdev->unique_rev_id >= 0x02) { 1141 u8 hi_pri_lvl; 1142 u32 bpp; 1143 u32 mb; 1144 1145 if (crtc->primary->fb->bits_per_pixel > 16) 1146 bpp = 32; 1147 else if (crtc->primary->fb->bits_per_pixel > 8) 1148 bpp = 16; 1149 else 1150 bpp = 8; 1151 1152 mb = (mode->clock * bpp) / 1000; 1153 if (mb > 3100) 1154 hi_pri_lvl = 0; 1155 else if (mb > 2600) 1156 hi_pri_lvl = 1; 1157 else if (mb > 1900) 1158 hi_pri_lvl = 2; 1159 else if (mb > 1160) 1160 hi_pri_lvl = 3; 1161 else if (mb > 440) 1162 hi_pri_lvl = 4; 1163 else 1164 hi_pri_lvl = 5; 1165 1166 WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 1167 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl); 1168 } else { 1169 WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 1170 if (mdev->unique_rev_id >= 0x01) 1171 WREG8(MGAREG_CRTCEXT_DATA, 0x03); 1172 else 1173 WREG8(MGAREG_CRTCEXT_DATA, 0x04); 1174 } 1175 } 1176 return 0; 1177 } 1178 1179 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */ 1180 static int mga_suspend(struct drm_crtc *crtc) 1181 { 1182 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1183 struct drm_device *dev = crtc->dev; 1184 struct mga_device *mdev = dev->dev_private; 1185 struct pci_dev *pdev = dev->pdev; 1186 int option; 1187 1188 if (mdev->suspended) 1189 return 0; 1190 1191 WREG_SEQ(1, 0x20); 1192 WREG_ECRT(1, 0x30); 1193 /* Disable the pixel clock */ 1194 WREG_DAC(0x1a, 0x05); 1195 /* Power down the DAC */ 1196 WREG_DAC(0x1e, 0x18); 1197 /* Power down the pixel PLL */ 1198 WREG_DAC(0x1a, 0x0d); 1199 1200 /* Disable PLLs and clocks */ 1201 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); 1202 option &= ~(0x1F8024); 1203 pci_write_config_dword(pdev, PCI_MGA_OPTION, option); 1204 pci_set_power_state(pdev, PCI_D3hot); 1205 pci_disable_device(pdev); 1206 1207 mdev->suspended = true; 1208 1209 return 0; 1210 } 1211 1212 static int mga_resume(struct drm_crtc *crtc) 1213 { 1214 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1215 struct drm_device *dev = crtc->dev; 1216 struct mga_device *mdev = dev->dev_private; 1217 struct pci_dev *pdev = dev->pdev; 1218 int option; 1219 1220 if (!mdev->suspended) 1221 return 0; 1222 1223 pci_set_power_state(pdev, PCI_D0); 1224 pci_enable_device(pdev); 1225 1226 /* Disable sysclk */ 1227 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); 1228 option &= ~(0x4); 1229 pci_write_config_dword(pdev, PCI_MGA_OPTION, option); 1230 1231 mdev->suspended = false; 1232 1233 return 0; 1234 } 1235 1236 #endif 1237 1238 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode) 1239 { 1240 struct drm_device *dev = crtc->dev; 1241 struct mga_device *mdev = dev->dev_private; 1242 u8 seq1 = 0, crtcext1 = 0; 1243 1244 switch (mode) { 1245 case DRM_MODE_DPMS_ON: 1246 seq1 = 0; 1247 crtcext1 = 0; 1248 mga_crtc_load_lut(crtc); 1249 break; 1250 case DRM_MODE_DPMS_STANDBY: 1251 seq1 = 0x20; 1252 crtcext1 = 0x10; 1253 break; 1254 case DRM_MODE_DPMS_SUSPEND: 1255 seq1 = 0x20; 1256 crtcext1 = 0x20; 1257 break; 1258 case DRM_MODE_DPMS_OFF: 1259 seq1 = 0x20; 1260 crtcext1 = 0x30; 1261 break; 1262 } 1263 1264 #if 0 1265 if (mode == DRM_MODE_DPMS_OFF) { 1266 mga_suspend(crtc); 1267 } 1268 #endif 1269 WREG8(MGAREG_SEQ_INDEX, 0x01); 1270 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20; 1271 mga_wait_vsync(mdev); 1272 mga_wait_busy(mdev); 1273 WREG8(MGAREG_SEQ_DATA, seq1); 1274 msleep(20); 1275 WREG8(MGAREG_CRTCEXT_INDEX, 0x01); 1276 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30; 1277 WREG8(MGAREG_CRTCEXT_DATA, crtcext1); 1278 1279 #if 0 1280 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) { 1281 mga_resume(crtc); 1282 drm_helper_resume_force_mode(dev); 1283 } 1284 #endif 1285 } 1286 1287 /* 1288 * This is called before a mode is programmed. A typical use might be to 1289 * enable DPMS during the programming to avoid seeing intermediate stages, 1290 * but that's not relevant to us 1291 */ 1292 static void mga_crtc_prepare(struct drm_crtc *crtc) 1293 { 1294 struct drm_device *dev = crtc->dev; 1295 struct mga_device *mdev = dev->dev_private; 1296 u8 tmp; 1297 1298 /* mga_resume(crtc);*/ 1299 1300 WREG8(MGAREG_CRTC_INDEX, 0x11); 1301 tmp = RREG8(MGAREG_CRTC_DATA); 1302 WREG_CRT(0x11, tmp | 0x80); 1303 1304 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { 1305 WREG_SEQ(0, 1); 1306 msleep(50); 1307 WREG_SEQ(1, 0x20); 1308 msleep(20); 1309 } else { 1310 WREG8(MGAREG_SEQ_INDEX, 0x1); 1311 tmp = RREG8(MGAREG_SEQ_DATA); 1312 1313 /* start sync reset */ 1314 WREG_SEQ(0, 1); 1315 WREG_SEQ(1, tmp | 0x20); 1316 } 1317 1318 if (mdev->type == G200_WB || mdev->type == G200_EW3) 1319 mga_g200wb_prepare(crtc); 1320 1321 WREG_CRT(17, 0); 1322 } 1323 1324 /* 1325 * This is called after a mode is programmed. It should reverse anything done 1326 * by the prepare function 1327 */ 1328 static void mga_crtc_commit(struct drm_crtc *crtc) 1329 { 1330 struct drm_device *dev = crtc->dev; 1331 struct mga_device *mdev = dev->dev_private; 1332 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 1333 u8 tmp; 1334 1335 if (mdev->type == G200_WB || mdev->type == G200_EW3) 1336 mga_g200wb_commit(crtc); 1337 1338 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { 1339 msleep(50); 1340 WREG_SEQ(1, 0x0); 1341 msleep(20); 1342 WREG_SEQ(0, 0x3); 1343 } else { 1344 WREG8(MGAREG_SEQ_INDEX, 0x1); 1345 tmp = RREG8(MGAREG_SEQ_DATA); 1346 1347 tmp &= ~0x20; 1348 WREG_SEQ(0x1, tmp); 1349 WREG_SEQ(0, 3); 1350 } 1351 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 1352 } 1353 1354 /* 1355 * The core can pass us a set of gamma values to program. We actually only 1356 * use this for 8-bit mode so can't perform smooth fades on deeper modes, 1357 * but it's a requirement that we provide the function 1358 */ 1359 static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 1360 u16 *blue, uint32_t start, uint32_t size) 1361 { 1362 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1363 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size; 1364 int i; 1365 1366 for (i = start; i < end; i++) { 1367 mga_crtc->lut_r[i] = red[i] >> 8; 1368 mga_crtc->lut_g[i] = green[i] >> 8; 1369 mga_crtc->lut_b[i] = blue[i] >> 8; 1370 } 1371 mga_crtc_load_lut(crtc); 1372 } 1373 1374 /* Simple cleanup function */ 1375 static void mga_crtc_destroy(struct drm_crtc *crtc) 1376 { 1377 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1378 1379 drm_crtc_cleanup(crtc); 1380 kfree(mga_crtc); 1381 } 1382 1383 static void mga_crtc_disable(struct drm_crtc *crtc) 1384 { 1385 int ret; 1386 DRM_DEBUG_KMS("\n"); 1387 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1388 if (crtc->primary->fb) { 1389 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb); 1390 struct drm_gem_object *obj = mga_fb->obj; 1391 struct mgag200_bo *bo = gem_to_mga_bo(obj); 1392 ret = mgag200_bo_reserve(bo, false); 1393 if (ret) 1394 return; 1395 mgag200_bo_push_sysram(bo); 1396 mgag200_bo_unreserve(bo); 1397 } 1398 crtc->primary->fb = NULL; 1399 } 1400 1401 /* These provide the minimum set of functions required to handle a CRTC */ 1402 static const struct drm_crtc_funcs mga_crtc_funcs = { 1403 .cursor_set = mga_crtc_cursor_set, 1404 .cursor_move = mga_crtc_cursor_move, 1405 .gamma_set = mga_crtc_gamma_set, 1406 .set_config = drm_crtc_helper_set_config, 1407 .destroy = mga_crtc_destroy, 1408 }; 1409 1410 static const struct drm_crtc_helper_funcs mga_helper_funcs = { 1411 .disable = mga_crtc_disable, 1412 .dpms = mga_crtc_dpms, 1413 .mode_fixup = mga_crtc_mode_fixup, 1414 .mode_set = mga_crtc_mode_set, 1415 .mode_set_base = mga_crtc_mode_set_base, 1416 .prepare = mga_crtc_prepare, 1417 .commit = mga_crtc_commit, 1418 .load_lut = mga_crtc_load_lut, 1419 }; 1420 1421 /* CRTC setup */ 1422 static void mga_crtc_init(struct mga_device *mdev) 1423 { 1424 struct mga_crtc *mga_crtc; 1425 int i; 1426 1427 mga_crtc = kzalloc(sizeof(struct mga_crtc) + 1428 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)), 1429 GFP_KERNEL); 1430 1431 if (mga_crtc == NULL) 1432 return; 1433 1434 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs); 1435 1436 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE); 1437 mdev->mode_info.crtc = mga_crtc; 1438 1439 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 1440 mga_crtc->lut_r[i] = i; 1441 mga_crtc->lut_g[i] = i; 1442 mga_crtc->lut_b[i] = i; 1443 } 1444 1445 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs); 1446 } 1447 1448 /** Sets the color ramps on behalf of fbcon */ 1449 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 1450 u16 blue, int regno) 1451 { 1452 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1453 1454 mga_crtc->lut_r[regno] = red >> 8; 1455 mga_crtc->lut_g[regno] = green >> 8; 1456 mga_crtc->lut_b[regno] = blue >> 8; 1457 } 1458 1459 /** Gets the color ramps on behalf of fbcon */ 1460 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 1461 u16 *blue, int regno) 1462 { 1463 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1464 1465 *red = (u16)mga_crtc->lut_r[regno] << 8; 1466 *green = (u16)mga_crtc->lut_g[regno] << 8; 1467 *blue = (u16)mga_crtc->lut_b[regno] << 8; 1468 } 1469 1470 /* 1471 * The encoder comes after the CRTC in the output pipeline, but before 1472 * the connector. It's responsible for ensuring that the digital 1473 * stream is appropriately converted into the output format. Setup is 1474 * very simple in this case - all we have to do is inform qemu of the 1475 * colour depth in order to ensure that it displays appropriately 1476 */ 1477 1478 /* 1479 * These functions are analagous to those in the CRTC code, but are intended 1480 * to handle any encoder-specific limitations 1481 */ 1482 static bool mga_encoder_mode_fixup(struct drm_encoder *encoder, 1483 const struct drm_display_mode *mode, 1484 struct drm_display_mode *adjusted_mode) 1485 { 1486 return true; 1487 } 1488 1489 static void mga_encoder_mode_set(struct drm_encoder *encoder, 1490 struct drm_display_mode *mode, 1491 struct drm_display_mode *adjusted_mode) 1492 { 1493 1494 } 1495 1496 static void mga_encoder_dpms(struct drm_encoder *encoder, int state) 1497 { 1498 return; 1499 } 1500 1501 static void mga_encoder_prepare(struct drm_encoder *encoder) 1502 { 1503 } 1504 1505 static void mga_encoder_commit(struct drm_encoder *encoder) 1506 { 1507 } 1508 1509 static void mga_encoder_destroy(struct drm_encoder *encoder) 1510 { 1511 struct mga_encoder *mga_encoder = to_mga_encoder(encoder); 1512 drm_encoder_cleanup(encoder); 1513 kfree(mga_encoder); 1514 } 1515 1516 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = { 1517 .dpms = mga_encoder_dpms, 1518 .mode_fixup = mga_encoder_mode_fixup, 1519 .mode_set = mga_encoder_mode_set, 1520 .prepare = mga_encoder_prepare, 1521 .commit = mga_encoder_commit, 1522 }; 1523 1524 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = { 1525 .destroy = mga_encoder_destroy, 1526 }; 1527 1528 static struct drm_encoder *mga_encoder_init(struct drm_device *dev) 1529 { 1530 struct drm_encoder *encoder; 1531 struct mga_encoder *mga_encoder; 1532 1533 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL); 1534 if (!mga_encoder) 1535 return NULL; 1536 1537 encoder = &mga_encoder->base; 1538 encoder->possible_crtcs = 0x1; 1539 1540 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs, 1541 DRM_MODE_ENCODER_DAC); 1542 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs); 1543 1544 return encoder; 1545 } 1546 1547 1548 static int mga_vga_get_modes(struct drm_connector *connector) 1549 { 1550 struct mga_connector *mga_connector = to_mga_connector(connector); 1551 struct edid *edid; 1552 int ret = 0; 1553 1554 edid = drm_get_edid(connector, &mga_connector->i2c->adapter); 1555 if (edid) { 1556 drm_mode_connector_update_edid_property(connector, edid); 1557 ret = drm_add_edid_modes(connector, edid); 1558 kfree(edid); 1559 } 1560 return ret; 1561 } 1562 1563 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode, 1564 int bits_per_pixel) 1565 { 1566 uint32_t total_area, divisor; 1567 int64_t active_area, pixels_per_second, bandwidth; 1568 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 1569 1570 divisor = 1024; 1571 1572 if (!mode->htotal || !mode->vtotal || !mode->clock) 1573 return 0; 1574 1575 active_area = mode->hdisplay * mode->vdisplay; 1576 total_area = mode->htotal * mode->vtotal; 1577 1578 pixels_per_second = active_area * mode->clock * 1000; 1579 do_div(pixels_per_second, total_area); 1580 1581 bandwidth = pixels_per_second * bytes_per_pixel * 100; 1582 do_div(bandwidth, divisor); 1583 1584 return (uint32_t)(bandwidth); 1585 } 1586 1587 #define MODE_BANDWIDTH MODE_BAD 1588 1589 static int mga_vga_mode_valid(struct drm_connector *connector, 1590 struct drm_display_mode *mode) 1591 { 1592 struct drm_device *dev = connector->dev; 1593 struct mga_device *mdev = (struct mga_device*)dev->dev_private; 1594 int bpp = 32; 1595 1596 if (IS_G200_SE(mdev)) { 1597 if (mdev->unique_rev_id == 0x01) { 1598 if (mode->hdisplay > 1600) 1599 return MODE_VIRTUAL_X; 1600 if (mode->vdisplay > 1200) 1601 return MODE_VIRTUAL_Y; 1602 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1603 > (24400 * 1024)) 1604 return MODE_BANDWIDTH; 1605 } else if (mdev->unique_rev_id == 0x02) { 1606 if (mode->hdisplay > 1920) 1607 return MODE_VIRTUAL_X; 1608 if (mode->vdisplay > 1200) 1609 return MODE_VIRTUAL_Y; 1610 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1611 > (30100 * 1024)) 1612 return MODE_BANDWIDTH; 1613 } 1614 } else if (mdev->type == G200_WB) { 1615 if (mode->hdisplay > 1280) 1616 return MODE_VIRTUAL_X; 1617 if (mode->vdisplay > 1024) 1618 return MODE_VIRTUAL_Y; 1619 if (mga_vga_calculate_mode_bandwidth(mode, 1620 bpp > (31877 * 1024))) 1621 return MODE_BANDWIDTH; 1622 } else if (mdev->type == G200_EV && 1623 (mga_vga_calculate_mode_bandwidth(mode, bpp) 1624 > (32700 * 1024))) { 1625 return MODE_BANDWIDTH; 1626 } else if (mdev->type == G200_EH && 1627 (mga_vga_calculate_mode_bandwidth(mode, bpp) 1628 > (37500 * 1024))) { 1629 return MODE_BANDWIDTH; 1630 } else if (mdev->type == G200_ER && 1631 (mga_vga_calculate_mode_bandwidth(mode, 1632 bpp) > (55000 * 1024))) { 1633 return MODE_BANDWIDTH; 1634 } 1635 1636 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 1637 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 1638 return MODE_H_ILLEGAL; 1639 } 1640 1641 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 1642 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 1643 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 1644 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 1645 return MODE_BAD; 1646 } 1647 1648 /* Validate the mode input by the user */ 1649 if (connector->cmdline_mode.specified) { 1650 if (connector->cmdline_mode.bpp_specified) 1651 bpp = connector->cmdline_mode.bpp; 1652 } 1653 1654 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) { 1655 if (connector->cmdline_mode.specified) 1656 connector->cmdline_mode.specified = false; 1657 return MODE_BAD; 1658 } 1659 1660 return MODE_OK; 1661 } 1662 1663 static struct drm_encoder *mga_connector_best_encoder(struct drm_connector 1664 *connector) 1665 { 1666 int enc_id = connector->encoder_ids[0]; 1667 /* pick the encoder ids */ 1668 if (enc_id) 1669 return drm_encoder_find(connector->dev, enc_id); 1670 return NULL; 1671 } 1672 1673 static enum drm_connector_status mga_vga_detect(struct drm_connector 1674 *connector, bool force) 1675 { 1676 return connector_status_connected; 1677 } 1678 1679 static void mga_connector_destroy(struct drm_connector *connector) 1680 { 1681 struct mga_connector *mga_connector = to_mga_connector(connector); 1682 mgag200_i2c_destroy(mga_connector->i2c); 1683 drm_connector_cleanup(connector); 1684 kfree(connector); 1685 } 1686 1687 struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { 1688 .get_modes = mga_vga_get_modes, 1689 .mode_valid = mga_vga_mode_valid, 1690 .best_encoder = mga_connector_best_encoder, 1691 }; 1692 1693 struct drm_connector_funcs mga_vga_connector_funcs = { 1694 .dpms = drm_helper_connector_dpms, 1695 .detect = mga_vga_detect, 1696 .fill_modes = drm_helper_probe_single_connector_modes, 1697 .destroy = mga_connector_destroy, 1698 }; 1699 1700 static struct drm_connector *mga_vga_init(struct drm_device *dev) 1701 { 1702 struct drm_connector *connector; 1703 struct mga_connector *mga_connector; 1704 1705 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL); 1706 if (!mga_connector) 1707 return NULL; 1708 1709 connector = &mga_connector->base; 1710 1711 drm_connector_init(dev, connector, 1712 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA); 1713 1714 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); 1715 1716 drm_connector_register(connector); 1717 1718 mga_connector->i2c = mgag200_i2c_create(dev); 1719 if (!mga_connector->i2c) 1720 DRM_ERROR("failed to add ddc bus\n"); 1721 1722 return connector; 1723 } 1724 1725 1726 int mgag200_modeset_init(struct mga_device *mdev) 1727 { 1728 struct drm_encoder *encoder; 1729 struct drm_connector *connector; 1730 int ret; 1731 1732 mdev->mode_info.mode_config_initialized = true; 1733 1734 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 1735 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 1736 1737 mdev->dev->mode_config.fb_base = mdev->mc.vram_base; 1738 1739 mga_crtc_init(mdev); 1740 1741 encoder = mga_encoder_init(mdev->dev); 1742 if (!encoder) { 1743 DRM_ERROR("mga_encoder_init failed\n"); 1744 return -1; 1745 } 1746 1747 connector = mga_vga_init(mdev->dev); 1748 if (!connector) { 1749 DRM_ERROR("mga_vga_init failed\n"); 1750 return -1; 1751 } 1752 1753 drm_mode_connector_attach_encoder(connector, encoder); 1754 1755 ret = mgag200_fbdev_init(mdev); 1756 if (ret) { 1757 DRM_ERROR("mga_fbdev_init failed\n"); 1758 return ret; 1759 } 1760 1761 return 0; 1762 } 1763 1764 void mgag200_modeset_fini(struct mga_device *mdev) 1765 { 1766 1767 } 1768