1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/dma-buf-map.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_atomic_state_helper.h> 16 #include <drm/drm_crtc_helper.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_format_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem_atomic_helper.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_print.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_simple_kms_helper.h> 26 27 #include "mgag200_drv.h" 28 29 #define MGAG200_LUT_SIZE 256 30 31 /* 32 * This file contains setup code for the CRTC. 33 */ 34 35 static void mga_crtc_load_lut(struct drm_crtc *crtc) 36 { 37 struct drm_device *dev = crtc->dev; 38 struct mga_device *mdev = to_mga_device(dev); 39 struct drm_framebuffer *fb; 40 u16 *r_ptr, *g_ptr, *b_ptr; 41 int i; 42 43 if (!crtc->enabled) 44 return; 45 46 if (!mdev->display_pipe.plane.state) 47 return; 48 49 fb = mdev->display_pipe.plane.state->fb; 50 51 r_ptr = crtc->gamma_store; 52 g_ptr = r_ptr + crtc->gamma_size; 53 b_ptr = g_ptr + crtc->gamma_size; 54 55 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 56 57 if (fb && fb->format->cpp[0] * 8 == 16) { 58 int inc = (fb->format->depth == 15) ? 8 : 4; 59 u8 r, b; 60 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) { 61 if (fb->format->depth == 16) { 62 if (i > (MGAG200_LUT_SIZE >> 1)) { 63 r = b = 0; 64 } else { 65 r = *r_ptr++ >> 8; 66 b = *b_ptr++ >> 8; 67 r_ptr++; 68 b_ptr++; 69 } 70 } else { 71 r = *r_ptr++ >> 8; 72 b = *b_ptr++ >> 8; 73 } 74 /* VGA registers */ 75 WREG8(DAC_INDEX + MGA1064_COL_PAL, r); 76 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); 77 WREG8(DAC_INDEX + MGA1064_COL_PAL, b); 78 } 79 return; 80 } 81 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 82 /* VGA registers */ 83 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8); 84 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); 85 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8); 86 } 87 } 88 89 static inline void mga_wait_vsync(struct mga_device *mdev) 90 { 91 unsigned long timeout = jiffies + HZ/10; 92 unsigned int status = 0; 93 94 do { 95 status = RREG32(MGAREG_Status); 96 } while ((status & 0x08) && time_before(jiffies, timeout)); 97 timeout = jiffies + HZ/10; 98 status = 0; 99 do { 100 status = RREG32(MGAREG_Status); 101 } while (!(status & 0x08) && time_before(jiffies, timeout)); 102 } 103 104 static inline void mga_wait_busy(struct mga_device *mdev) 105 { 106 unsigned long timeout = jiffies + HZ; 107 unsigned int status = 0; 108 do { 109 status = RREG8(MGAREG_Status + 2); 110 } while ((status & 0x01) && time_before(jiffies, timeout)); 111 } 112 113 static void mgag200_g200wb_hold_bmc(struct mga_device *mdev) 114 { 115 u8 tmp; 116 int iter_max; 117 118 /* 1- The first step is to warn the BMC of an upcoming mode change. 119 * We are putting the misc<0> to output.*/ 120 121 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); 122 tmp = RREG8(DAC_DATA); 123 tmp |= 0x10; 124 WREG_DAC(MGA1064_GEN_IO_CTL, tmp); 125 126 /* we are putting a 1 on the misc<0> line */ 127 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 128 tmp = RREG8(DAC_DATA); 129 tmp |= 0x10; 130 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 131 132 /* 2- Second step to mask and further scan request 133 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) 134 */ 135 WREG8(DAC_INDEX, MGA1064_SPAREREG); 136 tmp = RREG8(DAC_DATA); 137 tmp |= 0x80; 138 WREG_DAC(MGA1064_SPAREREG, tmp); 139 140 /* 3a- the third step is to verifu if there is an active scan 141 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) 142 */ 143 iter_max = 300; 144 while (!(tmp & 0x1) && iter_max) { 145 WREG8(DAC_INDEX, MGA1064_SPAREREG); 146 tmp = RREG8(DAC_DATA); 147 udelay(1000); 148 iter_max--; 149 } 150 151 /* 3b- this step occurs only if the remove is actually scanning 152 * we are waiting for the end of the frame which is a 1 on 153 * remvsyncsts (XSPAREREG<1>) 154 */ 155 if (iter_max) { 156 iter_max = 300; 157 while ((tmp & 0x2) && iter_max) { 158 WREG8(DAC_INDEX, MGA1064_SPAREREG); 159 tmp = RREG8(DAC_DATA); 160 udelay(1000); 161 iter_max--; 162 } 163 } 164 } 165 166 static void mgag200_g200wb_release_bmc(struct mga_device *mdev) 167 { 168 u8 tmp; 169 170 /* 1- The first step is to ensure that the vrsten and hrsten are set */ 171 WREG8(MGAREG_CRTCEXT_INDEX, 1); 172 tmp = RREG8(MGAREG_CRTCEXT_DATA); 173 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); 174 175 /* 2- second step is to assert the rstlvl2 */ 176 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 177 tmp = RREG8(DAC_DATA); 178 tmp |= 0x8; 179 WREG8(DAC_DATA, tmp); 180 181 /* wait 10 us */ 182 udelay(10); 183 184 /* 3- deassert rstlvl2 */ 185 tmp &= ~0x08; 186 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 187 WREG8(DAC_DATA, tmp); 188 189 /* 4- remove mask of scan request */ 190 WREG8(DAC_INDEX, MGA1064_SPAREREG); 191 tmp = RREG8(DAC_DATA); 192 tmp &= ~0x80; 193 WREG8(DAC_DATA, tmp); 194 195 /* 5- put back a 0 on the misc<0> line */ 196 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 197 tmp = RREG8(DAC_DATA); 198 tmp &= ~0x10; 199 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 200 } 201 202 /* 203 * This is how the framebuffer base address is stored in g200 cards: 204 * * Assume @offset is the gpu_addr variable of the framebuffer object 205 * * Then addr is the number of _pixels_ (not bytes) from the start of 206 * VRAM to the first pixel we want to display. (divided by 2 for 32bit 207 * framebuffers) 208 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 209 * addr<20> -> CRTCEXT0<6> 210 * addr<19-16> -> CRTCEXT0<3-0> 211 * addr<15-8> -> CRTCC<7-0> 212 * addr<7-0> -> CRTCD<7-0> 213 * 214 * CRTCEXT0 has to be programmed last to trigger an update and make the 215 * new addr variable take effect. 216 */ 217 static void mgag200_set_startadd(struct mga_device *mdev, 218 unsigned long offset) 219 { 220 struct drm_device *dev = &mdev->base; 221 u32 startadd; 222 u8 crtcc, crtcd, crtcext0; 223 224 startadd = offset / 8; 225 226 /* 227 * Can't store addresses any higher than that, but we also 228 * don't have more than 16 MiB of memory, so it should be fine. 229 */ 230 drm_WARN_ON(dev, startadd > 0x1fffff); 231 232 RREG_ECRT(0x00, crtcext0); 233 234 crtcc = (startadd >> 8) & 0xff; 235 crtcd = startadd & 0xff; 236 crtcext0 &= 0xb0; 237 crtcext0 |= ((startadd >> 14) & BIT(6)) | 238 ((startadd >> 16) & 0x0f); 239 240 WREG_CRT(0x0c, crtcc); 241 WREG_CRT(0x0d, crtcd); 242 WREG_ECRT(0x00, crtcext0); 243 } 244 245 static void mgag200_set_dac_regs(struct mga_device *mdev) 246 { 247 size_t i; 248 u8 dacvalue[] = { 249 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, 250 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, 251 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, 252 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, 253 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 254 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, 255 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, 256 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, 257 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, 258 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 259 }; 260 261 switch (mdev->type) { 262 case G200_PCI: 263 case G200_AGP: 264 dacvalue[MGA1064_SYS_PLL_M] = 0x04; 265 dacvalue[MGA1064_SYS_PLL_N] = 0x2D; 266 dacvalue[MGA1064_SYS_PLL_P] = 0x19; 267 break; 268 case G200_SE_A: 269 case G200_SE_B: 270 dacvalue[MGA1064_VREF_CTL] = 0x03; 271 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 272 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | 273 MGA1064_MISC_CTL_VGA8 | 274 MGA1064_MISC_CTL_DAC_RAM_CS; 275 break; 276 case G200_WB: 277 case G200_EW3: 278 dacvalue[MGA1064_VREF_CTL] = 0x07; 279 break; 280 case G200_EV: 281 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 282 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 283 MGA1064_MISC_CTL_DAC_RAM_CS; 284 break; 285 case G200_EH: 286 case G200_EH3: 287 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 288 MGA1064_MISC_CTL_DAC_RAM_CS; 289 break; 290 case G200_ER: 291 break; 292 } 293 294 for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { 295 if ((i <= 0x17) || 296 (i == 0x1b) || 297 (i == 0x1c) || 298 ((i >= 0x1f) && (i <= 0x29)) || 299 ((i >= 0x30) && (i <= 0x37))) 300 continue; 301 if (IS_G200_SE(mdev) && 302 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) 303 continue; 304 if ((mdev->type == G200_EV || 305 mdev->type == G200_WB || 306 mdev->type == G200_EH || 307 mdev->type == G200_EW3 || 308 mdev->type == G200_EH3) && 309 (i >= 0x44) && (i <= 0x4e)) 310 continue; 311 312 WREG_DAC(i, dacvalue[i]); 313 } 314 315 if (mdev->type == G200_ER) 316 WREG_DAC(0x90, 0); 317 } 318 319 static void mgag200_init_regs(struct mga_device *mdev) 320 { 321 u8 crtc11, misc; 322 323 mgag200_set_dac_regs(mdev); 324 325 WREG_SEQ(2, 0x0f); 326 WREG_SEQ(3, 0x00); 327 WREG_SEQ(4, 0x0e); 328 329 WREG_CRT(10, 0); 330 WREG_CRT(11, 0); 331 WREG_CRT(12, 0); 332 WREG_CRT(13, 0); 333 WREG_CRT(14, 0); 334 WREG_CRT(15, 0); 335 336 RREG_CRT(0x11, crtc11); 337 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | 338 MGAREG_CRTC11_VINTEN | 339 MGAREG_CRTC11_VINTCLR); 340 WREG_CRT(0x11, crtc11); 341 342 if (mdev->type == G200_ER) 343 WREG_ECRT(0x24, 0x5); 344 345 if (mdev->type == G200_EW3) 346 WREG_ECRT(0x34, 0x5); 347 348 misc = RREG8(MGA_MISC_IN); 349 misc |= MGAREG_MISC_IOADSEL; 350 WREG8(MGA_MISC_OUT, misc); 351 } 352 353 static void mgag200_set_mode_regs(struct mga_device *mdev, 354 const struct drm_display_mode *mode) 355 { 356 unsigned int hdisplay, hsyncstart, hsyncend, htotal; 357 unsigned int vdisplay, vsyncstart, vsyncend, vtotal; 358 u8 misc, crtcext1, crtcext2, crtcext5; 359 360 hdisplay = mode->hdisplay / 8 - 1; 361 hsyncstart = mode->hsync_start / 8 - 1; 362 hsyncend = mode->hsync_end / 8 - 1; 363 htotal = mode->htotal / 8 - 1; 364 365 /* Work around hardware quirk */ 366 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 367 htotal++; 368 369 vdisplay = mode->vdisplay - 1; 370 vsyncstart = mode->vsync_start - 1; 371 vsyncend = mode->vsync_end - 1; 372 vtotal = mode->vtotal - 2; 373 374 misc = RREG8(MGA_MISC_IN); 375 376 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 377 misc |= MGAREG_MISC_HSYNCPOL; 378 else 379 misc &= ~MGAREG_MISC_HSYNCPOL; 380 381 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 382 misc |= MGAREG_MISC_VSYNCPOL; 383 else 384 misc &= ~MGAREG_MISC_VSYNCPOL; 385 386 crtcext1 = (((htotal - 4) & 0x100) >> 8) | 387 ((hdisplay & 0x100) >> 7) | 388 ((hsyncstart & 0x100) >> 6) | 389 (htotal & 0x40); 390 if (mdev->type == G200_WB || mdev->type == G200_EW3) 391 crtcext1 |= BIT(7) | /* vrsten */ 392 BIT(3); /* hrsten */ 393 394 crtcext2 = ((vtotal & 0xc00) >> 10) | 395 ((vdisplay & 0x400) >> 8) | 396 ((vdisplay & 0xc00) >> 7) | 397 ((vsyncstart & 0xc00) >> 5) | 398 ((vdisplay & 0x400) >> 3); 399 crtcext5 = 0x00; 400 401 WREG_CRT(0, htotal - 4); 402 WREG_CRT(1, hdisplay); 403 WREG_CRT(2, hdisplay); 404 WREG_CRT(3, (htotal & 0x1F) | 0x80); 405 WREG_CRT(4, hsyncstart); 406 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 407 WREG_CRT(6, vtotal & 0xFF); 408 WREG_CRT(7, ((vtotal & 0x100) >> 8) | 409 ((vdisplay & 0x100) >> 7) | 410 ((vsyncstart & 0x100) >> 6) | 411 ((vdisplay & 0x100) >> 5) | 412 ((vdisplay & 0x100) >> 4) | /* linecomp */ 413 ((vtotal & 0x200) >> 4) | 414 ((vdisplay & 0x200) >> 3) | 415 ((vsyncstart & 0x200) >> 2)); 416 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 417 ((vdisplay & 0x200) >> 3)); 418 WREG_CRT(16, vsyncstart & 0xFF); 419 WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 420 WREG_CRT(18, vdisplay & 0xFF); 421 WREG_CRT(20, 0); 422 WREG_CRT(21, vdisplay & 0xFF); 423 WREG_CRT(22, (vtotal + 1) & 0xFF); 424 WREG_CRT(23, 0xc3); 425 WREG_CRT(24, vdisplay & 0xFF); 426 427 WREG_ECRT(0x01, crtcext1); 428 WREG_ECRT(0x02, crtcext2); 429 WREG_ECRT(0x05, crtcext5); 430 431 WREG8(MGA_MISC_OUT, misc); 432 } 433 434 static u8 mgag200_get_bpp_shift(const struct drm_format_info *format) 435 { 436 static const u8 bpp_shift[] = {0, 1, 0, 2}; 437 438 return bpp_shift[format->cpp[0] - 1]; 439 } 440 441 /* 442 * Calculates the HW offset value from the framebuffer's pitch. The 443 * offset is a multiple of the pixel size and depends on the display 444 * format. 445 */ 446 static u32 mgag200_calculate_offset(struct mga_device *mdev, 447 const struct drm_framebuffer *fb) 448 { 449 u32 offset = fb->pitches[0] / fb->format->cpp[0]; 450 u8 bppshift = mgag200_get_bpp_shift(fb->format); 451 452 if (fb->format->cpp[0] * 8 == 24) 453 offset = (offset * 3) >> (4 - bppshift); 454 else 455 offset = offset >> (4 - bppshift); 456 457 return offset; 458 } 459 460 static void mgag200_set_offset(struct mga_device *mdev, 461 const struct drm_framebuffer *fb) 462 { 463 u8 crtc13, crtcext0; 464 u32 offset = mgag200_calculate_offset(mdev, fb); 465 466 RREG_ECRT(0, crtcext0); 467 468 crtc13 = offset & 0xff; 469 470 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK; 471 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK; 472 473 WREG_CRT(0x13, crtc13); 474 WREG_ECRT(0x00, crtcext0); 475 } 476 477 static void mgag200_set_format_regs(struct mga_device *mdev, 478 const struct drm_framebuffer *fb) 479 { 480 struct drm_device *dev = &mdev->base; 481 const struct drm_format_info *format = fb->format; 482 unsigned int bpp, bppshift, scale; 483 u8 crtcext3, xmulctrl; 484 485 bpp = format->cpp[0] * 8; 486 487 bppshift = mgag200_get_bpp_shift(format); 488 switch (bpp) { 489 case 24: 490 scale = ((1 << bppshift) * 3) - 1; 491 break; 492 default: 493 scale = (1 << bppshift) - 1; 494 break; 495 } 496 497 RREG_ECRT(3, crtcext3); 498 499 switch (bpp) { 500 case 8: 501 xmulctrl = MGA1064_MUL_CTL_8bits; 502 break; 503 case 16: 504 if (format->depth == 15) 505 xmulctrl = MGA1064_MUL_CTL_15bits; 506 else 507 xmulctrl = MGA1064_MUL_CTL_16bits; 508 break; 509 case 24: 510 xmulctrl = MGA1064_MUL_CTL_24bits; 511 break; 512 case 32: 513 xmulctrl = MGA1064_MUL_CTL_32_24bits; 514 break; 515 default: 516 /* BUG: We should have caught this problem already. */ 517 drm_WARN_ON(dev, "invalid format depth\n"); 518 return; 519 } 520 521 crtcext3 &= ~GENMASK(2, 0); 522 crtcext3 |= scale; 523 524 WREG_DAC(MGA1064_MUL_CTL, xmulctrl); 525 526 WREG_GFX(0, 0x00); 527 WREG_GFX(1, 0x00); 528 WREG_GFX(2, 0x00); 529 WREG_GFX(3, 0x00); 530 WREG_GFX(4, 0x00); 531 WREG_GFX(5, 0x40); 532 WREG_GFX(6, 0x05); 533 WREG_GFX(7, 0x0f); 534 WREG_GFX(8, 0x0f); 535 536 WREG_ECRT(3, crtcext3); 537 } 538 539 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev) 540 { 541 static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */ 542 u32 memctl; 543 544 memctl = RREG32(MGAREG_MEMCTL); 545 546 memctl |= RESET_FLAG; 547 WREG32(MGAREG_MEMCTL, memctl); 548 549 udelay(1000); 550 551 memctl &= ~RESET_FLAG; 552 WREG32(MGAREG_MEMCTL, memctl); 553 } 554 555 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev, 556 const struct drm_display_mode *mode, 557 const struct drm_framebuffer *fb) 558 { 559 u32 unique_rev_id = mdev->model.g200se.unique_rev_id; 560 unsigned int hiprilvl; 561 u8 crtcext6; 562 563 if (unique_rev_id >= 0x04) { 564 hiprilvl = 0; 565 } else if (unique_rev_id >= 0x02) { 566 unsigned int bpp; 567 unsigned long mb; 568 569 if (fb->format->cpp[0] * 8 > 16) 570 bpp = 32; 571 else if (fb->format->cpp[0] * 8 > 8) 572 bpp = 16; 573 else 574 bpp = 8; 575 576 mb = (mode->clock * bpp) / 1000; 577 if (mb > 3100) 578 hiprilvl = 0; 579 else if (mb > 2600) 580 hiprilvl = 1; 581 else if (mb > 1900) 582 hiprilvl = 2; 583 else if (mb > 1160) 584 hiprilvl = 3; 585 else if (mb > 440) 586 hiprilvl = 4; 587 else 588 hiprilvl = 5; 589 590 } else if (unique_rev_id >= 0x01) { 591 hiprilvl = 3; 592 } else { 593 hiprilvl = 4; 594 } 595 596 crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */ 597 598 WREG_ECRT(0x06, crtcext6); 599 } 600 601 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev) 602 { 603 WREG_ECRT(0x06, 0x00); 604 } 605 606 static void mgag200_enable_display(struct mga_device *mdev) 607 { 608 u8 seq0, seq1, crtcext1; 609 610 RREG_SEQ(0x00, seq0); 611 seq0 |= MGAREG_SEQ0_SYNCRST | 612 MGAREG_SEQ0_ASYNCRST; 613 WREG_SEQ(0x00, seq0); 614 615 /* 616 * TODO: replace busy waiting with vblank IRQ; put 617 * msleep(50) before changing SCROFF 618 */ 619 mga_wait_vsync(mdev); 620 mga_wait_busy(mdev); 621 622 RREG_SEQ(0x01, seq1); 623 seq1 &= ~MGAREG_SEQ1_SCROFF; 624 WREG_SEQ(0x01, seq1); 625 626 msleep(20); 627 628 RREG_ECRT(0x01, crtcext1); 629 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF; 630 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF; 631 WREG_ECRT(0x01, crtcext1); 632 } 633 634 static void mgag200_disable_display(struct mga_device *mdev) 635 { 636 u8 seq0, seq1, crtcext1; 637 638 RREG_SEQ(0x00, seq0); 639 seq0 &= ~MGAREG_SEQ0_SYNCRST; 640 WREG_SEQ(0x00, seq0); 641 642 /* 643 * TODO: replace busy waiting with vblank IRQ; put 644 * msleep(50) before changing SCROFF 645 */ 646 mga_wait_vsync(mdev); 647 mga_wait_busy(mdev); 648 649 RREG_SEQ(0x01, seq1); 650 seq1 |= MGAREG_SEQ1_SCROFF; 651 WREG_SEQ(0x01, seq1); 652 653 msleep(20); 654 655 RREG_ECRT(0x01, crtcext1); 656 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF | 657 MGAREG_CRTCEXT1_HSYNCOFF; 658 WREG_ECRT(0x01, crtcext1); 659 } 660 661 /* 662 * Connector 663 */ 664 665 static int mga_vga_get_modes(struct drm_connector *connector) 666 { 667 struct mga_connector *mga_connector = to_mga_connector(connector); 668 struct edid *edid; 669 int ret = 0; 670 671 edid = drm_get_edid(connector, &mga_connector->i2c->adapter); 672 if (edid) { 673 drm_connector_update_edid_property(connector, edid); 674 ret = drm_add_edid_modes(connector, edid); 675 kfree(edid); 676 } 677 return ret; 678 } 679 680 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode, 681 int bits_per_pixel) 682 { 683 uint32_t total_area, divisor; 684 uint64_t active_area, pixels_per_second, bandwidth; 685 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 686 687 divisor = 1024; 688 689 if (!mode->htotal || !mode->vtotal || !mode->clock) 690 return 0; 691 692 active_area = mode->hdisplay * mode->vdisplay; 693 total_area = mode->htotal * mode->vtotal; 694 695 pixels_per_second = active_area * mode->clock * 1000; 696 do_div(pixels_per_second, total_area); 697 698 bandwidth = pixels_per_second * bytes_per_pixel * 100; 699 do_div(bandwidth, divisor); 700 701 return (uint32_t)(bandwidth); 702 } 703 704 #define MODE_BANDWIDTH MODE_BAD 705 706 static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector, 707 struct drm_display_mode *mode) 708 { 709 struct drm_device *dev = connector->dev; 710 struct mga_device *mdev = to_mga_device(dev); 711 int bpp = 32; 712 713 if (IS_G200_SE(mdev)) { 714 u32 unique_rev_id = mdev->model.g200se.unique_rev_id; 715 716 if (unique_rev_id == 0x01) { 717 if (mode->hdisplay > 1600) 718 return MODE_VIRTUAL_X; 719 if (mode->vdisplay > 1200) 720 return MODE_VIRTUAL_Y; 721 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 722 > (24400 * 1024)) 723 return MODE_BANDWIDTH; 724 } else if (unique_rev_id == 0x02) { 725 if (mode->hdisplay > 1920) 726 return MODE_VIRTUAL_X; 727 if (mode->vdisplay > 1200) 728 return MODE_VIRTUAL_Y; 729 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 730 > (30100 * 1024)) 731 return MODE_BANDWIDTH; 732 } else { 733 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 734 > (55000 * 1024)) 735 return MODE_BANDWIDTH; 736 } 737 } else if (mdev->type == G200_WB) { 738 if (mode->hdisplay > 1280) 739 return MODE_VIRTUAL_X; 740 if (mode->vdisplay > 1024) 741 return MODE_VIRTUAL_Y; 742 if (mga_vga_calculate_mode_bandwidth(mode, bpp) > 743 (31877 * 1024)) 744 return MODE_BANDWIDTH; 745 } else if (mdev->type == G200_EV && 746 (mga_vga_calculate_mode_bandwidth(mode, bpp) 747 > (32700 * 1024))) { 748 return MODE_BANDWIDTH; 749 } else if (mdev->type == G200_EH && 750 (mga_vga_calculate_mode_bandwidth(mode, bpp) 751 > (37500 * 1024))) { 752 return MODE_BANDWIDTH; 753 } else if (mdev->type == G200_ER && 754 (mga_vga_calculate_mode_bandwidth(mode, 755 bpp) > (55000 * 1024))) { 756 return MODE_BANDWIDTH; 757 } 758 759 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 760 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 761 return MODE_H_ILLEGAL; 762 } 763 764 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 765 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 766 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 767 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 768 return MODE_BAD; 769 } 770 771 /* Validate the mode input by the user */ 772 if (connector->cmdline_mode.specified) { 773 if (connector->cmdline_mode.bpp_specified) 774 bpp = connector->cmdline_mode.bpp; 775 } 776 777 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->vram_fb_available) { 778 if (connector->cmdline_mode.specified) 779 connector->cmdline_mode.specified = false; 780 return MODE_BAD; 781 } 782 783 return MODE_OK; 784 } 785 786 static void mga_connector_destroy(struct drm_connector *connector) 787 { 788 struct mga_connector *mga_connector = to_mga_connector(connector); 789 mgag200_i2c_destroy(mga_connector->i2c); 790 drm_connector_cleanup(connector); 791 } 792 793 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { 794 .get_modes = mga_vga_get_modes, 795 .mode_valid = mga_vga_mode_valid, 796 }; 797 798 static const struct drm_connector_funcs mga_vga_connector_funcs = { 799 .reset = drm_atomic_helper_connector_reset, 800 .fill_modes = drm_helper_probe_single_connector_modes, 801 .destroy = mga_connector_destroy, 802 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 803 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 804 }; 805 806 static int mgag200_vga_connector_init(struct mga_device *mdev) 807 { 808 struct drm_device *dev = &mdev->base; 809 struct mga_connector *mconnector = &mdev->connector; 810 struct drm_connector *connector = &mconnector->base; 811 struct mga_i2c_chan *i2c; 812 int ret; 813 814 i2c = mgag200_i2c_create(dev); 815 if (!i2c) 816 drm_warn(dev, "failed to add DDC bus\n"); 817 818 ret = drm_connector_init_with_ddc(dev, connector, 819 &mga_vga_connector_funcs, 820 DRM_MODE_CONNECTOR_VGA, 821 &i2c->adapter); 822 if (ret) 823 goto err_mgag200_i2c_destroy; 824 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); 825 826 mconnector->i2c = i2c; 827 828 return 0; 829 830 err_mgag200_i2c_destroy: 831 mgag200_i2c_destroy(i2c); 832 return ret; 833 } 834 835 /* 836 * Simple Display Pipe 837 */ 838 839 static enum drm_mode_status 840 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 841 const struct drm_display_mode *mode) 842 { 843 return MODE_OK; 844 } 845 846 static void 847 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb, 848 struct drm_rect *clip, const struct dma_buf_map *map) 849 { 850 void __iomem *dst = mdev->vram; 851 void *vmap = map->vaddr; /* TODO: Use mapping abstraction properly */ 852 853 dst += drm_fb_clip_offset(fb->pitches[0], fb->format, clip); 854 drm_fb_memcpy_toio(dst, fb->pitches[0], vmap, fb, clip); 855 856 /* Always scanout image at VRAM offset 0 */ 857 mgag200_set_startadd(mdev, (u32)0); 858 mgag200_set_offset(mdev, fb); 859 } 860 861 static void 862 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe, 863 struct drm_crtc_state *crtc_state, 864 struct drm_plane_state *plane_state) 865 { 866 struct drm_crtc *crtc = &pipe->crtc; 867 struct drm_device *dev = crtc->dev; 868 struct mga_device *mdev = to_mga_device(dev); 869 struct mgag200_pll *pixpll = &mdev->pixpll; 870 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 871 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 872 struct drm_framebuffer *fb = plane_state->fb; 873 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 874 struct drm_rect fullscreen = { 875 .x1 = 0, 876 .x2 = fb->width, 877 .y1 = 0, 878 .y2 = fb->height, 879 }; 880 881 if (mdev->type == G200_WB || mdev->type == G200_EW3) 882 mgag200_g200wb_hold_bmc(mdev); 883 884 mgag200_set_format_regs(mdev, fb); 885 mgag200_set_mode_regs(mdev, adjusted_mode); 886 887 pixpll->funcs->update(pixpll, &mgag200_crtc_state->pixpllc); 888 889 if (mdev->type == G200_ER) 890 mgag200_g200er_reset_tagfifo(mdev); 891 892 if (IS_G200_SE(mdev)) 893 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb); 894 else if (mdev->type == G200_EV) 895 mgag200_g200ev_set_hiprilvl(mdev); 896 897 if (mdev->type == G200_WB || mdev->type == G200_EW3) 898 mgag200_g200wb_release_bmc(mdev); 899 900 mga_crtc_load_lut(crtc); 901 mgag200_enable_display(mdev); 902 903 mgag200_handle_damage(mdev, fb, &fullscreen, &shadow_plane_state->data[0]); 904 } 905 906 static void 907 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe) 908 { 909 struct drm_crtc *crtc = &pipe->crtc; 910 struct mga_device *mdev = to_mga_device(crtc->dev); 911 912 mgag200_disable_display(mdev); 913 } 914 915 static int 916 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe, 917 struct drm_plane_state *plane_state, 918 struct drm_crtc_state *crtc_state) 919 { 920 struct drm_plane *plane = plane_state->plane; 921 struct drm_device *dev = plane->dev; 922 struct mga_device *mdev = to_mga_device(dev); 923 struct mgag200_pll *pixpll = &mdev->pixpll; 924 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 925 struct drm_framebuffer *new_fb = plane_state->fb; 926 struct drm_framebuffer *fb = NULL; 927 int ret; 928 929 if (!new_fb) 930 return 0; 931 932 if (plane->state) 933 fb = plane->state->fb; 934 935 if (!fb || (fb->format != new_fb->format)) 936 crtc_state->mode_changed = true; /* update PLL settings */ 937 938 if (crtc_state->mode_changed) { 939 ret = pixpll->funcs->compute(pixpll, crtc_state->mode.clock, 940 &mgag200_crtc_state->pixpllc); 941 if (ret) 942 return ret; 943 } 944 945 return 0; 946 } 947 948 static void 949 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe, 950 struct drm_plane_state *old_state) 951 { 952 struct drm_plane *plane = &pipe->plane; 953 struct drm_device *dev = plane->dev; 954 struct mga_device *mdev = to_mga_device(dev); 955 struct drm_plane_state *state = plane->state; 956 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state); 957 struct drm_framebuffer *fb = state->fb; 958 struct drm_rect damage; 959 960 if (!fb) 961 return; 962 963 if (drm_atomic_helper_damage_merged(old_state, state, &damage)) 964 mgag200_handle_damage(mdev, fb, &damage, &shadow_plane_state->data[0]); 965 } 966 967 static struct drm_crtc_state * 968 mgag200_simple_display_pipe_duplicate_crtc_state(struct drm_simple_display_pipe *pipe) 969 { 970 struct drm_crtc *crtc = &pipe->crtc; 971 struct drm_crtc_state *crtc_state = crtc->state; 972 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 973 struct mgag200_crtc_state *new_mgag200_crtc_state; 974 975 if (!crtc_state) 976 return NULL; 977 978 new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL); 979 if (!new_mgag200_crtc_state) 980 return NULL; 981 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base); 982 983 memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc, 984 sizeof(new_mgag200_crtc_state->pixpllc)); 985 986 return &new_mgag200_crtc_state->base; 987 } 988 989 static void mgag200_simple_display_pipe_destroy_crtc_state(struct drm_simple_display_pipe *pipe, 990 struct drm_crtc_state *crtc_state) 991 { 992 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 993 994 __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base); 995 kfree(mgag200_crtc_state); 996 } 997 998 static void mgag200_simple_display_pipe_reset_crtc(struct drm_simple_display_pipe *pipe) 999 { 1000 struct drm_crtc *crtc = &pipe->crtc; 1001 struct mgag200_crtc_state *mgag200_crtc_state; 1002 1003 if (crtc->state) { 1004 mgag200_simple_display_pipe_destroy_crtc_state(pipe, crtc->state); 1005 crtc->state = NULL; /* must be set to NULL here */ 1006 } 1007 1008 mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL); 1009 if (!mgag200_crtc_state) 1010 return; 1011 __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base); 1012 } 1013 1014 static const struct drm_simple_display_pipe_funcs 1015 mgag200_simple_display_pipe_funcs = { 1016 .mode_valid = mgag200_simple_display_pipe_mode_valid, 1017 .enable = mgag200_simple_display_pipe_enable, 1018 .disable = mgag200_simple_display_pipe_disable, 1019 .check = mgag200_simple_display_pipe_check, 1020 .update = mgag200_simple_display_pipe_update, 1021 .reset_crtc = mgag200_simple_display_pipe_reset_crtc, 1022 .duplicate_crtc_state = mgag200_simple_display_pipe_duplicate_crtc_state, 1023 .destroy_crtc_state = mgag200_simple_display_pipe_destroy_crtc_state, 1024 DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS, 1025 }; 1026 1027 static const uint32_t mgag200_simple_display_pipe_formats[] = { 1028 DRM_FORMAT_XRGB8888, 1029 DRM_FORMAT_RGB565, 1030 DRM_FORMAT_RGB888, 1031 }; 1032 1033 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = { 1034 DRM_FORMAT_MOD_LINEAR, 1035 DRM_FORMAT_MOD_INVALID 1036 }; 1037 1038 /* 1039 * Mode config 1040 */ 1041 1042 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = { 1043 .fb_create = drm_gem_fb_create_with_dirty, 1044 .atomic_check = drm_atomic_helper_check, 1045 .atomic_commit = drm_atomic_helper_commit, 1046 }; 1047 1048 static unsigned int mgag200_preferred_depth(struct mga_device *mdev) 1049 { 1050 if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024)) 1051 return 16; 1052 else 1053 return 32; 1054 } 1055 1056 int mgag200_modeset_init(struct mga_device *mdev) 1057 { 1058 struct drm_device *dev = &mdev->base; 1059 struct drm_connector *connector = &mdev->connector.base; 1060 struct drm_simple_display_pipe *pipe = &mdev->display_pipe; 1061 size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats); 1062 int ret; 1063 1064 mgag200_init_regs(mdev); 1065 1066 ret = drmm_mode_config_init(dev); 1067 if (ret) { 1068 drm_err(dev, "drmm_mode_config_init() failed, error %d\n", 1069 ret); 1070 return ret; 1071 } 1072 1073 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 1074 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 1075 1076 dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev); 1077 1078 dev->mode_config.fb_base = mdev->mc.vram_base; 1079 1080 dev->mode_config.funcs = &mgag200_mode_config_funcs; 1081 1082 ret = mgag200_vga_connector_init(mdev); 1083 if (ret) { 1084 drm_err(dev, 1085 "mgag200_vga_connector_init() failed, error %d\n", 1086 ret); 1087 return ret; 1088 } 1089 1090 ret = mgag200_pixpll_init(&mdev->pixpll, mdev); 1091 if (ret) 1092 return ret; 1093 1094 ret = drm_simple_display_pipe_init(dev, pipe, 1095 &mgag200_simple_display_pipe_funcs, 1096 mgag200_simple_display_pipe_formats, 1097 format_count, 1098 mgag200_simple_display_pipe_fmtmods, 1099 connector); 1100 if (ret) { 1101 drm_err(dev, 1102 "drm_simple_display_pipe_init() failed, error %d\n", 1103 ret); 1104 return ret; 1105 } 1106 1107 /* FIXME: legacy gamma tables; convert to CRTC state */ 1108 drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE); 1109 1110 drm_mode_config_reset(dev); 1111 1112 return 0; 1113 } 1114