1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 11 #include <linux/delay.h> 12 13 #include <drm/drmP.h> 14 #include <drm/drm_crtc_helper.h> 15 #include <drm/drm_plane_helper.h> 16 #include <drm/drm_probe_helper.h> 17 18 #include "mgag200_drv.h" 19 20 #define MGAG200_LUT_SIZE 256 21 22 /* 23 * This file contains setup code for the CRTC. 24 */ 25 26 static void mga_crtc_load_lut(struct drm_crtc *crtc) 27 { 28 struct drm_device *dev = crtc->dev; 29 struct mga_device *mdev = dev->dev_private; 30 struct drm_framebuffer *fb = crtc->primary->fb; 31 u16 *r_ptr, *g_ptr, *b_ptr; 32 int i; 33 34 if (!crtc->enabled) 35 return; 36 37 r_ptr = crtc->gamma_store; 38 g_ptr = r_ptr + crtc->gamma_size; 39 b_ptr = g_ptr + crtc->gamma_size; 40 41 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 42 43 if (fb && fb->format->cpp[0] * 8 == 16) { 44 int inc = (fb->format->depth == 15) ? 8 : 4; 45 u8 r, b; 46 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) { 47 if (fb->format->depth == 16) { 48 if (i > (MGAG200_LUT_SIZE >> 1)) { 49 r = b = 0; 50 } else { 51 r = *r_ptr++ >> 8; 52 b = *b_ptr++ >> 8; 53 r_ptr++; 54 b_ptr++; 55 } 56 } else { 57 r = *r_ptr++ >> 8; 58 b = *b_ptr++ >> 8; 59 } 60 /* VGA registers */ 61 WREG8(DAC_INDEX + MGA1064_COL_PAL, r); 62 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); 63 WREG8(DAC_INDEX + MGA1064_COL_PAL, b); 64 } 65 return; 66 } 67 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 68 /* VGA registers */ 69 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8); 70 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); 71 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8); 72 } 73 } 74 75 static inline void mga_wait_vsync(struct mga_device *mdev) 76 { 77 unsigned long timeout = jiffies + HZ/10; 78 unsigned int status = 0; 79 80 do { 81 status = RREG32(MGAREG_Status); 82 } while ((status & 0x08) && time_before(jiffies, timeout)); 83 timeout = jiffies + HZ/10; 84 status = 0; 85 do { 86 status = RREG32(MGAREG_Status); 87 } while (!(status & 0x08) && time_before(jiffies, timeout)); 88 } 89 90 static inline void mga_wait_busy(struct mga_device *mdev) 91 { 92 unsigned long timeout = jiffies + HZ; 93 unsigned int status = 0; 94 do { 95 status = RREG8(MGAREG_Status + 2); 96 } while ((status & 0x01) && time_before(jiffies, timeout)); 97 } 98 99 #define P_ARRAY_SIZE 9 100 101 static int mga_g200se_set_plls(struct mga_device *mdev, long clock) 102 { 103 unsigned int vcomax, vcomin, pllreffreq; 104 unsigned int delta, tmpdelta, permitteddelta; 105 unsigned int testp, testm, testn; 106 unsigned int p, m, n; 107 unsigned int computed; 108 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1}; 109 unsigned int fvv; 110 unsigned int i; 111 112 if (mdev->unique_rev_id <= 0x03) { 113 114 m = n = p = 0; 115 vcomax = 320000; 116 vcomin = 160000; 117 pllreffreq = 25000; 118 119 delta = 0xffffffff; 120 permitteddelta = clock * 5 / 1000; 121 122 for (testp = 8; testp > 0; testp /= 2) { 123 if (clock * testp > vcomax) 124 continue; 125 if (clock * testp < vcomin) 126 continue; 127 128 for (testn = 17; testn < 256; testn++) { 129 for (testm = 1; testm < 32; testm++) { 130 computed = (pllreffreq * testn) / 131 (testm * testp); 132 if (computed > clock) 133 tmpdelta = computed - clock; 134 else 135 tmpdelta = clock - computed; 136 if (tmpdelta < delta) { 137 delta = tmpdelta; 138 m = testm - 1; 139 n = testn - 1; 140 p = testp - 1; 141 } 142 } 143 } 144 } 145 } else { 146 147 148 m = n = p = 0; 149 vcomax = 1600000; 150 vcomin = 800000; 151 pllreffreq = 25000; 152 153 if (clock < 25000) 154 clock = 25000; 155 156 clock = clock * 2; 157 158 delta = 0xFFFFFFFF; 159 /* Permited delta is 0.5% as VESA Specification */ 160 permitteddelta = clock * 5 / 1000; 161 162 for (i = 0 ; i < P_ARRAY_SIZE ; i++) { 163 testp = pvalues_e4[i]; 164 165 if ((clock * testp) > vcomax) 166 continue; 167 if ((clock * testp) < vcomin) 168 continue; 169 170 for (testn = 50; testn <= 256; testn++) { 171 for (testm = 1; testm <= 32; testm++) { 172 computed = (pllreffreq * testn) / 173 (testm * testp); 174 if (computed > clock) 175 tmpdelta = computed - clock; 176 else 177 tmpdelta = clock - computed; 178 179 if (tmpdelta < delta) { 180 delta = tmpdelta; 181 m = testm - 1; 182 n = testn - 1; 183 p = testp - 1; 184 } 185 } 186 } 187 } 188 189 fvv = pllreffreq * (n + 1) / (m + 1); 190 fvv = (fvv - 800000) / 50000; 191 192 if (fvv > 15) 193 fvv = 15; 194 195 p |= (fvv << 4); 196 m |= 0x80; 197 198 clock = clock / 2; 199 } 200 201 if (delta > permitteddelta) { 202 pr_warn("PLL delta too large\n"); 203 return 1; 204 } 205 206 WREG_DAC(MGA1064_PIX_PLLC_M, m); 207 WREG_DAC(MGA1064_PIX_PLLC_N, n); 208 WREG_DAC(MGA1064_PIX_PLLC_P, p); 209 210 if (mdev->unique_rev_id >= 0x04) { 211 WREG_DAC(0x1a, 0x09); 212 msleep(20); 213 WREG_DAC(0x1a, 0x01); 214 215 } 216 217 return 0; 218 } 219 220 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock) 221 { 222 unsigned int vcomax, vcomin, pllreffreq; 223 unsigned int delta, tmpdelta; 224 unsigned int testp, testm, testn, testp2; 225 unsigned int p, m, n; 226 unsigned int computed; 227 int i, j, tmpcount, vcount; 228 bool pll_locked = false; 229 u8 tmp; 230 231 m = n = p = 0; 232 233 delta = 0xffffffff; 234 235 if (mdev->type == G200_EW3) { 236 237 vcomax = 800000; 238 vcomin = 400000; 239 pllreffreq = 25000; 240 241 for (testp = 1; testp < 8; testp++) { 242 for (testp2 = 1; testp2 < 8; testp2++) { 243 if (testp < testp2) 244 continue; 245 if ((clock * testp * testp2) > vcomax) 246 continue; 247 if ((clock * testp * testp2) < vcomin) 248 continue; 249 for (testm = 1; testm < 26; testm++) { 250 for (testn = 32; testn < 2048 ; testn++) { 251 computed = (pllreffreq * testn) / 252 (testm * testp * testp2); 253 if (computed > clock) 254 tmpdelta = computed - clock; 255 else 256 tmpdelta = clock - computed; 257 if (tmpdelta < delta) { 258 delta = tmpdelta; 259 m = ((testn & 0x100) >> 1) | 260 (testm); 261 n = (testn & 0xFF); 262 p = ((testn & 0x600) >> 3) | 263 (testp2 << 3) | 264 (testp); 265 } 266 } 267 } 268 } 269 } 270 } else { 271 272 vcomax = 550000; 273 vcomin = 150000; 274 pllreffreq = 48000; 275 276 for (testp = 1; testp < 9; testp++) { 277 if (clock * testp > vcomax) 278 continue; 279 if (clock * testp < vcomin) 280 continue; 281 282 for (testm = 1; testm < 17; testm++) { 283 for (testn = 1; testn < 151; testn++) { 284 computed = (pllreffreq * testn) / 285 (testm * testp); 286 if (computed > clock) 287 tmpdelta = computed - clock; 288 else 289 tmpdelta = clock - computed; 290 if (tmpdelta < delta) { 291 delta = tmpdelta; 292 n = testn - 1; 293 m = (testm - 1) | 294 ((n >> 1) & 0x80); 295 p = testp - 1; 296 } 297 } 298 } 299 } 300 } 301 302 for (i = 0; i <= 32 && pll_locked == false; i++) { 303 if (i > 0) { 304 WREG8(MGAREG_CRTC_INDEX, 0x1e); 305 tmp = RREG8(MGAREG_CRTC_DATA); 306 if (tmp < 0xff) 307 WREG8(MGAREG_CRTC_DATA, tmp+1); 308 } 309 310 /* set pixclkdis to 1 */ 311 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 312 tmp = RREG8(DAC_DATA); 313 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 314 WREG8(DAC_DATA, tmp); 315 316 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 317 tmp = RREG8(DAC_DATA); 318 tmp |= MGA1064_REMHEADCTL_CLKDIS; 319 WREG8(DAC_DATA, tmp); 320 321 /* select PLL Set C */ 322 tmp = RREG8(MGAREG_MEM_MISC_READ); 323 tmp |= 0x3 << 2; 324 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 325 326 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 327 tmp = RREG8(DAC_DATA); 328 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80; 329 WREG8(DAC_DATA, tmp); 330 331 udelay(500); 332 333 /* reset the PLL */ 334 WREG8(DAC_INDEX, MGA1064_VREF_CTL); 335 tmp = RREG8(DAC_DATA); 336 tmp &= ~0x04; 337 WREG8(DAC_DATA, tmp); 338 339 udelay(50); 340 341 /* program pixel pll register */ 342 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n); 343 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m); 344 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p); 345 346 udelay(50); 347 348 /* turn pll on */ 349 WREG8(DAC_INDEX, MGA1064_VREF_CTL); 350 tmp = RREG8(DAC_DATA); 351 tmp |= 0x04; 352 WREG_DAC(MGA1064_VREF_CTL, tmp); 353 354 udelay(500); 355 356 /* select the pixel pll */ 357 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 358 tmp = RREG8(DAC_DATA); 359 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 360 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 361 WREG8(DAC_DATA, tmp); 362 363 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 364 tmp = RREG8(DAC_DATA); 365 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK; 366 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL; 367 WREG8(DAC_DATA, tmp); 368 369 /* reset dotclock rate bit */ 370 WREG8(MGAREG_SEQ_INDEX, 1); 371 tmp = RREG8(MGAREG_SEQ_DATA); 372 tmp &= ~0x8; 373 WREG8(MGAREG_SEQ_DATA, tmp); 374 375 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 376 tmp = RREG8(DAC_DATA); 377 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 378 WREG8(DAC_DATA, tmp); 379 380 vcount = RREG8(MGAREG_VCOUNT); 381 382 for (j = 0; j < 30 && pll_locked == false; j++) { 383 tmpcount = RREG8(MGAREG_VCOUNT); 384 if (tmpcount < vcount) 385 vcount = 0; 386 if ((tmpcount - vcount) > 2) 387 pll_locked = true; 388 else 389 udelay(5); 390 } 391 } 392 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 393 tmp = RREG8(DAC_DATA); 394 tmp &= ~MGA1064_REMHEADCTL_CLKDIS; 395 WREG_DAC(MGA1064_REMHEADCTL, tmp); 396 return 0; 397 } 398 399 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock) 400 { 401 unsigned int vcomax, vcomin, pllreffreq; 402 unsigned int delta, tmpdelta; 403 unsigned int testp, testm, testn; 404 unsigned int p, m, n; 405 unsigned int computed; 406 u8 tmp; 407 408 m = n = p = 0; 409 vcomax = 550000; 410 vcomin = 150000; 411 pllreffreq = 50000; 412 413 delta = 0xffffffff; 414 415 for (testp = 16; testp > 0; testp--) { 416 if (clock * testp > vcomax) 417 continue; 418 if (clock * testp < vcomin) 419 continue; 420 421 for (testn = 1; testn < 257; testn++) { 422 for (testm = 1; testm < 17; testm++) { 423 computed = (pllreffreq * testn) / 424 (testm * testp); 425 if (computed > clock) 426 tmpdelta = computed - clock; 427 else 428 tmpdelta = clock - computed; 429 if (tmpdelta < delta) { 430 delta = tmpdelta; 431 n = testn - 1; 432 m = testm - 1; 433 p = testp - 1; 434 } 435 } 436 } 437 } 438 439 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 440 tmp = RREG8(DAC_DATA); 441 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 442 WREG8(DAC_DATA, tmp); 443 444 tmp = RREG8(MGAREG_MEM_MISC_READ); 445 tmp |= 0x3 << 2; 446 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 447 448 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 449 tmp = RREG8(DAC_DATA); 450 WREG8(DAC_DATA, tmp & ~0x40); 451 452 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 453 tmp = RREG8(DAC_DATA); 454 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 455 WREG8(DAC_DATA, tmp); 456 457 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m); 458 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n); 459 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p); 460 461 udelay(50); 462 463 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 464 tmp = RREG8(DAC_DATA); 465 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 466 WREG8(DAC_DATA, tmp); 467 468 udelay(500); 469 470 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 471 tmp = RREG8(DAC_DATA); 472 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 473 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 474 WREG8(DAC_DATA, tmp); 475 476 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 477 tmp = RREG8(DAC_DATA); 478 WREG8(DAC_DATA, tmp | 0x40); 479 480 tmp = RREG8(MGAREG_MEM_MISC_READ); 481 tmp |= (0x3 << 2); 482 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 483 484 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 485 tmp = RREG8(DAC_DATA); 486 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 487 WREG8(DAC_DATA, tmp); 488 489 return 0; 490 } 491 492 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock) 493 { 494 unsigned int vcomax, vcomin, pllreffreq; 495 unsigned int delta, tmpdelta; 496 unsigned int testp, testm, testn; 497 unsigned int p, m, n; 498 unsigned int computed; 499 int i, j, tmpcount, vcount; 500 u8 tmp; 501 bool pll_locked = false; 502 503 m = n = p = 0; 504 505 if (mdev->type == G200_EH3) { 506 vcomax = 3000000; 507 vcomin = 1500000; 508 pllreffreq = 25000; 509 510 delta = 0xffffffff; 511 512 testp = 0; 513 514 for (testm = 150; testm >= 6; testm--) { 515 if (clock * testm > vcomax) 516 continue; 517 if (clock * testm < vcomin) 518 continue; 519 for (testn = 120; testn >= 60; testn--) { 520 computed = (pllreffreq * testn) / testm; 521 if (computed > clock) 522 tmpdelta = computed - clock; 523 else 524 tmpdelta = clock - computed; 525 if (tmpdelta < delta) { 526 delta = tmpdelta; 527 n = testn; 528 m = testm; 529 p = testp; 530 } 531 if (delta == 0) 532 break; 533 } 534 if (delta == 0) 535 break; 536 } 537 } else { 538 539 vcomax = 800000; 540 vcomin = 400000; 541 pllreffreq = 33333; 542 543 delta = 0xffffffff; 544 545 for (testp = 16; testp > 0; testp >>= 1) { 546 if (clock * testp > vcomax) 547 continue; 548 if (clock * testp < vcomin) 549 continue; 550 551 for (testm = 1; testm < 33; testm++) { 552 for (testn = 17; testn < 257; testn++) { 553 computed = (pllreffreq * testn) / 554 (testm * testp); 555 if (computed > clock) 556 tmpdelta = computed - clock; 557 else 558 tmpdelta = clock - computed; 559 if (tmpdelta < delta) { 560 delta = tmpdelta; 561 n = testn - 1; 562 m = (testm - 1); 563 p = testp - 1; 564 } 565 if ((clock * testp) >= 600000) 566 p |= 0x80; 567 } 568 } 569 } 570 } 571 for (i = 0; i <= 32 && pll_locked == false; i++) { 572 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 573 tmp = RREG8(DAC_DATA); 574 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 575 WREG8(DAC_DATA, tmp); 576 577 tmp = RREG8(MGAREG_MEM_MISC_READ); 578 tmp |= 0x3 << 2; 579 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 580 581 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 582 tmp = RREG8(DAC_DATA); 583 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 584 WREG8(DAC_DATA, tmp); 585 586 udelay(500); 587 588 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m); 589 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n); 590 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p); 591 592 udelay(500); 593 594 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 595 tmp = RREG8(DAC_DATA); 596 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 597 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 598 WREG8(DAC_DATA, tmp); 599 600 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 601 tmp = RREG8(DAC_DATA); 602 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 603 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 604 WREG8(DAC_DATA, tmp); 605 606 vcount = RREG8(MGAREG_VCOUNT); 607 608 for (j = 0; j < 30 && pll_locked == false; j++) { 609 tmpcount = RREG8(MGAREG_VCOUNT); 610 if (tmpcount < vcount) 611 vcount = 0; 612 if ((tmpcount - vcount) > 2) 613 pll_locked = true; 614 else 615 udelay(5); 616 } 617 } 618 619 return 0; 620 } 621 622 static int mga_g200er_set_plls(struct mga_device *mdev, long clock) 623 { 624 unsigned int vcomax, vcomin, pllreffreq; 625 unsigned int delta, tmpdelta; 626 int testr, testn, testm, testo; 627 unsigned int p, m, n; 628 unsigned int computed, vco; 629 int tmp; 630 const unsigned int m_div_val[] = { 1, 2, 4, 8 }; 631 632 m = n = p = 0; 633 vcomax = 1488000; 634 vcomin = 1056000; 635 pllreffreq = 48000; 636 637 delta = 0xffffffff; 638 639 for (testr = 0; testr < 4; testr++) { 640 if (delta == 0) 641 break; 642 for (testn = 5; testn < 129; testn++) { 643 if (delta == 0) 644 break; 645 for (testm = 3; testm >= 0; testm--) { 646 if (delta == 0) 647 break; 648 for (testo = 5; testo < 33; testo++) { 649 vco = pllreffreq * (testn + 1) / 650 (testr + 1); 651 if (vco < vcomin) 652 continue; 653 if (vco > vcomax) 654 continue; 655 computed = vco / (m_div_val[testm] * (testo + 1)); 656 if (computed > clock) 657 tmpdelta = computed - clock; 658 else 659 tmpdelta = clock - computed; 660 if (tmpdelta < delta) { 661 delta = tmpdelta; 662 m = testm | (testo << 3); 663 n = testn; 664 p = testr | (testr << 3); 665 } 666 } 667 } 668 } 669 } 670 671 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 672 tmp = RREG8(DAC_DATA); 673 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 674 WREG8(DAC_DATA, tmp); 675 676 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 677 tmp = RREG8(DAC_DATA); 678 tmp |= MGA1064_REMHEADCTL_CLKDIS; 679 WREG8(DAC_DATA, tmp); 680 681 tmp = RREG8(MGAREG_MEM_MISC_READ); 682 tmp |= (0x3<<2) | 0xc0; 683 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 684 685 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 686 tmp = RREG8(DAC_DATA); 687 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 688 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 689 WREG8(DAC_DATA, tmp); 690 691 udelay(500); 692 693 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n); 694 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m); 695 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p); 696 697 udelay(50); 698 699 return 0; 700 } 701 702 static int mga_crtc_set_plls(struct mga_device *mdev, long clock) 703 { 704 switch(mdev->type) { 705 case G200_SE_A: 706 case G200_SE_B: 707 return mga_g200se_set_plls(mdev, clock); 708 break; 709 case G200_WB: 710 case G200_EW3: 711 return mga_g200wb_set_plls(mdev, clock); 712 break; 713 case G200_EV: 714 return mga_g200ev_set_plls(mdev, clock); 715 break; 716 case G200_EH: 717 case G200_EH3: 718 return mga_g200eh_set_plls(mdev, clock); 719 break; 720 case G200_ER: 721 return mga_g200er_set_plls(mdev, clock); 722 break; 723 } 724 return 0; 725 } 726 727 static void mga_g200wb_prepare(struct drm_crtc *crtc) 728 { 729 struct mga_device *mdev = crtc->dev->dev_private; 730 u8 tmp; 731 int iter_max; 732 733 /* 1- The first step is to warn the BMC of an upcoming mode change. 734 * We are putting the misc<0> to output.*/ 735 736 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); 737 tmp = RREG8(DAC_DATA); 738 tmp |= 0x10; 739 WREG_DAC(MGA1064_GEN_IO_CTL, tmp); 740 741 /* we are putting a 1 on the misc<0> line */ 742 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 743 tmp = RREG8(DAC_DATA); 744 tmp |= 0x10; 745 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 746 747 /* 2- Second step to mask and further scan request 748 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) 749 */ 750 WREG8(DAC_INDEX, MGA1064_SPAREREG); 751 tmp = RREG8(DAC_DATA); 752 tmp |= 0x80; 753 WREG_DAC(MGA1064_SPAREREG, tmp); 754 755 /* 3a- the third step is to verifu if there is an active scan 756 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) 757 */ 758 iter_max = 300; 759 while (!(tmp & 0x1) && iter_max) { 760 WREG8(DAC_INDEX, MGA1064_SPAREREG); 761 tmp = RREG8(DAC_DATA); 762 udelay(1000); 763 iter_max--; 764 } 765 766 /* 3b- this step occurs only if the remove is actually scanning 767 * we are waiting for the end of the frame which is a 1 on 768 * remvsyncsts (XSPAREREG<1>) 769 */ 770 if (iter_max) { 771 iter_max = 300; 772 while ((tmp & 0x2) && iter_max) { 773 WREG8(DAC_INDEX, MGA1064_SPAREREG); 774 tmp = RREG8(DAC_DATA); 775 udelay(1000); 776 iter_max--; 777 } 778 } 779 } 780 781 static void mga_g200wb_commit(struct drm_crtc *crtc) 782 { 783 u8 tmp; 784 struct mga_device *mdev = crtc->dev->dev_private; 785 786 /* 1- The first step is to ensure that the vrsten and hrsten are set */ 787 WREG8(MGAREG_CRTCEXT_INDEX, 1); 788 tmp = RREG8(MGAREG_CRTCEXT_DATA); 789 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); 790 791 /* 2- second step is to assert the rstlvl2 */ 792 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 793 tmp = RREG8(DAC_DATA); 794 tmp |= 0x8; 795 WREG8(DAC_DATA, tmp); 796 797 /* wait 10 us */ 798 udelay(10); 799 800 /* 3- deassert rstlvl2 */ 801 tmp &= ~0x08; 802 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 803 WREG8(DAC_DATA, tmp); 804 805 /* 4- remove mask of scan request */ 806 WREG8(DAC_INDEX, MGA1064_SPAREREG); 807 tmp = RREG8(DAC_DATA); 808 tmp &= ~0x80; 809 WREG8(DAC_DATA, tmp); 810 811 /* 5- put back a 0 on the misc<0> line */ 812 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 813 tmp = RREG8(DAC_DATA); 814 tmp &= ~0x10; 815 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 816 } 817 818 /* 819 This is how the framebuffer base address is stored in g200 cards: 820 * Assume @offset is the gpu_addr variable of the framebuffer object 821 * Then addr is the number of _pixels_ (not bytes) from the start of 822 VRAM to the first pixel we want to display. (divided by 2 for 32bit 823 framebuffers) 824 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 825 addr<20> -> CRTCEXT0<6> 826 addr<19-16> -> CRTCEXT0<3-0> 827 addr<15-8> -> CRTCC<7-0> 828 addr<7-0> -> CRTCD<7-0> 829 CRTCEXT0 has to be programmed last to trigger an update and make the 830 new addr variable take effect. 831 */ 832 static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset) 833 { 834 struct mga_device *mdev = crtc->dev->dev_private; 835 u32 addr; 836 int count; 837 u8 crtcext0; 838 839 while (RREG8(0x1fda) & 0x08); 840 while (!(RREG8(0x1fda) & 0x08)); 841 842 count = RREG8(MGAREG_VCOUNT) + 2; 843 while (RREG8(MGAREG_VCOUNT) < count); 844 845 WREG8(MGAREG_CRTCEXT_INDEX, 0); 846 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA); 847 crtcext0 &= 0xB0; 848 addr = offset / 8; 849 /* Can't store addresses any higher than that... 850 but we also don't have more than 16MB of memory, so it should be fine. */ 851 WARN_ON(addr > 0x1fffff); 852 crtcext0 |= (!!(addr & (1<<20)))<<6; 853 WREG_CRT(0x0d, (u8)(addr & 0xff)); 854 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff); 855 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0); 856 } 857 858 859 /* ast is different - we will force move buffers out of VRAM */ 860 static int mga_crtc_do_set_base(struct drm_crtc *crtc, 861 struct drm_framebuffer *fb, 862 int x, int y, int atomic) 863 { 864 struct mga_device *mdev = crtc->dev->dev_private; 865 struct drm_gem_object *obj; 866 struct mga_framebuffer *mga_fb; 867 struct mgag200_bo *bo; 868 int ret; 869 u64 gpu_addr; 870 871 /* push the previous fb to system ram */ 872 if (!atomic && fb) { 873 mga_fb = to_mga_framebuffer(fb); 874 obj = mga_fb->obj; 875 bo = gem_to_mga_bo(obj); 876 ret = mgag200_bo_reserve(bo, false); 877 if (ret) 878 return ret; 879 mgag200_bo_push_sysram(bo); 880 mgag200_bo_unreserve(bo); 881 } 882 883 mga_fb = to_mga_framebuffer(crtc->primary->fb); 884 obj = mga_fb->obj; 885 bo = gem_to_mga_bo(obj); 886 887 ret = mgag200_bo_reserve(bo, false); 888 if (ret) 889 return ret; 890 891 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 892 if (ret) { 893 mgag200_bo_unreserve(bo); 894 return ret; 895 } 896 897 if (&mdev->mfbdev->mfb == mga_fb) { 898 /* if pushing console in kmap it */ 899 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); 900 if (ret) 901 DRM_ERROR("failed to kmap fbcon\n"); 902 903 } 904 mgag200_bo_unreserve(bo); 905 906 mga_set_start_address(crtc, (u32)gpu_addr); 907 908 return 0; 909 } 910 911 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 912 struct drm_framebuffer *old_fb) 913 { 914 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0); 915 } 916 917 static int mga_crtc_mode_set(struct drm_crtc *crtc, 918 struct drm_display_mode *mode, 919 struct drm_display_mode *adjusted_mode, 920 int x, int y, struct drm_framebuffer *old_fb) 921 { 922 struct drm_device *dev = crtc->dev; 923 struct mga_device *mdev = dev->dev_private; 924 const struct drm_framebuffer *fb = crtc->primary->fb; 925 int hdisplay, hsyncstart, hsyncend, htotal; 926 int vdisplay, vsyncstart, vsyncend, vtotal; 927 int pitch; 928 int option = 0, option2 = 0; 929 int i; 930 unsigned char misc = 0; 931 unsigned char ext_vga[6]; 932 u8 bppshift; 933 934 static unsigned char dacvalue[] = { 935 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, 936 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, 937 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, 938 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, 939 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 940 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, 941 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, 942 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, 943 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, 944 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 945 }; 946 947 bppshift = mdev->bpp_shifts[fb->format->cpp[0] - 1]; 948 949 switch (mdev->type) { 950 case G200_SE_A: 951 case G200_SE_B: 952 dacvalue[MGA1064_VREF_CTL] = 0x03; 953 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 954 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | 955 MGA1064_MISC_CTL_VGA8 | 956 MGA1064_MISC_CTL_DAC_RAM_CS; 957 if (mdev->has_sdram) 958 option = 0x40049120; 959 else 960 option = 0x4004d120; 961 option2 = 0x00008000; 962 break; 963 case G200_WB: 964 case G200_EW3: 965 dacvalue[MGA1064_VREF_CTL] = 0x07; 966 option = 0x41049120; 967 option2 = 0x0000b000; 968 break; 969 case G200_EV: 970 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 971 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 972 MGA1064_MISC_CTL_DAC_RAM_CS; 973 option = 0x00000120; 974 option2 = 0x0000b000; 975 break; 976 case G200_EH: 977 case G200_EH3: 978 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 979 MGA1064_MISC_CTL_DAC_RAM_CS; 980 option = 0x00000120; 981 option2 = 0x0000b000; 982 break; 983 case G200_ER: 984 break; 985 } 986 987 switch (fb->format->cpp[0] * 8) { 988 case 8: 989 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits; 990 break; 991 case 16: 992 if (fb->format->depth == 15) 993 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits; 994 else 995 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits; 996 break; 997 case 24: 998 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits; 999 break; 1000 case 32: 1001 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits; 1002 break; 1003 } 1004 1005 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1006 misc |= 0x40; 1007 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1008 misc |= 0x80; 1009 1010 1011 for (i = 0; i < sizeof(dacvalue); i++) { 1012 if ((i <= 0x17) || 1013 (i == 0x1b) || 1014 (i == 0x1c) || 1015 ((i >= 0x1f) && (i <= 0x29)) || 1016 ((i >= 0x30) && (i <= 0x37))) 1017 continue; 1018 if (IS_G200_SE(mdev) && 1019 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) 1020 continue; 1021 if ((mdev->type == G200_EV || 1022 mdev->type == G200_WB || 1023 mdev->type == G200_EH || 1024 mdev->type == G200_EW3 || 1025 mdev->type == G200_EH3) && 1026 (i >= 0x44) && (i <= 0x4e)) 1027 continue; 1028 1029 WREG_DAC(i, dacvalue[i]); 1030 } 1031 1032 if (mdev->type == G200_ER) 1033 WREG_DAC(0x90, 0); 1034 1035 if (option) 1036 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option); 1037 if (option2) 1038 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2); 1039 1040 WREG_SEQ(2, 0xf); 1041 WREG_SEQ(3, 0); 1042 WREG_SEQ(4, 0xe); 1043 1044 pitch = fb->pitches[0] / fb->format->cpp[0]; 1045 if (fb->format->cpp[0] * 8 == 24) 1046 pitch = (pitch * 3) >> (4 - bppshift); 1047 else 1048 pitch = pitch >> (4 - bppshift); 1049 1050 hdisplay = mode->hdisplay / 8 - 1; 1051 hsyncstart = mode->hsync_start / 8 - 1; 1052 hsyncend = mode->hsync_end / 8 - 1; 1053 htotal = mode->htotal / 8 - 1; 1054 1055 /* Work around hardware quirk */ 1056 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 1057 htotal++; 1058 1059 vdisplay = mode->vdisplay - 1; 1060 vsyncstart = mode->vsync_start - 1; 1061 vsyncend = mode->vsync_end - 1; 1062 vtotal = mode->vtotal - 2; 1063 1064 WREG_GFX(0, 0); 1065 WREG_GFX(1, 0); 1066 WREG_GFX(2, 0); 1067 WREG_GFX(3, 0); 1068 WREG_GFX(4, 0); 1069 WREG_GFX(5, 0x40); 1070 WREG_GFX(6, 0x5); 1071 WREG_GFX(7, 0xf); 1072 WREG_GFX(8, 0xf); 1073 1074 WREG_CRT(0, htotal - 4); 1075 WREG_CRT(1, hdisplay); 1076 WREG_CRT(2, hdisplay); 1077 WREG_CRT(3, (htotal & 0x1F) | 0x80); 1078 WREG_CRT(4, hsyncstart); 1079 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 1080 WREG_CRT(6, vtotal & 0xFF); 1081 WREG_CRT(7, ((vtotal & 0x100) >> 8) | 1082 ((vdisplay & 0x100) >> 7) | 1083 ((vsyncstart & 0x100) >> 6) | 1084 ((vdisplay & 0x100) >> 5) | 1085 ((vdisplay & 0x100) >> 4) | /* linecomp */ 1086 ((vtotal & 0x200) >> 4)| 1087 ((vdisplay & 0x200) >> 3) | 1088 ((vsyncstart & 0x200) >> 2)); 1089 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 1090 ((vdisplay & 0x200) >> 3)); 1091 WREG_CRT(10, 0); 1092 WREG_CRT(11, 0); 1093 WREG_CRT(12, 0); 1094 WREG_CRT(13, 0); 1095 WREG_CRT(14, 0); 1096 WREG_CRT(15, 0); 1097 WREG_CRT(16, vsyncstart & 0xFF); 1098 WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 1099 WREG_CRT(18, vdisplay & 0xFF); 1100 WREG_CRT(19, pitch & 0xFF); 1101 WREG_CRT(20, 0); 1102 WREG_CRT(21, vdisplay & 0xFF); 1103 WREG_CRT(22, (vtotal + 1) & 0xFF); 1104 WREG_CRT(23, 0xc3); 1105 WREG_CRT(24, vdisplay & 0xFF); 1106 1107 ext_vga[0] = 0; 1108 ext_vga[5] = 0; 1109 1110 /* TODO interlace */ 1111 1112 ext_vga[0] |= (pitch & 0x300) >> 4; 1113 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) | 1114 ((hdisplay & 0x100) >> 7) | 1115 ((hsyncstart & 0x100) >> 6) | 1116 (htotal & 0x40); 1117 ext_vga[2] = ((vtotal & 0xc00) >> 10) | 1118 ((vdisplay & 0x400) >> 8) | 1119 ((vdisplay & 0xc00) >> 7) | 1120 ((vsyncstart & 0xc00) >> 5) | 1121 ((vdisplay & 0x400) >> 3); 1122 if (fb->format->cpp[0] * 8 == 24) 1123 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80; 1124 else 1125 ext_vga[3] = ((1 << bppshift) - 1) | 0x80; 1126 ext_vga[4] = 0; 1127 if (mdev->type == G200_WB || mdev->type == G200_EW3) 1128 ext_vga[1] |= 0x88; 1129 1130 /* Set pixel clocks */ 1131 misc = 0x2d; 1132 WREG8(MGA_MISC_OUT, misc); 1133 1134 mga_crtc_set_plls(mdev, mode->clock); 1135 1136 for (i = 0; i < 6; i++) { 1137 WREG_ECRT(i, ext_vga[i]); 1138 } 1139 1140 if (mdev->type == G200_ER) 1141 WREG_ECRT(0x24, 0x5); 1142 1143 if (mdev->type == G200_EW3) 1144 WREG_ECRT(0x34, 0x5); 1145 1146 if (mdev->type == G200_EV) { 1147 WREG_ECRT(6, 0); 1148 } 1149 1150 WREG_ECRT(0, ext_vga[0]); 1151 /* Enable mga pixel clock */ 1152 misc = 0x2d; 1153 1154 WREG8(MGA_MISC_OUT, misc); 1155 1156 if (adjusted_mode) 1157 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode)); 1158 1159 mga_crtc_do_set_base(crtc, old_fb, x, y, 0); 1160 1161 /* reset tagfifo */ 1162 if (mdev->type == G200_ER) { 1163 u32 mem_ctl = RREG32(MGAREG_MEMCTL); 1164 u8 seq1; 1165 1166 /* screen off */ 1167 WREG8(MGAREG_SEQ_INDEX, 0x01); 1168 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20; 1169 WREG8(MGAREG_SEQ_DATA, seq1); 1170 1171 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000); 1172 udelay(1000); 1173 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000); 1174 1175 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20); 1176 } 1177 1178 1179 if (IS_G200_SE(mdev)) { 1180 if (mdev->unique_rev_id >= 0x04) { 1181 WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 1182 WREG8(MGAREG_CRTCEXT_DATA, 0); 1183 } else if (mdev->unique_rev_id >= 0x02) { 1184 u8 hi_pri_lvl; 1185 u32 bpp; 1186 u32 mb; 1187 1188 if (fb->format->cpp[0] * 8 > 16) 1189 bpp = 32; 1190 else if (fb->format->cpp[0] * 8 > 8) 1191 bpp = 16; 1192 else 1193 bpp = 8; 1194 1195 mb = (mode->clock * bpp) / 1000; 1196 if (mb > 3100) 1197 hi_pri_lvl = 0; 1198 else if (mb > 2600) 1199 hi_pri_lvl = 1; 1200 else if (mb > 1900) 1201 hi_pri_lvl = 2; 1202 else if (mb > 1160) 1203 hi_pri_lvl = 3; 1204 else if (mb > 440) 1205 hi_pri_lvl = 4; 1206 else 1207 hi_pri_lvl = 5; 1208 1209 WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 1210 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl); 1211 } else { 1212 WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 1213 if (mdev->unique_rev_id >= 0x01) 1214 WREG8(MGAREG_CRTCEXT_DATA, 0x03); 1215 else 1216 WREG8(MGAREG_CRTCEXT_DATA, 0x04); 1217 } 1218 } 1219 return 0; 1220 } 1221 1222 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */ 1223 static int mga_suspend(struct drm_crtc *crtc) 1224 { 1225 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1226 struct drm_device *dev = crtc->dev; 1227 struct mga_device *mdev = dev->dev_private; 1228 struct pci_dev *pdev = dev->pdev; 1229 int option; 1230 1231 if (mdev->suspended) 1232 return 0; 1233 1234 WREG_SEQ(1, 0x20); 1235 WREG_ECRT(1, 0x30); 1236 /* Disable the pixel clock */ 1237 WREG_DAC(0x1a, 0x05); 1238 /* Power down the DAC */ 1239 WREG_DAC(0x1e, 0x18); 1240 /* Power down the pixel PLL */ 1241 WREG_DAC(0x1a, 0x0d); 1242 1243 /* Disable PLLs and clocks */ 1244 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); 1245 option &= ~(0x1F8024); 1246 pci_write_config_dword(pdev, PCI_MGA_OPTION, option); 1247 pci_set_power_state(pdev, PCI_D3hot); 1248 pci_disable_device(pdev); 1249 1250 mdev->suspended = true; 1251 1252 return 0; 1253 } 1254 1255 static int mga_resume(struct drm_crtc *crtc) 1256 { 1257 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1258 struct drm_device *dev = crtc->dev; 1259 struct mga_device *mdev = dev->dev_private; 1260 struct pci_dev *pdev = dev->pdev; 1261 int option; 1262 1263 if (!mdev->suspended) 1264 return 0; 1265 1266 pci_set_power_state(pdev, PCI_D0); 1267 pci_enable_device(pdev); 1268 1269 /* Disable sysclk */ 1270 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); 1271 option &= ~(0x4); 1272 pci_write_config_dword(pdev, PCI_MGA_OPTION, option); 1273 1274 mdev->suspended = false; 1275 1276 return 0; 1277 } 1278 1279 #endif 1280 1281 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode) 1282 { 1283 struct drm_device *dev = crtc->dev; 1284 struct mga_device *mdev = dev->dev_private; 1285 u8 seq1 = 0, crtcext1 = 0; 1286 1287 switch (mode) { 1288 case DRM_MODE_DPMS_ON: 1289 seq1 = 0; 1290 crtcext1 = 0; 1291 mga_crtc_load_lut(crtc); 1292 break; 1293 case DRM_MODE_DPMS_STANDBY: 1294 seq1 = 0x20; 1295 crtcext1 = 0x10; 1296 break; 1297 case DRM_MODE_DPMS_SUSPEND: 1298 seq1 = 0x20; 1299 crtcext1 = 0x20; 1300 break; 1301 case DRM_MODE_DPMS_OFF: 1302 seq1 = 0x20; 1303 crtcext1 = 0x30; 1304 break; 1305 } 1306 1307 #if 0 1308 if (mode == DRM_MODE_DPMS_OFF) { 1309 mga_suspend(crtc); 1310 } 1311 #endif 1312 WREG8(MGAREG_SEQ_INDEX, 0x01); 1313 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20; 1314 mga_wait_vsync(mdev); 1315 mga_wait_busy(mdev); 1316 WREG8(MGAREG_SEQ_DATA, seq1); 1317 msleep(20); 1318 WREG8(MGAREG_CRTCEXT_INDEX, 0x01); 1319 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30; 1320 WREG8(MGAREG_CRTCEXT_DATA, crtcext1); 1321 1322 #if 0 1323 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) { 1324 mga_resume(crtc); 1325 drm_helper_resume_force_mode(dev); 1326 } 1327 #endif 1328 } 1329 1330 /* 1331 * This is called before a mode is programmed. A typical use might be to 1332 * enable DPMS during the programming to avoid seeing intermediate stages, 1333 * but that's not relevant to us 1334 */ 1335 static void mga_crtc_prepare(struct drm_crtc *crtc) 1336 { 1337 struct drm_device *dev = crtc->dev; 1338 struct mga_device *mdev = dev->dev_private; 1339 u8 tmp; 1340 1341 /* mga_resume(crtc);*/ 1342 1343 WREG8(MGAREG_CRTC_INDEX, 0x11); 1344 tmp = RREG8(MGAREG_CRTC_DATA); 1345 WREG_CRT(0x11, tmp | 0x80); 1346 1347 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { 1348 WREG_SEQ(0, 1); 1349 msleep(50); 1350 WREG_SEQ(1, 0x20); 1351 msleep(20); 1352 } else { 1353 WREG8(MGAREG_SEQ_INDEX, 0x1); 1354 tmp = RREG8(MGAREG_SEQ_DATA); 1355 1356 /* start sync reset */ 1357 WREG_SEQ(0, 1); 1358 WREG_SEQ(1, tmp | 0x20); 1359 } 1360 1361 if (mdev->type == G200_WB || mdev->type == G200_EW3) 1362 mga_g200wb_prepare(crtc); 1363 1364 WREG_CRT(17, 0); 1365 } 1366 1367 /* 1368 * This is called after a mode is programmed. It should reverse anything done 1369 * by the prepare function 1370 */ 1371 static void mga_crtc_commit(struct drm_crtc *crtc) 1372 { 1373 struct drm_device *dev = crtc->dev; 1374 struct mga_device *mdev = dev->dev_private; 1375 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 1376 u8 tmp; 1377 1378 if (mdev->type == G200_WB || mdev->type == G200_EW3) 1379 mga_g200wb_commit(crtc); 1380 1381 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { 1382 msleep(50); 1383 WREG_SEQ(1, 0x0); 1384 msleep(20); 1385 WREG_SEQ(0, 0x3); 1386 } else { 1387 WREG8(MGAREG_SEQ_INDEX, 0x1); 1388 tmp = RREG8(MGAREG_SEQ_DATA); 1389 1390 tmp &= ~0x20; 1391 WREG_SEQ(0x1, tmp); 1392 WREG_SEQ(0, 3); 1393 } 1394 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 1395 } 1396 1397 /* 1398 * The core can pass us a set of gamma values to program. We actually only 1399 * use this for 8-bit mode so can't perform smooth fades on deeper modes, 1400 * but it's a requirement that we provide the function 1401 */ 1402 static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 1403 u16 *blue, uint32_t size, 1404 struct drm_modeset_acquire_ctx *ctx) 1405 { 1406 mga_crtc_load_lut(crtc); 1407 1408 return 0; 1409 } 1410 1411 /* Simple cleanup function */ 1412 static void mga_crtc_destroy(struct drm_crtc *crtc) 1413 { 1414 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1415 1416 drm_crtc_cleanup(crtc); 1417 kfree(mga_crtc); 1418 } 1419 1420 static void mga_crtc_disable(struct drm_crtc *crtc) 1421 { 1422 int ret; 1423 DRM_DEBUG_KMS("\n"); 1424 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1425 if (crtc->primary->fb) { 1426 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb); 1427 struct drm_gem_object *obj = mga_fb->obj; 1428 struct mgag200_bo *bo = gem_to_mga_bo(obj); 1429 ret = mgag200_bo_reserve(bo, false); 1430 if (ret) 1431 return; 1432 mgag200_bo_push_sysram(bo); 1433 mgag200_bo_unreserve(bo); 1434 } 1435 crtc->primary->fb = NULL; 1436 } 1437 1438 /* These provide the minimum set of functions required to handle a CRTC */ 1439 static const struct drm_crtc_funcs mga_crtc_funcs = { 1440 .cursor_set = mga_crtc_cursor_set, 1441 .cursor_move = mga_crtc_cursor_move, 1442 .gamma_set = mga_crtc_gamma_set, 1443 .set_config = drm_crtc_helper_set_config, 1444 .destroy = mga_crtc_destroy, 1445 }; 1446 1447 static const struct drm_crtc_helper_funcs mga_helper_funcs = { 1448 .disable = mga_crtc_disable, 1449 .dpms = mga_crtc_dpms, 1450 .mode_set = mga_crtc_mode_set, 1451 .mode_set_base = mga_crtc_mode_set_base, 1452 .prepare = mga_crtc_prepare, 1453 .commit = mga_crtc_commit, 1454 }; 1455 1456 /* CRTC setup */ 1457 static void mga_crtc_init(struct mga_device *mdev) 1458 { 1459 struct mga_crtc *mga_crtc; 1460 1461 mga_crtc = kzalloc(sizeof(struct mga_crtc) + 1462 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)), 1463 GFP_KERNEL); 1464 1465 if (mga_crtc == NULL) 1466 return; 1467 1468 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs); 1469 1470 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE); 1471 mdev->mode_info.crtc = mga_crtc; 1472 1473 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs); 1474 } 1475 1476 /* 1477 * The encoder comes after the CRTC in the output pipeline, but before 1478 * the connector. It's responsible for ensuring that the digital 1479 * stream is appropriately converted into the output format. Setup is 1480 * very simple in this case - all we have to do is inform qemu of the 1481 * colour depth in order to ensure that it displays appropriately 1482 */ 1483 1484 /* 1485 * These functions are analagous to those in the CRTC code, but are intended 1486 * to handle any encoder-specific limitations 1487 */ 1488 static void mga_encoder_mode_set(struct drm_encoder *encoder, 1489 struct drm_display_mode *mode, 1490 struct drm_display_mode *adjusted_mode) 1491 { 1492 1493 } 1494 1495 static void mga_encoder_dpms(struct drm_encoder *encoder, int state) 1496 { 1497 return; 1498 } 1499 1500 static void mga_encoder_prepare(struct drm_encoder *encoder) 1501 { 1502 } 1503 1504 static void mga_encoder_commit(struct drm_encoder *encoder) 1505 { 1506 } 1507 1508 static void mga_encoder_destroy(struct drm_encoder *encoder) 1509 { 1510 struct mga_encoder *mga_encoder = to_mga_encoder(encoder); 1511 drm_encoder_cleanup(encoder); 1512 kfree(mga_encoder); 1513 } 1514 1515 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = { 1516 .dpms = mga_encoder_dpms, 1517 .mode_set = mga_encoder_mode_set, 1518 .prepare = mga_encoder_prepare, 1519 .commit = mga_encoder_commit, 1520 }; 1521 1522 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = { 1523 .destroy = mga_encoder_destroy, 1524 }; 1525 1526 static struct drm_encoder *mga_encoder_init(struct drm_device *dev) 1527 { 1528 struct drm_encoder *encoder; 1529 struct mga_encoder *mga_encoder; 1530 1531 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL); 1532 if (!mga_encoder) 1533 return NULL; 1534 1535 encoder = &mga_encoder->base; 1536 encoder->possible_crtcs = 0x1; 1537 1538 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs, 1539 DRM_MODE_ENCODER_DAC, NULL); 1540 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs); 1541 1542 return encoder; 1543 } 1544 1545 1546 static int mga_vga_get_modes(struct drm_connector *connector) 1547 { 1548 struct mga_connector *mga_connector = to_mga_connector(connector); 1549 struct edid *edid; 1550 int ret = 0; 1551 1552 edid = drm_get_edid(connector, &mga_connector->i2c->adapter); 1553 if (edid) { 1554 drm_connector_update_edid_property(connector, edid); 1555 ret = drm_add_edid_modes(connector, edid); 1556 kfree(edid); 1557 } 1558 return ret; 1559 } 1560 1561 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode, 1562 int bits_per_pixel) 1563 { 1564 uint32_t total_area, divisor; 1565 uint64_t active_area, pixels_per_second, bandwidth; 1566 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 1567 1568 divisor = 1024; 1569 1570 if (!mode->htotal || !mode->vtotal || !mode->clock) 1571 return 0; 1572 1573 active_area = mode->hdisplay * mode->vdisplay; 1574 total_area = mode->htotal * mode->vtotal; 1575 1576 pixels_per_second = active_area * mode->clock * 1000; 1577 do_div(pixels_per_second, total_area); 1578 1579 bandwidth = pixels_per_second * bytes_per_pixel * 100; 1580 do_div(bandwidth, divisor); 1581 1582 return (uint32_t)(bandwidth); 1583 } 1584 1585 #define MODE_BANDWIDTH MODE_BAD 1586 1587 static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector, 1588 struct drm_display_mode *mode) 1589 { 1590 struct drm_device *dev = connector->dev; 1591 struct mga_device *mdev = (struct mga_device*)dev->dev_private; 1592 int bpp = 32; 1593 1594 if (IS_G200_SE(mdev)) { 1595 if (mdev->unique_rev_id == 0x01) { 1596 if (mode->hdisplay > 1600) 1597 return MODE_VIRTUAL_X; 1598 if (mode->vdisplay > 1200) 1599 return MODE_VIRTUAL_Y; 1600 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1601 > (24400 * 1024)) 1602 return MODE_BANDWIDTH; 1603 } else if (mdev->unique_rev_id == 0x02) { 1604 if (mode->hdisplay > 1920) 1605 return MODE_VIRTUAL_X; 1606 if (mode->vdisplay > 1200) 1607 return MODE_VIRTUAL_Y; 1608 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1609 > (30100 * 1024)) 1610 return MODE_BANDWIDTH; 1611 } else { 1612 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1613 > (55000 * 1024)) 1614 return MODE_BANDWIDTH; 1615 } 1616 } else if (mdev->type == G200_WB) { 1617 if (mode->hdisplay > 1280) 1618 return MODE_VIRTUAL_X; 1619 if (mode->vdisplay > 1024) 1620 return MODE_VIRTUAL_Y; 1621 if (mga_vga_calculate_mode_bandwidth(mode, bpp) > 1622 (31877 * 1024)) 1623 return MODE_BANDWIDTH; 1624 } else if (mdev->type == G200_EV && 1625 (mga_vga_calculate_mode_bandwidth(mode, bpp) 1626 > (32700 * 1024))) { 1627 return MODE_BANDWIDTH; 1628 } else if (mdev->type == G200_EH && 1629 (mga_vga_calculate_mode_bandwidth(mode, bpp) 1630 > (37500 * 1024))) { 1631 return MODE_BANDWIDTH; 1632 } else if (mdev->type == G200_ER && 1633 (mga_vga_calculate_mode_bandwidth(mode, 1634 bpp) > (55000 * 1024))) { 1635 return MODE_BANDWIDTH; 1636 } 1637 1638 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 1639 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 1640 return MODE_H_ILLEGAL; 1641 } 1642 1643 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 1644 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 1645 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 1646 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 1647 return MODE_BAD; 1648 } 1649 1650 /* Validate the mode input by the user */ 1651 if (connector->cmdline_mode.specified) { 1652 if (connector->cmdline_mode.bpp_specified) 1653 bpp = connector->cmdline_mode.bpp; 1654 } 1655 1656 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) { 1657 if (connector->cmdline_mode.specified) 1658 connector->cmdline_mode.specified = false; 1659 return MODE_BAD; 1660 } 1661 1662 return MODE_OK; 1663 } 1664 1665 static struct drm_encoder *mga_connector_best_encoder(struct drm_connector 1666 *connector) 1667 { 1668 int enc_id = connector->encoder_ids[0]; 1669 /* pick the encoder ids */ 1670 if (enc_id) 1671 return drm_encoder_find(connector->dev, NULL, enc_id); 1672 return NULL; 1673 } 1674 1675 static void mga_connector_destroy(struct drm_connector *connector) 1676 { 1677 struct mga_connector *mga_connector = to_mga_connector(connector); 1678 mgag200_i2c_destroy(mga_connector->i2c); 1679 drm_connector_cleanup(connector); 1680 kfree(connector); 1681 } 1682 1683 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { 1684 .get_modes = mga_vga_get_modes, 1685 .mode_valid = mga_vga_mode_valid, 1686 .best_encoder = mga_connector_best_encoder, 1687 }; 1688 1689 static const struct drm_connector_funcs mga_vga_connector_funcs = { 1690 .dpms = drm_helper_connector_dpms, 1691 .fill_modes = drm_helper_probe_single_connector_modes, 1692 .destroy = mga_connector_destroy, 1693 }; 1694 1695 static struct drm_connector *mga_vga_init(struct drm_device *dev) 1696 { 1697 struct drm_connector *connector; 1698 struct mga_connector *mga_connector; 1699 1700 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL); 1701 if (!mga_connector) 1702 return NULL; 1703 1704 connector = &mga_connector->base; 1705 1706 drm_connector_init(dev, connector, 1707 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA); 1708 1709 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); 1710 1711 drm_connector_register(connector); 1712 1713 mga_connector->i2c = mgag200_i2c_create(dev); 1714 if (!mga_connector->i2c) 1715 DRM_ERROR("failed to add ddc bus\n"); 1716 1717 return connector; 1718 } 1719 1720 1721 int mgag200_modeset_init(struct mga_device *mdev) 1722 { 1723 struct drm_encoder *encoder; 1724 struct drm_connector *connector; 1725 int ret; 1726 1727 mdev->mode_info.mode_config_initialized = true; 1728 1729 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 1730 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 1731 1732 mdev->dev->mode_config.fb_base = mdev->mc.vram_base; 1733 1734 mga_crtc_init(mdev); 1735 1736 encoder = mga_encoder_init(mdev->dev); 1737 if (!encoder) { 1738 DRM_ERROR("mga_encoder_init failed\n"); 1739 return -1; 1740 } 1741 1742 connector = mga_vga_init(mdev->dev); 1743 if (!connector) { 1744 DRM_ERROR("mga_vga_init failed\n"); 1745 return -1; 1746 } 1747 1748 drm_connector_attach_encoder(connector, encoder); 1749 1750 ret = mgag200_fbdev_init(mdev); 1751 if (ret) { 1752 DRM_ERROR("mga_fbdev_init failed\n"); 1753 return ret; 1754 } 1755 1756 return 0; 1757 } 1758 1759 void mgag200_modeset_fini(struct mga_device *mdev) 1760 { 1761 1762 } 1763