1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/iosys-map.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_atomic_state_helper.h> 16 #include <drm/drm_crtc_helper.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_format_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem_atomic_helper.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_print.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_simple_kms_helper.h> 26 27 #include "mgag200_drv.h" 28 29 #define MGAG200_LUT_SIZE 256 30 31 /* 32 * This file contains setup code for the CRTC. 33 */ 34 35 static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, 36 const struct drm_format_info *format) 37 { 38 int i; 39 40 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 41 42 switch (format->format) { 43 case DRM_FORMAT_RGB565: 44 /* Use better interpolation, to take 32 values from 0 to 255 */ 45 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 46 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 47 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 48 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 49 } 50 /* Green has one more bit, so add padding with 0 for red and blue. */ 51 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 52 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 53 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 54 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 55 } 56 break; 57 case DRM_FORMAT_RGB888: 58 case DRM_FORMAT_XRGB8888: 59 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 60 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 61 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 62 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 63 } 64 break; 65 default: 66 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 67 &format->format); 68 break; 69 } 70 } 71 72 static void mgag200_crtc_set_gamma(struct mga_device *mdev, 73 const struct drm_format_info *format, 74 struct drm_color_lut *lut) 75 { 76 int i; 77 78 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 79 80 switch (format->format) { 81 case DRM_FORMAT_RGB565: 82 /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ 83 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 84 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].red >> 8); 85 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 86 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].blue >> 8); 87 } 88 /* Green has one more bit, so add padding with 0 for red and blue. */ 89 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 90 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 91 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 92 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 93 } 94 break; 95 case DRM_FORMAT_RGB888: 96 case DRM_FORMAT_XRGB8888: 97 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 98 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].red >> 8); 99 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].green >> 8); 100 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].blue >> 8); 101 } 102 break; 103 default: 104 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 105 &format->format); 106 break; 107 } 108 } 109 110 static inline void mga_wait_vsync(struct mga_device *mdev) 111 { 112 unsigned long timeout = jiffies + HZ/10; 113 unsigned int status = 0; 114 115 do { 116 status = RREG32(MGAREG_Status); 117 } while ((status & 0x08) && time_before(jiffies, timeout)); 118 timeout = jiffies + HZ/10; 119 status = 0; 120 do { 121 status = RREG32(MGAREG_Status); 122 } while (!(status & 0x08) && time_before(jiffies, timeout)); 123 } 124 125 static inline void mga_wait_busy(struct mga_device *mdev) 126 { 127 unsigned long timeout = jiffies + HZ; 128 unsigned int status = 0; 129 do { 130 status = RREG8(MGAREG_Status + 2); 131 } while ((status & 0x01) && time_before(jiffies, timeout)); 132 } 133 134 static void mgag200_g200wb_hold_bmc(struct mga_device *mdev) 135 { 136 u8 tmp; 137 int iter_max; 138 139 /* 1- The first step is to warn the BMC of an upcoming mode change. 140 * We are putting the misc<0> to output.*/ 141 142 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); 143 tmp = RREG8(DAC_DATA); 144 tmp |= 0x10; 145 WREG_DAC(MGA1064_GEN_IO_CTL, tmp); 146 147 /* we are putting a 1 on the misc<0> line */ 148 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 149 tmp = RREG8(DAC_DATA); 150 tmp |= 0x10; 151 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 152 153 /* 2- Second step to mask and further scan request 154 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) 155 */ 156 WREG8(DAC_INDEX, MGA1064_SPAREREG); 157 tmp = RREG8(DAC_DATA); 158 tmp |= 0x80; 159 WREG_DAC(MGA1064_SPAREREG, tmp); 160 161 /* 3a- the third step is to verifu if there is an active scan 162 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) 163 */ 164 iter_max = 300; 165 while (!(tmp & 0x1) && iter_max) { 166 WREG8(DAC_INDEX, MGA1064_SPAREREG); 167 tmp = RREG8(DAC_DATA); 168 udelay(1000); 169 iter_max--; 170 } 171 172 /* 3b- this step occurs only if the remove is actually scanning 173 * we are waiting for the end of the frame which is a 1 on 174 * remvsyncsts (XSPAREREG<1>) 175 */ 176 if (iter_max) { 177 iter_max = 300; 178 while ((tmp & 0x2) && iter_max) { 179 WREG8(DAC_INDEX, MGA1064_SPAREREG); 180 tmp = RREG8(DAC_DATA); 181 udelay(1000); 182 iter_max--; 183 } 184 } 185 } 186 187 static void mgag200_g200wb_release_bmc(struct mga_device *mdev) 188 { 189 u8 tmp; 190 191 /* 1- The first step is to ensure that the vrsten and hrsten are set */ 192 WREG8(MGAREG_CRTCEXT_INDEX, 1); 193 tmp = RREG8(MGAREG_CRTCEXT_DATA); 194 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); 195 196 /* 2- second step is to assert the rstlvl2 */ 197 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 198 tmp = RREG8(DAC_DATA); 199 tmp |= 0x8; 200 WREG8(DAC_DATA, tmp); 201 202 /* wait 10 us */ 203 udelay(10); 204 205 /* 3- deassert rstlvl2 */ 206 tmp &= ~0x08; 207 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 208 WREG8(DAC_DATA, tmp); 209 210 /* 4- remove mask of scan request */ 211 WREG8(DAC_INDEX, MGA1064_SPAREREG); 212 tmp = RREG8(DAC_DATA); 213 tmp &= ~0x80; 214 WREG8(DAC_DATA, tmp); 215 216 /* 5- put back a 0 on the misc<0> line */ 217 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 218 tmp = RREG8(DAC_DATA); 219 tmp &= ~0x10; 220 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 221 } 222 223 /* 224 * This is how the framebuffer base address is stored in g200 cards: 225 * * Assume @offset is the gpu_addr variable of the framebuffer object 226 * * Then addr is the number of _pixels_ (not bytes) from the start of 227 * VRAM to the first pixel we want to display. (divided by 2 for 32bit 228 * framebuffers) 229 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 230 * addr<20> -> CRTCEXT0<6> 231 * addr<19-16> -> CRTCEXT0<3-0> 232 * addr<15-8> -> CRTCC<7-0> 233 * addr<7-0> -> CRTCD<7-0> 234 * 235 * CRTCEXT0 has to be programmed last to trigger an update and make the 236 * new addr variable take effect. 237 */ 238 static void mgag200_set_startadd(struct mga_device *mdev, 239 unsigned long offset) 240 { 241 struct drm_device *dev = &mdev->base; 242 u32 startadd; 243 u8 crtcc, crtcd, crtcext0; 244 245 startadd = offset / 8; 246 247 if (startadd > 0) 248 drm_WARN_ON_ONCE(dev, mdev->flags & MGAG200_FLAG_HW_BUG_NO_STARTADD); 249 250 /* 251 * Can't store addresses any higher than that, but we also 252 * don't have more than 16 MiB of memory, so it should be fine. 253 */ 254 drm_WARN_ON(dev, startadd > 0x1fffff); 255 256 RREG_ECRT(0x00, crtcext0); 257 258 crtcc = (startadd >> 8) & 0xff; 259 crtcd = startadd & 0xff; 260 crtcext0 &= 0xb0; 261 crtcext0 |= ((startadd >> 14) & BIT(6)) | 262 ((startadd >> 16) & 0x0f); 263 264 WREG_CRT(0x0c, crtcc); 265 WREG_CRT(0x0d, crtcd); 266 WREG_ECRT(0x00, crtcext0); 267 } 268 269 static void mgag200_set_dac_regs(struct mga_device *mdev) 270 { 271 size_t i; 272 u8 dacvalue[] = { 273 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, 274 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, 275 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, 276 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, 277 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 278 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, 279 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, 280 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, 281 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, 282 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 283 }; 284 285 switch (mdev->type) { 286 case G200_PCI: 287 case G200_AGP: 288 dacvalue[MGA1064_SYS_PLL_M] = 0x04; 289 dacvalue[MGA1064_SYS_PLL_N] = 0x2D; 290 dacvalue[MGA1064_SYS_PLL_P] = 0x19; 291 break; 292 case G200_SE_A: 293 case G200_SE_B: 294 dacvalue[MGA1064_VREF_CTL] = 0x03; 295 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 296 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | 297 MGA1064_MISC_CTL_VGA8 | 298 MGA1064_MISC_CTL_DAC_RAM_CS; 299 break; 300 case G200_WB: 301 case G200_EW3: 302 dacvalue[MGA1064_VREF_CTL] = 0x07; 303 break; 304 case G200_EV: 305 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 306 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 307 MGA1064_MISC_CTL_DAC_RAM_CS; 308 break; 309 case G200_EH: 310 case G200_EH3: 311 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 312 MGA1064_MISC_CTL_DAC_RAM_CS; 313 break; 314 case G200_ER: 315 break; 316 } 317 318 for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { 319 if ((i <= 0x17) || 320 (i == 0x1b) || 321 (i == 0x1c) || 322 ((i >= 0x1f) && (i <= 0x29)) || 323 ((i >= 0x30) && (i <= 0x37))) 324 continue; 325 if (IS_G200_SE(mdev) && 326 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) 327 continue; 328 if ((mdev->type == G200_EV || 329 mdev->type == G200_WB || 330 mdev->type == G200_EH || 331 mdev->type == G200_EW3 || 332 mdev->type == G200_EH3) && 333 (i >= 0x44) && (i <= 0x4e)) 334 continue; 335 336 WREG_DAC(i, dacvalue[i]); 337 } 338 339 if (mdev->type == G200_ER) 340 WREG_DAC(0x90, 0); 341 } 342 343 static void mgag200_init_regs(struct mga_device *mdev) 344 { 345 u8 crtc11, misc; 346 347 mgag200_set_dac_regs(mdev); 348 349 WREG_SEQ(2, 0x0f); 350 WREG_SEQ(3, 0x00); 351 WREG_SEQ(4, 0x0e); 352 353 WREG_CRT(10, 0); 354 WREG_CRT(11, 0); 355 WREG_CRT(12, 0); 356 WREG_CRT(13, 0); 357 WREG_CRT(14, 0); 358 WREG_CRT(15, 0); 359 360 RREG_CRT(0x11, crtc11); 361 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | 362 MGAREG_CRTC11_VINTEN | 363 MGAREG_CRTC11_VINTCLR); 364 WREG_CRT(0x11, crtc11); 365 366 if (mdev->type == G200_ER) 367 WREG_ECRT(0x24, 0x5); 368 369 if (mdev->type == G200_EW3) 370 WREG_ECRT(0x34, 0x5); 371 372 misc = RREG8(MGA_MISC_IN); 373 misc |= MGAREG_MISC_IOADSEL; 374 WREG8(MGA_MISC_OUT, misc); 375 } 376 377 static void mgag200_set_mode_regs(struct mga_device *mdev, 378 const struct drm_display_mode *mode) 379 { 380 unsigned int hdisplay, hsyncstart, hsyncend, htotal; 381 unsigned int vdisplay, vsyncstart, vsyncend, vtotal; 382 u8 misc, crtcext1, crtcext2, crtcext5; 383 384 hdisplay = mode->hdisplay / 8 - 1; 385 hsyncstart = mode->hsync_start / 8 - 1; 386 hsyncend = mode->hsync_end / 8 - 1; 387 htotal = mode->htotal / 8 - 1; 388 389 /* Work around hardware quirk */ 390 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 391 htotal++; 392 393 vdisplay = mode->vdisplay - 1; 394 vsyncstart = mode->vsync_start - 1; 395 vsyncend = mode->vsync_end - 1; 396 vtotal = mode->vtotal - 2; 397 398 misc = RREG8(MGA_MISC_IN); 399 400 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 401 misc |= MGAREG_MISC_HSYNCPOL; 402 else 403 misc &= ~MGAREG_MISC_HSYNCPOL; 404 405 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 406 misc |= MGAREG_MISC_VSYNCPOL; 407 else 408 misc &= ~MGAREG_MISC_VSYNCPOL; 409 410 crtcext1 = (((htotal - 4) & 0x100) >> 8) | 411 ((hdisplay & 0x100) >> 7) | 412 ((hsyncstart & 0x100) >> 6) | 413 (htotal & 0x40); 414 if (mdev->type == G200_WB || mdev->type == G200_EW3) 415 crtcext1 |= BIT(7) | /* vrsten */ 416 BIT(3); /* hrsten */ 417 418 crtcext2 = ((vtotal & 0xc00) >> 10) | 419 ((vdisplay & 0x400) >> 8) | 420 ((vdisplay & 0xc00) >> 7) | 421 ((vsyncstart & 0xc00) >> 5) | 422 ((vdisplay & 0x400) >> 3); 423 crtcext5 = 0x00; 424 425 WREG_CRT(0, htotal - 4); 426 WREG_CRT(1, hdisplay); 427 WREG_CRT(2, hdisplay); 428 WREG_CRT(3, (htotal & 0x1F) | 0x80); 429 WREG_CRT(4, hsyncstart); 430 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 431 WREG_CRT(6, vtotal & 0xFF); 432 WREG_CRT(7, ((vtotal & 0x100) >> 8) | 433 ((vdisplay & 0x100) >> 7) | 434 ((vsyncstart & 0x100) >> 6) | 435 ((vdisplay & 0x100) >> 5) | 436 ((vdisplay & 0x100) >> 4) | /* linecomp */ 437 ((vtotal & 0x200) >> 4) | 438 ((vdisplay & 0x200) >> 3) | 439 ((vsyncstart & 0x200) >> 2)); 440 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 441 ((vdisplay & 0x200) >> 3)); 442 WREG_CRT(16, vsyncstart & 0xFF); 443 WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 444 WREG_CRT(18, vdisplay & 0xFF); 445 WREG_CRT(20, 0); 446 WREG_CRT(21, vdisplay & 0xFF); 447 WREG_CRT(22, (vtotal + 1) & 0xFF); 448 WREG_CRT(23, 0xc3); 449 WREG_CRT(24, vdisplay & 0xFF); 450 451 WREG_ECRT(0x01, crtcext1); 452 WREG_ECRT(0x02, crtcext2); 453 WREG_ECRT(0x05, crtcext5); 454 455 WREG8(MGA_MISC_OUT, misc); 456 } 457 458 static u8 mgag200_get_bpp_shift(const struct drm_format_info *format) 459 { 460 static const u8 bpp_shift[] = {0, 1, 0, 2}; 461 462 return bpp_shift[format->cpp[0] - 1]; 463 } 464 465 /* 466 * Calculates the HW offset value from the framebuffer's pitch. The 467 * offset is a multiple of the pixel size and depends on the display 468 * format. 469 */ 470 static u32 mgag200_calculate_offset(struct mga_device *mdev, 471 const struct drm_framebuffer *fb) 472 { 473 u32 offset = fb->pitches[0] / fb->format->cpp[0]; 474 u8 bppshift = mgag200_get_bpp_shift(fb->format); 475 476 if (fb->format->cpp[0] * 8 == 24) 477 offset = (offset * 3) >> (4 - bppshift); 478 else 479 offset = offset >> (4 - bppshift); 480 481 return offset; 482 } 483 484 static void mgag200_set_offset(struct mga_device *mdev, 485 const struct drm_framebuffer *fb) 486 { 487 u8 crtc13, crtcext0; 488 u32 offset = mgag200_calculate_offset(mdev, fb); 489 490 RREG_ECRT(0, crtcext0); 491 492 crtc13 = offset & 0xff; 493 494 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK; 495 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK; 496 497 WREG_CRT(0x13, crtc13); 498 WREG_ECRT(0x00, crtcext0); 499 } 500 501 static void mgag200_set_format_regs(struct mga_device *mdev, 502 const struct drm_framebuffer *fb) 503 { 504 struct drm_device *dev = &mdev->base; 505 const struct drm_format_info *format = fb->format; 506 unsigned int bpp, bppshift, scale; 507 u8 crtcext3, xmulctrl; 508 509 bpp = format->cpp[0] * 8; 510 511 bppshift = mgag200_get_bpp_shift(format); 512 switch (bpp) { 513 case 24: 514 scale = ((1 << bppshift) * 3) - 1; 515 break; 516 default: 517 scale = (1 << bppshift) - 1; 518 break; 519 } 520 521 RREG_ECRT(3, crtcext3); 522 523 switch (bpp) { 524 case 8: 525 xmulctrl = MGA1064_MUL_CTL_8bits; 526 break; 527 case 16: 528 if (format->depth == 15) 529 xmulctrl = MGA1064_MUL_CTL_15bits; 530 else 531 xmulctrl = MGA1064_MUL_CTL_16bits; 532 break; 533 case 24: 534 xmulctrl = MGA1064_MUL_CTL_24bits; 535 break; 536 case 32: 537 xmulctrl = MGA1064_MUL_CTL_32_24bits; 538 break; 539 default: 540 /* BUG: We should have caught this problem already. */ 541 drm_WARN_ON(dev, "invalid format depth\n"); 542 return; 543 } 544 545 crtcext3 &= ~GENMASK(2, 0); 546 crtcext3 |= scale; 547 548 WREG_DAC(MGA1064_MUL_CTL, xmulctrl); 549 550 WREG_GFX(0, 0x00); 551 WREG_GFX(1, 0x00); 552 WREG_GFX(2, 0x00); 553 WREG_GFX(3, 0x00); 554 WREG_GFX(4, 0x00); 555 WREG_GFX(5, 0x40); 556 /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode), 557 * so that it doesn't hang when running kexec/kdump on G200_SE rev42. 558 */ 559 WREG_GFX(6, 0x0d); 560 WREG_GFX(7, 0x0f); 561 WREG_GFX(8, 0x0f); 562 563 WREG_ECRT(3, crtcext3); 564 } 565 566 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev) 567 { 568 static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */ 569 u32 memctl; 570 571 memctl = RREG32(MGAREG_MEMCTL); 572 573 memctl |= RESET_FLAG; 574 WREG32(MGAREG_MEMCTL, memctl); 575 576 udelay(1000); 577 578 memctl &= ~RESET_FLAG; 579 WREG32(MGAREG_MEMCTL, memctl); 580 } 581 582 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev, 583 const struct drm_display_mode *mode, 584 const struct drm_framebuffer *fb) 585 { 586 u32 unique_rev_id = mdev->model.g200se.unique_rev_id; 587 unsigned int hiprilvl; 588 u8 crtcext6; 589 590 if (unique_rev_id >= 0x04) { 591 hiprilvl = 0; 592 } else if (unique_rev_id >= 0x02) { 593 unsigned int bpp; 594 unsigned long mb; 595 596 if (fb->format->cpp[0] * 8 > 16) 597 bpp = 32; 598 else if (fb->format->cpp[0] * 8 > 8) 599 bpp = 16; 600 else 601 bpp = 8; 602 603 mb = (mode->clock * bpp) / 1000; 604 if (mb > 3100) 605 hiprilvl = 0; 606 else if (mb > 2600) 607 hiprilvl = 1; 608 else if (mb > 1900) 609 hiprilvl = 2; 610 else if (mb > 1160) 611 hiprilvl = 3; 612 else if (mb > 440) 613 hiprilvl = 4; 614 else 615 hiprilvl = 5; 616 617 } else if (unique_rev_id >= 0x01) { 618 hiprilvl = 3; 619 } else { 620 hiprilvl = 4; 621 } 622 623 crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */ 624 625 WREG_ECRT(0x06, crtcext6); 626 } 627 628 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev) 629 { 630 WREG_ECRT(0x06, 0x00); 631 } 632 633 static void mgag200_enable_display(struct mga_device *mdev) 634 { 635 u8 seq0, seq1, crtcext1; 636 637 RREG_SEQ(0x00, seq0); 638 seq0 |= MGAREG_SEQ0_SYNCRST | 639 MGAREG_SEQ0_ASYNCRST; 640 WREG_SEQ(0x00, seq0); 641 642 /* 643 * TODO: replace busy waiting with vblank IRQ; put 644 * msleep(50) before changing SCROFF 645 */ 646 mga_wait_vsync(mdev); 647 mga_wait_busy(mdev); 648 649 RREG_SEQ(0x01, seq1); 650 seq1 &= ~MGAREG_SEQ1_SCROFF; 651 WREG_SEQ(0x01, seq1); 652 653 msleep(20); 654 655 RREG_ECRT(0x01, crtcext1); 656 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF; 657 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF; 658 WREG_ECRT(0x01, crtcext1); 659 } 660 661 static void mgag200_disable_display(struct mga_device *mdev) 662 { 663 u8 seq0, seq1, crtcext1; 664 665 RREG_SEQ(0x00, seq0); 666 seq0 &= ~MGAREG_SEQ0_SYNCRST; 667 WREG_SEQ(0x00, seq0); 668 669 /* 670 * TODO: replace busy waiting with vblank IRQ; put 671 * msleep(50) before changing SCROFF 672 */ 673 mga_wait_vsync(mdev); 674 mga_wait_busy(mdev); 675 676 RREG_SEQ(0x01, seq1); 677 seq1 |= MGAREG_SEQ1_SCROFF; 678 WREG_SEQ(0x01, seq1); 679 680 msleep(20); 681 682 RREG_ECRT(0x01, crtcext1); 683 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF | 684 MGAREG_CRTCEXT1_HSYNCOFF; 685 WREG_ECRT(0x01, crtcext1); 686 } 687 688 /* 689 * Connector 690 */ 691 692 static int mgag200_vga_connector_helper_get_modes(struct drm_connector *connector) 693 { 694 struct mga_device *mdev = to_mga_device(connector->dev); 695 int ret; 696 697 /* 698 * Protect access to I/O registers from concurrent modesetting 699 * by acquiring the I/O-register lock. 700 */ 701 mutex_lock(&mdev->rmmio_lock); 702 ret = drm_connector_helper_get_modes_from_ddc(connector); 703 mutex_unlock(&mdev->rmmio_lock); 704 705 return ret; 706 } 707 708 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { 709 .get_modes = mgag200_vga_connector_helper_get_modes, 710 }; 711 712 static const struct drm_connector_funcs mga_vga_connector_funcs = { 713 .reset = drm_atomic_helper_connector_reset, 714 .fill_modes = drm_helper_probe_single_connector_modes, 715 .destroy = drm_connector_cleanup, 716 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 717 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 718 }; 719 720 /* 721 * Simple Display Pipe 722 */ 723 724 static enum drm_mode_status 725 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 726 const struct drm_display_mode *mode) 727 { 728 struct mga_device *mdev = to_mga_device(pipe->crtc.dev); 729 730 if (IS_G200_SE(mdev)) { 731 u32 unique_rev_id = mdev->model.g200se.unique_rev_id; 732 733 if (unique_rev_id == 0x01) { 734 if (mode->hdisplay > 1600) 735 return MODE_VIRTUAL_X; 736 if (mode->vdisplay > 1200) 737 return MODE_VIRTUAL_Y; 738 } else if (unique_rev_id == 0x02) { 739 if (mode->hdisplay > 1920) 740 return MODE_VIRTUAL_X; 741 if (mode->vdisplay > 1200) 742 return MODE_VIRTUAL_Y; 743 } 744 } else if (mdev->type == G200_WB) { 745 if (mode->hdisplay > 1280) 746 return MODE_VIRTUAL_X; 747 if (mode->vdisplay > 1024) 748 return MODE_VIRTUAL_Y; 749 } 750 751 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 752 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 753 return MODE_H_ILLEGAL; 754 } 755 756 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 757 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 758 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 759 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 760 return MODE_BAD; 761 } 762 763 return MODE_OK; 764 } 765 766 static void 767 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb, 768 struct drm_rect *clip, const struct iosys_map *map) 769 { 770 void __iomem *dst = mdev->vram; 771 void *vmap = map->vaddr; /* TODO: Use mapping abstraction properly */ 772 773 dst += drm_fb_clip_offset(fb->pitches[0], fb->format, clip); 774 drm_fb_memcpy_toio(dst, fb->pitches[0], vmap, fb, clip); 775 } 776 777 static void 778 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe, 779 struct drm_crtc_state *crtc_state, 780 struct drm_plane_state *plane_state) 781 { 782 struct drm_crtc *crtc = &pipe->crtc; 783 struct drm_device *dev = crtc->dev; 784 struct mga_device *mdev = to_mga_device(dev); 785 struct mgag200_pll *pixpll = &mdev->pixpll; 786 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 787 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 788 struct drm_framebuffer *fb = plane_state->fb; 789 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 790 struct drm_rect fullscreen = { 791 .x1 = 0, 792 .x2 = fb->width, 793 .y1 = 0, 794 .y2 = fb->height, 795 }; 796 797 /* 798 * Concurrent operations could possibly trigger a call to 799 * drm_connector_helper_funcs.get_modes by trying to read the 800 * display modes. Protect access to I/O registers by acquiring 801 * the I/O-register lock. 802 */ 803 mutex_lock(&mdev->rmmio_lock); 804 805 if (mdev->type == G200_WB || mdev->type == G200_EW3) 806 mgag200_g200wb_hold_bmc(mdev); 807 808 mgag200_set_format_regs(mdev, fb); 809 mgag200_set_mode_regs(mdev, adjusted_mode); 810 811 pixpll->funcs->update(pixpll, &mgag200_crtc_state->pixpllc); 812 813 if (mdev->type == G200_ER) 814 mgag200_g200er_reset_tagfifo(mdev); 815 816 if (IS_G200_SE(mdev)) 817 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb); 818 else if (mdev->type == G200_EV) 819 mgag200_g200ev_set_hiprilvl(mdev); 820 821 if (mdev->type == G200_WB || mdev->type == G200_EW3) 822 mgag200_g200wb_release_bmc(mdev); 823 824 if (crtc_state->gamma_lut) 825 mgag200_crtc_set_gamma(mdev, fb->format, crtc_state->gamma_lut->data); 826 else 827 mgag200_crtc_set_gamma_linear(mdev, fb->format); 828 829 mgag200_enable_display(mdev); 830 831 mgag200_handle_damage(mdev, fb, &fullscreen, &shadow_plane_state->data[0]); 832 833 /* Always scanout image at VRAM offset 0 */ 834 mgag200_set_startadd(mdev, (u32)0); 835 mgag200_set_offset(mdev, fb); 836 837 mutex_unlock(&mdev->rmmio_lock); 838 } 839 840 static void 841 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe) 842 { 843 struct drm_crtc *crtc = &pipe->crtc; 844 struct mga_device *mdev = to_mga_device(crtc->dev); 845 846 mgag200_disable_display(mdev); 847 } 848 849 static int 850 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe, 851 struct drm_plane_state *plane_state, 852 struct drm_crtc_state *crtc_state) 853 { 854 struct drm_plane *plane = plane_state->plane; 855 struct drm_device *dev = plane->dev; 856 struct mga_device *mdev = to_mga_device(dev); 857 struct mgag200_pll *pixpll = &mdev->pixpll; 858 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 859 struct drm_framebuffer *new_fb = plane_state->fb; 860 struct drm_framebuffer *fb = NULL; 861 int ret; 862 863 if (!new_fb) 864 return 0; 865 866 if (plane->state) 867 fb = plane->state->fb; 868 869 if (!fb || (fb->format != new_fb->format)) 870 crtc_state->mode_changed = true; /* update PLL settings */ 871 872 if (crtc_state->mode_changed) { 873 ret = pixpll->funcs->compute(pixpll, crtc_state->mode.clock, 874 &mgag200_crtc_state->pixpllc); 875 if (ret) 876 return ret; 877 } 878 879 if (crtc_state->color_mgmt_changed && crtc_state->gamma_lut) { 880 if (crtc_state->gamma_lut->length != 881 MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) { 882 drm_err(dev, "Wrong size for gamma_lut %zu\n", 883 crtc_state->gamma_lut->length); 884 return -EINVAL; 885 } 886 } 887 return 0; 888 } 889 890 static void 891 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe, 892 struct drm_plane_state *old_state) 893 { 894 struct drm_plane *plane = &pipe->plane; 895 struct drm_crtc *crtc = &pipe->crtc; 896 struct drm_device *dev = plane->dev; 897 struct mga_device *mdev = to_mga_device(dev); 898 struct drm_plane_state *state = plane->state; 899 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state); 900 struct drm_framebuffer *fb = state->fb; 901 struct drm_rect damage; 902 struct drm_atomic_helper_damage_iter iter; 903 904 if (!fb) 905 return; 906 907 mutex_lock(&mdev->rmmio_lock); 908 909 if (crtc->state->color_mgmt_changed && crtc->state->gamma_lut) 910 mgag200_crtc_set_gamma(mdev, fb->format, crtc->state->gamma_lut->data); 911 912 drm_atomic_helper_damage_iter_init(&iter, old_state, state); 913 drm_atomic_for_each_plane_damage(&iter, &damage) { 914 mgag200_handle_damage(mdev, fb, &damage, &shadow_plane_state->data[0]); 915 } 916 /* Always scanout image at VRAM offset 0 */ 917 mgag200_set_startadd(mdev, (u32)0); 918 mgag200_set_offset(mdev, fb); 919 920 mutex_unlock(&mdev->rmmio_lock); 921 } 922 923 static struct drm_crtc_state * 924 mgag200_simple_display_pipe_duplicate_crtc_state(struct drm_simple_display_pipe *pipe) 925 { 926 struct drm_crtc *crtc = &pipe->crtc; 927 struct drm_crtc_state *crtc_state = crtc->state; 928 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 929 struct mgag200_crtc_state *new_mgag200_crtc_state; 930 931 if (!crtc_state) 932 return NULL; 933 934 new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL); 935 if (!new_mgag200_crtc_state) 936 return NULL; 937 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base); 938 939 memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc, 940 sizeof(new_mgag200_crtc_state->pixpllc)); 941 942 return &new_mgag200_crtc_state->base; 943 } 944 945 static void mgag200_simple_display_pipe_destroy_crtc_state(struct drm_simple_display_pipe *pipe, 946 struct drm_crtc_state *crtc_state) 947 { 948 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 949 950 __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base); 951 kfree(mgag200_crtc_state); 952 } 953 954 static void mgag200_simple_display_pipe_reset_crtc(struct drm_simple_display_pipe *pipe) 955 { 956 struct drm_crtc *crtc = &pipe->crtc; 957 struct mgag200_crtc_state *mgag200_crtc_state; 958 959 if (crtc->state) { 960 mgag200_simple_display_pipe_destroy_crtc_state(pipe, crtc->state); 961 crtc->state = NULL; /* must be set to NULL here */ 962 } 963 964 mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL); 965 if (!mgag200_crtc_state) 966 return; 967 __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base); 968 } 969 970 static const struct drm_simple_display_pipe_funcs 971 mgag200_simple_display_pipe_funcs = { 972 .mode_valid = mgag200_simple_display_pipe_mode_valid, 973 .enable = mgag200_simple_display_pipe_enable, 974 .disable = mgag200_simple_display_pipe_disable, 975 .check = mgag200_simple_display_pipe_check, 976 .update = mgag200_simple_display_pipe_update, 977 .reset_crtc = mgag200_simple_display_pipe_reset_crtc, 978 .duplicate_crtc_state = mgag200_simple_display_pipe_duplicate_crtc_state, 979 .destroy_crtc_state = mgag200_simple_display_pipe_destroy_crtc_state, 980 DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS, 981 }; 982 983 static const uint32_t mgag200_simple_display_pipe_formats[] = { 984 DRM_FORMAT_XRGB8888, 985 DRM_FORMAT_RGB565, 986 DRM_FORMAT_RGB888, 987 }; 988 989 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = { 990 DRM_FORMAT_MOD_LINEAR, 991 DRM_FORMAT_MOD_INVALID 992 }; 993 994 /* 995 * Mode config 996 */ 997 998 /* Calculates a mode's required memory bandwidth (in KiB/sec). */ 999 static uint32_t mgag200_calculate_mode_bandwidth(const struct drm_display_mode *mode, 1000 unsigned int bits_per_pixel) 1001 { 1002 uint32_t total_area, divisor; 1003 uint64_t active_area, pixels_per_second, bandwidth; 1004 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 1005 1006 divisor = 1024; 1007 1008 if (!mode->htotal || !mode->vtotal || !mode->clock) 1009 return 0; 1010 1011 active_area = mode->hdisplay * mode->vdisplay; 1012 total_area = mode->htotal * mode->vtotal; 1013 1014 pixels_per_second = active_area * mode->clock * 1000; 1015 do_div(pixels_per_second, total_area); 1016 1017 bandwidth = pixels_per_second * bytes_per_pixel * 100; 1018 do_div(bandwidth, divisor); 1019 1020 return (uint32_t)bandwidth; 1021 } 1022 1023 static enum drm_mode_status mgag200_mode_config_mode_valid(struct drm_device *dev, 1024 const struct drm_display_mode *mode) 1025 { 1026 static const unsigned int max_bpp = 4; // DRM_FORMAT_XRGB8888 1027 struct mga_device *mdev = to_mga_device(dev); 1028 unsigned long fbsize, fbpages, max_fbpages; 1029 1030 max_fbpages = mdev->vram_fb_available >> PAGE_SHIFT; 1031 1032 fbsize = mode->hdisplay * mode->vdisplay * max_bpp; 1033 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); 1034 1035 if (fbpages > max_fbpages) 1036 return MODE_MEM; 1037 1038 if (IS_G200_SE(mdev)) { 1039 u32 unique_rev_id = mdev->model.g200se.unique_rev_id; 1040 1041 if (unique_rev_id == 0x01) { 1042 if (mgag200_calculate_mode_bandwidth(mode, max_bpp * 8) > (24400 * 1024)) 1043 return MODE_BAD; 1044 } else if (unique_rev_id == 0x02) { 1045 if (mgag200_calculate_mode_bandwidth(mode, max_bpp * 8) > (30100 * 1024)) 1046 return MODE_BAD; 1047 } else { 1048 if (mgag200_calculate_mode_bandwidth(mode, max_bpp * 8) > (55000 * 1024)) 1049 return MODE_BAD; 1050 } 1051 } else if (mdev->type == G200_WB) { 1052 if (mgag200_calculate_mode_bandwidth(mode, max_bpp * 8) > (31877 * 1024)) 1053 return MODE_BAD; 1054 } else if (mdev->type == G200_EV) { 1055 if (mgag200_calculate_mode_bandwidth(mode, max_bpp * 8) > (32700 * 1024)) 1056 return MODE_BAD; 1057 } else if (mdev->type == G200_EH) { 1058 if (mgag200_calculate_mode_bandwidth(mode, max_bpp * 8) > (37500 * 1024)) 1059 return MODE_BAD; 1060 } else if (mdev->type == G200_ER) { 1061 if (mgag200_calculate_mode_bandwidth(mode, max_bpp * 8) > (55000 * 1024)) 1062 return MODE_BAD; 1063 } 1064 1065 return MODE_OK; 1066 } 1067 1068 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = { 1069 .fb_create = drm_gem_fb_create_with_dirty, 1070 .mode_valid = mgag200_mode_config_mode_valid, 1071 .atomic_check = drm_atomic_helper_check, 1072 .atomic_commit = drm_atomic_helper_commit, 1073 }; 1074 1075 static unsigned int mgag200_preferred_depth(struct mga_device *mdev) 1076 { 1077 if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024)) 1078 return 16; 1079 else 1080 return 32; 1081 } 1082 1083 int mgag200_modeset_init(struct mga_device *mdev) 1084 { 1085 struct drm_device *dev = &mdev->base; 1086 struct mga_i2c_chan *i2c = &mdev->i2c; 1087 struct drm_connector *connector = &mdev->connector; 1088 struct drm_simple_display_pipe *pipe = &mdev->display_pipe; 1089 size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats); 1090 int ret; 1091 1092 mgag200_init_regs(mdev); 1093 1094 ret = drmm_mode_config_init(dev); 1095 if (ret) { 1096 drm_err(dev, "drmm_mode_config_init() failed, error %d\n", 1097 ret); 1098 return ret; 1099 } 1100 1101 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 1102 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 1103 1104 dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev); 1105 1106 dev->mode_config.fb_base = mdev->mc.vram_base; 1107 1108 dev->mode_config.funcs = &mgag200_mode_config_funcs; 1109 1110 ret = mgag200_i2c_init(mdev, i2c); 1111 if (ret) { 1112 drm_err(dev, "failed to add DDC bus: %d\n", ret); 1113 return ret; 1114 } 1115 1116 ret = drm_connector_init_with_ddc(dev, connector, 1117 &mga_vga_connector_funcs, 1118 DRM_MODE_CONNECTOR_VGA, 1119 &i2c->adapter); 1120 if (ret) { 1121 drm_err(dev, "drm_connector_init_with_ddc() failed: %d\n", ret); 1122 return ret; 1123 } 1124 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); 1125 1126 ret = mgag200_pixpll_init(&mdev->pixpll, mdev); 1127 if (ret) 1128 return ret; 1129 1130 ret = drm_simple_display_pipe_init(dev, pipe, 1131 &mgag200_simple_display_pipe_funcs, 1132 mgag200_simple_display_pipe_formats, 1133 format_count, 1134 mgag200_simple_display_pipe_fmtmods, 1135 connector); 1136 if (ret) { 1137 drm_err(dev, 1138 "drm_simple_display_pipe_init() failed, error %d\n", 1139 ret); 1140 return ret; 1141 } 1142 1143 drm_plane_enable_fb_damage_clips(&pipe->plane); 1144 1145 /* FIXME: legacy gamma tables, but atomic gamma doesn't work without */ 1146 drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE); 1147 1148 drm_crtc_enable_color_mgmt(&pipe->crtc, 0, false, MGAG200_LUT_SIZE); 1149 1150 drm_mode_config_reset(dev); 1151 1152 return 0; 1153 } 1154