1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/iosys-map.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_atomic_state_helper.h> 16 #include <drm/drm_crtc_helper.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_format_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_framebuffer.h> 21 #include <drm/drm_gem_atomic_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_plane_helper.h> 24 #include <drm/drm_print.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_simple_kms_helper.h> 27 28 #include "mgag200_drv.h" 29 30 #define MGAG200_LUT_SIZE 256 31 32 /* 33 * This file contains setup code for the CRTC. 34 */ 35 36 static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, 37 const struct drm_format_info *format) 38 { 39 int i; 40 41 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 42 43 switch (format->format) { 44 case DRM_FORMAT_RGB565: 45 /* Use better interpolation, to take 32 values from 0 to 255 */ 46 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 47 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 48 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 49 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 50 } 51 /* Green has one more bit, so add padding with 0 for red and blue. */ 52 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 53 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 54 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 55 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 56 } 57 break; 58 case DRM_FORMAT_RGB888: 59 case DRM_FORMAT_XRGB8888: 60 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 61 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 62 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 63 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 64 } 65 break; 66 default: 67 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 68 &format->format); 69 break; 70 } 71 } 72 73 static void mgag200_crtc_set_gamma(struct mga_device *mdev, 74 const struct drm_format_info *format, 75 struct drm_color_lut *lut) 76 { 77 int i; 78 79 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 80 81 switch (format->format) { 82 case DRM_FORMAT_RGB565: 83 /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ 84 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 85 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].red >> 8); 86 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 87 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].blue >> 8); 88 } 89 /* Green has one more bit, so add padding with 0 for red and blue. */ 90 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 91 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 92 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 93 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 94 } 95 break; 96 case DRM_FORMAT_RGB888: 97 case DRM_FORMAT_XRGB8888: 98 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 99 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].red >> 8); 100 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].green >> 8); 101 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].blue >> 8); 102 } 103 break; 104 default: 105 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 106 &format->format); 107 break; 108 } 109 } 110 111 static inline void mga_wait_vsync(struct mga_device *mdev) 112 { 113 unsigned long timeout = jiffies + HZ/10; 114 unsigned int status = 0; 115 116 do { 117 status = RREG32(MGAREG_Status); 118 } while ((status & 0x08) && time_before(jiffies, timeout)); 119 timeout = jiffies + HZ/10; 120 status = 0; 121 do { 122 status = RREG32(MGAREG_Status); 123 } while (!(status & 0x08) && time_before(jiffies, timeout)); 124 } 125 126 static inline void mga_wait_busy(struct mga_device *mdev) 127 { 128 unsigned long timeout = jiffies + HZ; 129 unsigned int status = 0; 130 do { 131 status = RREG8(MGAREG_Status + 2); 132 } while ((status & 0x01) && time_before(jiffies, timeout)); 133 } 134 135 static void mgag200_g200wb_hold_bmc(struct mga_device *mdev) 136 { 137 u8 tmp; 138 int iter_max; 139 140 /* 1- The first step is to warn the BMC of an upcoming mode change. 141 * We are putting the misc<0> to output.*/ 142 143 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); 144 tmp = RREG8(DAC_DATA); 145 tmp |= 0x10; 146 WREG_DAC(MGA1064_GEN_IO_CTL, tmp); 147 148 /* we are putting a 1 on the misc<0> line */ 149 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 150 tmp = RREG8(DAC_DATA); 151 tmp |= 0x10; 152 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 153 154 /* 2- Second step to mask and further scan request 155 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) 156 */ 157 WREG8(DAC_INDEX, MGA1064_SPAREREG); 158 tmp = RREG8(DAC_DATA); 159 tmp |= 0x80; 160 WREG_DAC(MGA1064_SPAREREG, tmp); 161 162 /* 3a- the third step is to verifu if there is an active scan 163 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) 164 */ 165 iter_max = 300; 166 while (!(tmp & 0x1) && iter_max) { 167 WREG8(DAC_INDEX, MGA1064_SPAREREG); 168 tmp = RREG8(DAC_DATA); 169 udelay(1000); 170 iter_max--; 171 } 172 173 /* 3b- this step occurs only if the remove is actually scanning 174 * we are waiting for the end of the frame which is a 1 on 175 * remvsyncsts (XSPAREREG<1>) 176 */ 177 if (iter_max) { 178 iter_max = 300; 179 while ((tmp & 0x2) && iter_max) { 180 WREG8(DAC_INDEX, MGA1064_SPAREREG); 181 tmp = RREG8(DAC_DATA); 182 udelay(1000); 183 iter_max--; 184 } 185 } 186 } 187 188 static void mgag200_g200wb_release_bmc(struct mga_device *mdev) 189 { 190 u8 tmp; 191 192 /* 1- The first step is to ensure that the vrsten and hrsten are set */ 193 WREG8(MGAREG_CRTCEXT_INDEX, 1); 194 tmp = RREG8(MGAREG_CRTCEXT_DATA); 195 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); 196 197 /* 2- second step is to assert the rstlvl2 */ 198 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 199 tmp = RREG8(DAC_DATA); 200 tmp |= 0x8; 201 WREG8(DAC_DATA, tmp); 202 203 /* wait 10 us */ 204 udelay(10); 205 206 /* 3- deassert rstlvl2 */ 207 tmp &= ~0x08; 208 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 209 WREG8(DAC_DATA, tmp); 210 211 /* 4- remove mask of scan request */ 212 WREG8(DAC_INDEX, MGA1064_SPAREREG); 213 tmp = RREG8(DAC_DATA); 214 tmp &= ~0x80; 215 WREG8(DAC_DATA, tmp); 216 217 /* 5- put back a 0 on the misc<0> line */ 218 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 219 tmp = RREG8(DAC_DATA); 220 tmp &= ~0x10; 221 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 222 } 223 224 /* 225 * This is how the framebuffer base address is stored in g200 cards: 226 * * Assume @offset is the gpu_addr variable of the framebuffer object 227 * * Then addr is the number of _pixels_ (not bytes) from the start of 228 * VRAM to the first pixel we want to display. (divided by 2 for 32bit 229 * framebuffers) 230 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 231 * addr<20> -> CRTCEXT0<6> 232 * addr<19-16> -> CRTCEXT0<3-0> 233 * addr<15-8> -> CRTCC<7-0> 234 * addr<7-0> -> CRTCD<7-0> 235 * 236 * CRTCEXT0 has to be programmed last to trigger an update and make the 237 * new addr variable take effect. 238 */ 239 static void mgag200_set_startadd(struct mga_device *mdev, 240 unsigned long offset) 241 { 242 struct drm_device *dev = &mdev->base; 243 u32 startadd; 244 u8 crtcc, crtcd, crtcext0; 245 246 startadd = offset / 8; 247 248 if (startadd > 0) 249 drm_WARN_ON_ONCE(dev, mdev->info->bug_no_startadd); 250 251 /* 252 * Can't store addresses any higher than that, but we also 253 * don't have more than 16 MiB of memory, so it should be fine. 254 */ 255 drm_WARN_ON(dev, startadd > 0x1fffff); 256 257 RREG_ECRT(0x00, crtcext0); 258 259 crtcc = (startadd >> 8) & 0xff; 260 crtcd = startadd & 0xff; 261 crtcext0 &= 0xb0; 262 crtcext0 |= ((startadd >> 14) & BIT(6)) | 263 ((startadd >> 16) & 0x0f); 264 265 WREG_CRT(0x0c, crtcc); 266 WREG_CRT(0x0d, crtcd); 267 WREG_ECRT(0x00, crtcext0); 268 } 269 270 static void mgag200_set_dac_regs(struct mga_device *mdev) 271 { 272 size_t i; 273 u8 dacvalue[] = { 274 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, 275 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, 276 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, 277 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, 278 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 279 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, 280 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, 281 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, 282 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, 283 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 284 }; 285 286 switch (mdev->type) { 287 case G200_PCI: 288 case G200_AGP: 289 dacvalue[MGA1064_SYS_PLL_M] = 0x04; 290 dacvalue[MGA1064_SYS_PLL_N] = 0x2D; 291 dacvalue[MGA1064_SYS_PLL_P] = 0x19; 292 break; 293 case G200_SE_A: 294 case G200_SE_B: 295 dacvalue[MGA1064_VREF_CTL] = 0x03; 296 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 297 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | 298 MGA1064_MISC_CTL_VGA8 | 299 MGA1064_MISC_CTL_DAC_RAM_CS; 300 break; 301 case G200_WB: 302 case G200_EW3: 303 dacvalue[MGA1064_VREF_CTL] = 0x07; 304 break; 305 case G200_EV: 306 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 307 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 308 MGA1064_MISC_CTL_DAC_RAM_CS; 309 break; 310 case G200_EH: 311 case G200_EH3: 312 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 313 MGA1064_MISC_CTL_DAC_RAM_CS; 314 break; 315 case G200_ER: 316 break; 317 } 318 319 for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { 320 if ((i <= 0x17) || 321 (i == 0x1b) || 322 (i == 0x1c) || 323 ((i >= 0x1f) && (i <= 0x29)) || 324 ((i >= 0x30) && (i <= 0x37))) 325 continue; 326 if (IS_G200_SE(mdev) && 327 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) 328 continue; 329 if ((mdev->type == G200_EV || 330 mdev->type == G200_WB || 331 mdev->type == G200_EH || 332 mdev->type == G200_EW3 || 333 mdev->type == G200_EH3) && 334 (i >= 0x44) && (i <= 0x4e)) 335 continue; 336 337 WREG_DAC(i, dacvalue[i]); 338 } 339 340 if (mdev->type == G200_ER) 341 WREG_DAC(0x90, 0); 342 } 343 344 static void mgag200_init_regs(struct mga_device *mdev) 345 { 346 u8 crtc11, misc; 347 348 mgag200_set_dac_regs(mdev); 349 350 WREG_SEQ(2, 0x0f); 351 WREG_SEQ(3, 0x00); 352 WREG_SEQ(4, 0x0e); 353 354 WREG_CRT(10, 0); 355 WREG_CRT(11, 0); 356 WREG_CRT(12, 0); 357 WREG_CRT(13, 0); 358 WREG_CRT(14, 0); 359 WREG_CRT(15, 0); 360 361 RREG_CRT(0x11, crtc11); 362 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | 363 MGAREG_CRTC11_VINTEN | 364 MGAREG_CRTC11_VINTCLR); 365 WREG_CRT(0x11, crtc11); 366 367 if (mdev->type == G200_ER) 368 WREG_ECRT(0x24, 0x5); 369 370 if (mdev->type == G200_EW3) 371 WREG_ECRT(0x34, 0x5); 372 373 misc = RREG8(MGA_MISC_IN); 374 misc |= MGAREG_MISC_IOADSEL; 375 WREG8(MGA_MISC_OUT, misc); 376 } 377 378 static void mgag200_set_mode_regs(struct mga_device *mdev, 379 const struct drm_display_mode *mode) 380 { 381 const struct mgag200_device_info *info = mdev->info; 382 unsigned int hdisplay, hsyncstart, hsyncend, htotal; 383 unsigned int vdisplay, vsyncstart, vsyncend, vtotal; 384 u8 misc, crtcext1, crtcext2, crtcext5; 385 386 hdisplay = mode->hdisplay / 8 - 1; 387 hsyncstart = mode->hsync_start / 8 - 1; 388 hsyncend = mode->hsync_end / 8 - 1; 389 htotal = mode->htotal / 8 - 1; 390 391 /* Work around hardware quirk */ 392 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 393 htotal++; 394 395 vdisplay = mode->vdisplay - 1; 396 vsyncstart = mode->vsync_start - 1; 397 vsyncend = mode->vsync_end - 1; 398 vtotal = mode->vtotal - 2; 399 400 misc = RREG8(MGA_MISC_IN); 401 402 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 403 misc |= MGAREG_MISC_HSYNCPOL; 404 else 405 misc &= ~MGAREG_MISC_HSYNCPOL; 406 407 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 408 misc |= MGAREG_MISC_VSYNCPOL; 409 else 410 misc &= ~MGAREG_MISC_VSYNCPOL; 411 412 crtcext1 = (((htotal - 4) & 0x100) >> 8) | 413 ((hdisplay & 0x100) >> 7) | 414 ((hsyncstart & 0x100) >> 6) | 415 (htotal & 0x40); 416 if (info->has_vidrst) 417 crtcext1 |= MGAREG_CRTCEXT1_VRSTEN | 418 MGAREG_CRTCEXT1_HRSTEN; 419 420 crtcext2 = ((vtotal & 0xc00) >> 10) | 421 ((vdisplay & 0x400) >> 8) | 422 ((vdisplay & 0xc00) >> 7) | 423 ((vsyncstart & 0xc00) >> 5) | 424 ((vdisplay & 0x400) >> 3); 425 crtcext5 = 0x00; 426 427 WREG_CRT(0, htotal - 4); 428 WREG_CRT(1, hdisplay); 429 WREG_CRT(2, hdisplay); 430 WREG_CRT(3, (htotal & 0x1F) | 0x80); 431 WREG_CRT(4, hsyncstart); 432 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 433 WREG_CRT(6, vtotal & 0xFF); 434 WREG_CRT(7, ((vtotal & 0x100) >> 8) | 435 ((vdisplay & 0x100) >> 7) | 436 ((vsyncstart & 0x100) >> 6) | 437 ((vdisplay & 0x100) >> 5) | 438 ((vdisplay & 0x100) >> 4) | /* linecomp */ 439 ((vtotal & 0x200) >> 4) | 440 ((vdisplay & 0x200) >> 3) | 441 ((vsyncstart & 0x200) >> 2)); 442 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 443 ((vdisplay & 0x200) >> 3)); 444 WREG_CRT(16, vsyncstart & 0xFF); 445 WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 446 WREG_CRT(18, vdisplay & 0xFF); 447 WREG_CRT(20, 0); 448 WREG_CRT(21, vdisplay & 0xFF); 449 WREG_CRT(22, (vtotal + 1) & 0xFF); 450 WREG_CRT(23, 0xc3); 451 WREG_CRT(24, vdisplay & 0xFF); 452 453 WREG_ECRT(0x01, crtcext1); 454 WREG_ECRT(0x02, crtcext2); 455 WREG_ECRT(0x05, crtcext5); 456 457 WREG8(MGA_MISC_OUT, misc); 458 } 459 460 static u8 mgag200_get_bpp_shift(const struct drm_format_info *format) 461 { 462 static const u8 bpp_shift[] = {0, 1, 0, 2}; 463 464 return bpp_shift[format->cpp[0] - 1]; 465 } 466 467 /* 468 * Calculates the HW offset value from the framebuffer's pitch. The 469 * offset is a multiple of the pixel size and depends on the display 470 * format. 471 */ 472 static u32 mgag200_calculate_offset(struct mga_device *mdev, 473 const struct drm_framebuffer *fb) 474 { 475 u32 offset = fb->pitches[0] / fb->format->cpp[0]; 476 u8 bppshift = mgag200_get_bpp_shift(fb->format); 477 478 if (fb->format->cpp[0] * 8 == 24) 479 offset = (offset * 3) >> (4 - bppshift); 480 else 481 offset = offset >> (4 - bppshift); 482 483 return offset; 484 } 485 486 static void mgag200_set_offset(struct mga_device *mdev, 487 const struct drm_framebuffer *fb) 488 { 489 u8 crtc13, crtcext0; 490 u32 offset = mgag200_calculate_offset(mdev, fb); 491 492 RREG_ECRT(0, crtcext0); 493 494 crtc13 = offset & 0xff; 495 496 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK; 497 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK; 498 499 WREG_CRT(0x13, crtc13); 500 WREG_ECRT(0x00, crtcext0); 501 } 502 503 static void mgag200_set_format_regs(struct mga_device *mdev, 504 const struct drm_framebuffer *fb) 505 { 506 struct drm_device *dev = &mdev->base; 507 const struct drm_format_info *format = fb->format; 508 unsigned int bpp, bppshift, scale; 509 u8 crtcext3, xmulctrl; 510 511 bpp = format->cpp[0] * 8; 512 513 bppshift = mgag200_get_bpp_shift(format); 514 switch (bpp) { 515 case 24: 516 scale = ((1 << bppshift) * 3) - 1; 517 break; 518 default: 519 scale = (1 << bppshift) - 1; 520 break; 521 } 522 523 RREG_ECRT(3, crtcext3); 524 525 switch (bpp) { 526 case 8: 527 xmulctrl = MGA1064_MUL_CTL_8bits; 528 break; 529 case 16: 530 if (format->depth == 15) 531 xmulctrl = MGA1064_MUL_CTL_15bits; 532 else 533 xmulctrl = MGA1064_MUL_CTL_16bits; 534 break; 535 case 24: 536 xmulctrl = MGA1064_MUL_CTL_24bits; 537 break; 538 case 32: 539 xmulctrl = MGA1064_MUL_CTL_32_24bits; 540 break; 541 default: 542 /* BUG: We should have caught this problem already. */ 543 drm_WARN_ON(dev, "invalid format depth\n"); 544 return; 545 } 546 547 crtcext3 &= ~GENMASK(2, 0); 548 crtcext3 |= scale; 549 550 WREG_DAC(MGA1064_MUL_CTL, xmulctrl); 551 552 WREG_GFX(0, 0x00); 553 WREG_GFX(1, 0x00); 554 WREG_GFX(2, 0x00); 555 WREG_GFX(3, 0x00); 556 WREG_GFX(4, 0x00); 557 WREG_GFX(5, 0x40); 558 /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode), 559 * so that it doesn't hang when running kexec/kdump on G200_SE rev42. 560 */ 561 WREG_GFX(6, 0x0d); 562 WREG_GFX(7, 0x0f); 563 WREG_GFX(8, 0x0f); 564 565 WREG_ECRT(3, crtcext3); 566 } 567 568 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev) 569 { 570 static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */ 571 u32 memctl; 572 573 memctl = RREG32(MGAREG_MEMCTL); 574 575 memctl |= RESET_FLAG; 576 WREG32(MGAREG_MEMCTL, memctl); 577 578 udelay(1000); 579 580 memctl &= ~RESET_FLAG; 581 WREG32(MGAREG_MEMCTL, memctl); 582 } 583 584 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev, 585 const struct drm_display_mode *mode, 586 const struct drm_framebuffer *fb) 587 { 588 struct mgag200_g200se_device *g200se = to_mgag200_g200se_device(&mdev->base); 589 unsigned int hiprilvl; 590 u8 crtcext6; 591 592 if (g200se->unique_rev_id >= 0x04) { 593 hiprilvl = 0; 594 } else if (g200se->unique_rev_id >= 0x02) { 595 unsigned int bpp; 596 unsigned long mb; 597 598 if (fb->format->cpp[0] * 8 > 16) 599 bpp = 32; 600 else if (fb->format->cpp[0] * 8 > 8) 601 bpp = 16; 602 else 603 bpp = 8; 604 605 mb = (mode->clock * bpp) / 1000; 606 if (mb > 3100) 607 hiprilvl = 0; 608 else if (mb > 2600) 609 hiprilvl = 1; 610 else if (mb > 1900) 611 hiprilvl = 2; 612 else if (mb > 1160) 613 hiprilvl = 3; 614 else if (mb > 440) 615 hiprilvl = 4; 616 else 617 hiprilvl = 5; 618 619 } else if (g200se->unique_rev_id >= 0x01) { 620 hiprilvl = 3; 621 } else { 622 hiprilvl = 4; 623 } 624 625 crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */ 626 627 WREG_ECRT(0x06, crtcext6); 628 } 629 630 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev) 631 { 632 WREG_ECRT(0x06, 0x00); 633 } 634 635 static void mgag200_enable_display(struct mga_device *mdev) 636 { 637 u8 seq0, seq1, crtcext1; 638 639 RREG_SEQ(0x00, seq0); 640 seq0 |= MGAREG_SEQ0_SYNCRST | 641 MGAREG_SEQ0_ASYNCRST; 642 WREG_SEQ(0x00, seq0); 643 644 /* 645 * TODO: replace busy waiting with vblank IRQ; put 646 * msleep(50) before changing SCROFF 647 */ 648 mga_wait_vsync(mdev); 649 mga_wait_busy(mdev); 650 651 RREG_SEQ(0x01, seq1); 652 seq1 &= ~MGAREG_SEQ1_SCROFF; 653 WREG_SEQ(0x01, seq1); 654 655 msleep(20); 656 657 RREG_ECRT(0x01, crtcext1); 658 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF; 659 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF; 660 WREG_ECRT(0x01, crtcext1); 661 } 662 663 static void mgag200_disable_display(struct mga_device *mdev) 664 { 665 u8 seq0, seq1, crtcext1; 666 667 RREG_SEQ(0x00, seq0); 668 seq0 &= ~MGAREG_SEQ0_SYNCRST; 669 WREG_SEQ(0x00, seq0); 670 671 /* 672 * TODO: replace busy waiting with vblank IRQ; put 673 * msleep(50) before changing SCROFF 674 */ 675 mga_wait_vsync(mdev); 676 mga_wait_busy(mdev); 677 678 RREG_SEQ(0x01, seq1); 679 seq1 |= MGAREG_SEQ1_SCROFF; 680 WREG_SEQ(0x01, seq1); 681 682 msleep(20); 683 684 RREG_ECRT(0x01, crtcext1); 685 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF | 686 MGAREG_CRTCEXT1_HSYNCOFF; 687 WREG_ECRT(0x01, crtcext1); 688 } 689 690 /* 691 * Connector 692 */ 693 694 static int mgag200_vga_connector_helper_get_modes(struct drm_connector *connector) 695 { 696 struct mga_device *mdev = to_mga_device(connector->dev); 697 int ret; 698 699 /* 700 * Protect access to I/O registers from concurrent modesetting 701 * by acquiring the I/O-register lock. 702 */ 703 mutex_lock(&mdev->rmmio_lock); 704 ret = drm_connector_helper_get_modes_from_ddc(connector); 705 mutex_unlock(&mdev->rmmio_lock); 706 707 return ret; 708 } 709 710 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { 711 .get_modes = mgag200_vga_connector_helper_get_modes, 712 }; 713 714 static const struct drm_connector_funcs mga_vga_connector_funcs = { 715 .reset = drm_atomic_helper_connector_reset, 716 .fill_modes = drm_helper_probe_single_connector_modes, 717 .destroy = drm_connector_cleanup, 718 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 719 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 720 }; 721 722 /* 723 * Simple Display Pipe 724 */ 725 726 static enum drm_mode_status 727 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 728 const struct drm_display_mode *mode) 729 { 730 struct mga_device *mdev = to_mga_device(pipe->crtc.dev); 731 const struct mgag200_device_info *info = mdev->info; 732 733 /* 734 * Some devices have additional limits on the size of the 735 * display mode. 736 */ 737 if (mode->hdisplay > info->max_hdisplay) 738 return MODE_VIRTUAL_X; 739 if (mode->vdisplay > info->max_vdisplay) 740 return MODE_VIRTUAL_Y; 741 742 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 743 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 744 return MODE_H_ILLEGAL; 745 } 746 747 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 748 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 749 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 750 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 751 return MODE_BAD; 752 } 753 754 return MODE_OK; 755 } 756 757 static void 758 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb, 759 struct drm_rect *clip, const struct iosys_map *map) 760 { 761 void __iomem *dst = mdev->vram; 762 void *vmap = map->vaddr; /* TODO: Use mapping abstraction properly */ 763 764 dst += drm_fb_clip_offset(fb->pitches[0], fb->format, clip); 765 drm_fb_memcpy_toio(dst, fb->pitches[0], vmap, fb, clip); 766 } 767 768 static void 769 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe, 770 struct drm_crtc_state *crtc_state, 771 struct drm_plane_state *plane_state) 772 { 773 struct drm_crtc *crtc = &pipe->crtc; 774 struct drm_device *dev = crtc->dev; 775 struct mga_device *mdev = to_mga_device(dev); 776 struct mgag200_pll *pixpll = &mdev->pixpll; 777 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 778 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 779 struct drm_framebuffer *fb = plane_state->fb; 780 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 781 struct drm_rect fullscreen = { 782 .x1 = 0, 783 .x2 = fb->width, 784 .y1 = 0, 785 .y2 = fb->height, 786 }; 787 788 /* 789 * Concurrent operations could possibly trigger a call to 790 * drm_connector_helper_funcs.get_modes by trying to read the 791 * display modes. Protect access to I/O registers by acquiring 792 * the I/O-register lock. 793 */ 794 mutex_lock(&mdev->rmmio_lock); 795 796 if (mdev->type == G200_WB || mdev->type == G200_EW3) 797 mgag200_g200wb_hold_bmc(mdev); 798 799 mgag200_set_format_regs(mdev, fb); 800 mgag200_set_mode_regs(mdev, adjusted_mode); 801 802 pixpll->funcs->update(pixpll, &mgag200_crtc_state->pixpllc); 803 804 if (mdev->type == G200_ER) 805 mgag200_g200er_reset_tagfifo(mdev); 806 807 if (IS_G200_SE(mdev)) 808 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb); 809 else if (mdev->type == G200_EV) 810 mgag200_g200ev_set_hiprilvl(mdev); 811 812 if (mdev->type == G200_WB || mdev->type == G200_EW3) 813 mgag200_g200wb_release_bmc(mdev); 814 815 if (crtc_state->gamma_lut) 816 mgag200_crtc_set_gamma(mdev, fb->format, crtc_state->gamma_lut->data); 817 else 818 mgag200_crtc_set_gamma_linear(mdev, fb->format); 819 820 mgag200_enable_display(mdev); 821 822 mgag200_handle_damage(mdev, fb, &fullscreen, &shadow_plane_state->data[0]); 823 824 /* Always scanout image at VRAM offset 0 */ 825 mgag200_set_startadd(mdev, (u32)0); 826 mgag200_set_offset(mdev, fb); 827 828 mutex_unlock(&mdev->rmmio_lock); 829 } 830 831 static void 832 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe) 833 { 834 struct drm_crtc *crtc = &pipe->crtc; 835 struct mga_device *mdev = to_mga_device(crtc->dev); 836 837 mgag200_disable_display(mdev); 838 } 839 840 static int 841 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe, 842 struct drm_plane_state *plane_state, 843 struct drm_crtc_state *crtc_state) 844 { 845 struct drm_plane *plane = plane_state->plane; 846 struct drm_device *dev = plane->dev; 847 struct mga_device *mdev = to_mga_device(dev); 848 struct mgag200_pll *pixpll = &mdev->pixpll; 849 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 850 struct drm_framebuffer *new_fb = plane_state->fb; 851 struct drm_framebuffer *fb = NULL; 852 int ret; 853 854 if (!new_fb) 855 return 0; 856 857 if (plane->state) 858 fb = plane->state->fb; 859 860 if (!fb || (fb->format != new_fb->format)) 861 crtc_state->mode_changed = true; /* update PLL settings */ 862 863 if (crtc_state->mode_changed) { 864 ret = pixpll->funcs->compute(pixpll, crtc_state->mode.clock, 865 &mgag200_crtc_state->pixpllc); 866 if (ret) 867 return ret; 868 } 869 870 if (crtc_state->color_mgmt_changed && crtc_state->gamma_lut) { 871 if (crtc_state->gamma_lut->length != 872 MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) { 873 drm_err(dev, "Wrong size for gamma_lut %zu\n", 874 crtc_state->gamma_lut->length); 875 return -EINVAL; 876 } 877 } 878 return 0; 879 } 880 881 static void 882 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe, 883 struct drm_plane_state *old_state) 884 { 885 struct drm_plane *plane = &pipe->plane; 886 struct drm_crtc *crtc = &pipe->crtc; 887 struct drm_device *dev = plane->dev; 888 struct mga_device *mdev = to_mga_device(dev); 889 struct drm_plane_state *state = plane->state; 890 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state); 891 struct drm_framebuffer *fb = state->fb; 892 struct drm_rect damage; 893 struct drm_atomic_helper_damage_iter iter; 894 895 if (!fb) 896 return; 897 898 mutex_lock(&mdev->rmmio_lock); 899 900 if (crtc->state->color_mgmt_changed && crtc->state->gamma_lut) 901 mgag200_crtc_set_gamma(mdev, fb->format, crtc->state->gamma_lut->data); 902 903 drm_atomic_helper_damage_iter_init(&iter, old_state, state); 904 drm_atomic_for_each_plane_damage(&iter, &damage) { 905 mgag200_handle_damage(mdev, fb, &damage, &shadow_plane_state->data[0]); 906 } 907 /* Always scanout image at VRAM offset 0 */ 908 mgag200_set_startadd(mdev, (u32)0); 909 mgag200_set_offset(mdev, fb); 910 911 mutex_unlock(&mdev->rmmio_lock); 912 } 913 914 static struct drm_crtc_state * 915 mgag200_simple_display_pipe_duplicate_crtc_state(struct drm_simple_display_pipe *pipe) 916 { 917 struct drm_crtc *crtc = &pipe->crtc; 918 struct drm_crtc_state *crtc_state = crtc->state; 919 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 920 struct mgag200_crtc_state *new_mgag200_crtc_state; 921 922 if (!crtc_state) 923 return NULL; 924 925 new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL); 926 if (!new_mgag200_crtc_state) 927 return NULL; 928 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base); 929 930 memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc, 931 sizeof(new_mgag200_crtc_state->pixpllc)); 932 933 return &new_mgag200_crtc_state->base; 934 } 935 936 static void mgag200_simple_display_pipe_destroy_crtc_state(struct drm_simple_display_pipe *pipe, 937 struct drm_crtc_state *crtc_state) 938 { 939 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 940 941 __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base); 942 kfree(mgag200_crtc_state); 943 } 944 945 static void mgag200_simple_display_pipe_reset_crtc(struct drm_simple_display_pipe *pipe) 946 { 947 struct drm_crtc *crtc = &pipe->crtc; 948 struct mgag200_crtc_state *mgag200_crtc_state; 949 950 if (crtc->state) { 951 mgag200_simple_display_pipe_destroy_crtc_state(pipe, crtc->state); 952 crtc->state = NULL; /* must be set to NULL here */ 953 } 954 955 mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL); 956 if (!mgag200_crtc_state) 957 return; 958 __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base); 959 } 960 961 static const struct drm_simple_display_pipe_funcs 962 mgag200_simple_display_pipe_funcs = { 963 .mode_valid = mgag200_simple_display_pipe_mode_valid, 964 .enable = mgag200_simple_display_pipe_enable, 965 .disable = mgag200_simple_display_pipe_disable, 966 .check = mgag200_simple_display_pipe_check, 967 .update = mgag200_simple_display_pipe_update, 968 .reset_crtc = mgag200_simple_display_pipe_reset_crtc, 969 .duplicate_crtc_state = mgag200_simple_display_pipe_duplicate_crtc_state, 970 .destroy_crtc_state = mgag200_simple_display_pipe_destroy_crtc_state, 971 DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS, 972 }; 973 974 static const uint32_t mgag200_simple_display_pipe_formats[] = { 975 DRM_FORMAT_XRGB8888, 976 DRM_FORMAT_RGB565, 977 DRM_FORMAT_RGB888, 978 }; 979 980 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = { 981 DRM_FORMAT_MOD_LINEAR, 982 DRM_FORMAT_MOD_INVALID 983 }; 984 985 /* 986 * Mode config 987 */ 988 989 /* Calculates a mode's required memory bandwidth (in KiB/sec). */ 990 static uint32_t mgag200_calculate_mode_bandwidth(const struct drm_display_mode *mode, 991 unsigned int bits_per_pixel) 992 { 993 uint32_t total_area, divisor; 994 uint64_t active_area, pixels_per_second, bandwidth; 995 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 996 997 divisor = 1024; 998 999 if (!mode->htotal || !mode->vtotal || !mode->clock) 1000 return 0; 1001 1002 active_area = mode->hdisplay * mode->vdisplay; 1003 total_area = mode->htotal * mode->vtotal; 1004 1005 pixels_per_second = active_area * mode->clock * 1000; 1006 do_div(pixels_per_second, total_area); 1007 1008 bandwidth = pixels_per_second * bytes_per_pixel * 100; 1009 do_div(bandwidth, divisor); 1010 1011 return (uint32_t)bandwidth; 1012 } 1013 1014 static enum drm_mode_status mgag200_mode_config_mode_valid(struct drm_device *dev, 1015 const struct drm_display_mode *mode) 1016 { 1017 static const unsigned int max_bpp = 4; // DRM_FORMAT_XRGB8888 1018 struct mga_device *mdev = to_mga_device(dev); 1019 unsigned long fbsize, fbpages, max_fbpages; 1020 const struct mgag200_device_info *info = mdev->info; 1021 1022 max_fbpages = mdev->vram_available >> PAGE_SHIFT; 1023 1024 fbsize = mode->hdisplay * mode->vdisplay * max_bpp; 1025 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); 1026 1027 if (fbpages > max_fbpages) 1028 return MODE_MEM; 1029 1030 /* 1031 * Test the mode's required memory bandwidth if the device 1032 * specifies a maximum. Not all devices do though. 1033 */ 1034 if (info->max_mem_bandwidth) { 1035 uint32_t mode_bandwidth = mgag200_calculate_mode_bandwidth(mode, max_bpp * 8); 1036 1037 if (mode_bandwidth > (info->max_mem_bandwidth * 1024)) 1038 return MODE_BAD; 1039 } 1040 1041 return MODE_OK; 1042 } 1043 1044 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = { 1045 .fb_create = drm_gem_fb_create_with_dirty, 1046 .mode_valid = mgag200_mode_config_mode_valid, 1047 .atomic_check = drm_atomic_helper_check, 1048 .atomic_commit = drm_atomic_helper_commit, 1049 }; 1050 1051 int mgag200_modeset_init(struct mga_device *mdev, resource_size_t vram_available) 1052 { 1053 struct drm_device *dev = &mdev->base; 1054 struct mga_i2c_chan *i2c = &mdev->i2c; 1055 struct drm_connector *connector = &mdev->connector; 1056 struct drm_simple_display_pipe *pipe = &mdev->display_pipe; 1057 size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats); 1058 int ret; 1059 1060 mgag200_init_regs(mdev); 1061 1062 mdev->vram_available = vram_available; 1063 1064 ret = drmm_mode_config_init(dev); 1065 if (ret) { 1066 drm_err(dev, "drmm_mode_config_init() failed, error %d\n", 1067 ret); 1068 return ret; 1069 } 1070 1071 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 1072 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 1073 dev->mode_config.preferred_depth = 24; 1074 dev->mode_config.fb_base = mdev->vram_res->start; 1075 dev->mode_config.funcs = &mgag200_mode_config_funcs; 1076 1077 ret = mgag200_i2c_init(mdev, i2c); 1078 if (ret) { 1079 drm_err(dev, "failed to add DDC bus: %d\n", ret); 1080 return ret; 1081 } 1082 1083 ret = drm_connector_init_with_ddc(dev, connector, 1084 &mga_vga_connector_funcs, 1085 DRM_MODE_CONNECTOR_VGA, 1086 &i2c->adapter); 1087 if (ret) { 1088 drm_err(dev, "drm_connector_init_with_ddc() failed: %d\n", ret); 1089 return ret; 1090 } 1091 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); 1092 1093 ret = mgag200_pixpll_init(&mdev->pixpll, mdev); 1094 if (ret) 1095 return ret; 1096 1097 ret = drm_simple_display_pipe_init(dev, pipe, 1098 &mgag200_simple_display_pipe_funcs, 1099 mgag200_simple_display_pipe_formats, 1100 format_count, 1101 mgag200_simple_display_pipe_fmtmods, 1102 connector); 1103 if (ret) { 1104 drm_err(dev, 1105 "drm_simple_display_pipe_init() failed, error %d\n", 1106 ret); 1107 return ret; 1108 } 1109 1110 drm_plane_enable_fb_damage_clips(&pipe->plane); 1111 1112 /* FIXME: legacy gamma tables, but atomic gamma doesn't work without */ 1113 drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE); 1114 1115 drm_crtc_enable_color_mgmt(&pipe->crtc, 0, false, MGAG200_LUT_SIZE); 1116 1117 drm_mode_config_reset(dev); 1118 1119 return 0; 1120 } 1121