1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/iosys-map.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_atomic_state_helper.h> 16 #include <drm/drm_crtc_helper.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_format_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem_atomic_helper.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_print.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_simple_kms_helper.h> 26 27 #include "mgag200_drv.h" 28 29 #define MGAG200_LUT_SIZE 256 30 31 /* 32 * This file contains setup code for the CRTC. 33 */ 34 35 static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, 36 const struct drm_format_info *format) 37 { 38 int i; 39 40 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 41 42 switch (format->format) { 43 case DRM_FORMAT_RGB565: 44 /* Use better interpolation, to take 32 values from 0 to 255 */ 45 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 46 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 47 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 48 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 49 } 50 /* Green has one more bit, so add padding with 0 for red and blue. */ 51 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 52 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 53 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 54 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 55 } 56 break; 57 case DRM_FORMAT_RGB888: 58 case DRM_FORMAT_XRGB8888: 59 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 60 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 61 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 62 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 63 } 64 break; 65 default: 66 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 67 &format->format); 68 break; 69 } 70 } 71 72 static void mgag200_crtc_set_gamma(struct mga_device *mdev, 73 const struct drm_format_info *format, 74 struct drm_color_lut *lut) 75 { 76 int i; 77 78 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 79 80 switch (format->format) { 81 case DRM_FORMAT_RGB565: 82 /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ 83 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 84 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].red >> 8); 85 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 86 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].blue >> 8); 87 } 88 /* Green has one more bit, so add padding with 0 for red and blue. */ 89 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 90 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 91 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 92 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 93 } 94 break; 95 case DRM_FORMAT_RGB888: 96 case DRM_FORMAT_XRGB8888: 97 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 98 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].red >> 8); 99 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].green >> 8); 100 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].blue >> 8); 101 } 102 break; 103 default: 104 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 105 &format->format); 106 break; 107 } 108 } 109 110 static inline void mga_wait_vsync(struct mga_device *mdev) 111 { 112 unsigned long timeout = jiffies + HZ/10; 113 unsigned int status = 0; 114 115 do { 116 status = RREG32(MGAREG_Status); 117 } while ((status & 0x08) && time_before(jiffies, timeout)); 118 timeout = jiffies + HZ/10; 119 status = 0; 120 do { 121 status = RREG32(MGAREG_Status); 122 } while (!(status & 0x08) && time_before(jiffies, timeout)); 123 } 124 125 static inline void mga_wait_busy(struct mga_device *mdev) 126 { 127 unsigned long timeout = jiffies + HZ; 128 unsigned int status = 0; 129 do { 130 status = RREG8(MGAREG_Status + 2); 131 } while ((status & 0x01) && time_before(jiffies, timeout)); 132 } 133 134 static void mgag200_g200wb_hold_bmc(struct mga_device *mdev) 135 { 136 u8 tmp; 137 int iter_max; 138 139 /* 1- The first step is to warn the BMC of an upcoming mode change. 140 * We are putting the misc<0> to output.*/ 141 142 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); 143 tmp = RREG8(DAC_DATA); 144 tmp |= 0x10; 145 WREG_DAC(MGA1064_GEN_IO_CTL, tmp); 146 147 /* we are putting a 1 on the misc<0> line */ 148 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 149 tmp = RREG8(DAC_DATA); 150 tmp |= 0x10; 151 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 152 153 /* 2- Second step to mask and further scan request 154 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) 155 */ 156 WREG8(DAC_INDEX, MGA1064_SPAREREG); 157 tmp = RREG8(DAC_DATA); 158 tmp |= 0x80; 159 WREG_DAC(MGA1064_SPAREREG, tmp); 160 161 /* 3a- the third step is to verifu if there is an active scan 162 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) 163 */ 164 iter_max = 300; 165 while (!(tmp & 0x1) && iter_max) { 166 WREG8(DAC_INDEX, MGA1064_SPAREREG); 167 tmp = RREG8(DAC_DATA); 168 udelay(1000); 169 iter_max--; 170 } 171 172 /* 3b- this step occurs only if the remove is actually scanning 173 * we are waiting for the end of the frame which is a 1 on 174 * remvsyncsts (XSPAREREG<1>) 175 */ 176 if (iter_max) { 177 iter_max = 300; 178 while ((tmp & 0x2) && iter_max) { 179 WREG8(DAC_INDEX, MGA1064_SPAREREG); 180 tmp = RREG8(DAC_DATA); 181 udelay(1000); 182 iter_max--; 183 } 184 } 185 } 186 187 static void mgag200_g200wb_release_bmc(struct mga_device *mdev) 188 { 189 u8 tmp; 190 191 /* 1- The first step is to ensure that the vrsten and hrsten are set */ 192 WREG8(MGAREG_CRTCEXT_INDEX, 1); 193 tmp = RREG8(MGAREG_CRTCEXT_DATA); 194 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); 195 196 /* 2- second step is to assert the rstlvl2 */ 197 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 198 tmp = RREG8(DAC_DATA); 199 tmp |= 0x8; 200 WREG8(DAC_DATA, tmp); 201 202 /* wait 10 us */ 203 udelay(10); 204 205 /* 3- deassert rstlvl2 */ 206 tmp &= ~0x08; 207 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 208 WREG8(DAC_DATA, tmp); 209 210 /* 4- remove mask of scan request */ 211 WREG8(DAC_INDEX, MGA1064_SPAREREG); 212 tmp = RREG8(DAC_DATA); 213 tmp &= ~0x80; 214 WREG8(DAC_DATA, tmp); 215 216 /* 5- put back a 0 on the misc<0> line */ 217 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 218 tmp = RREG8(DAC_DATA); 219 tmp &= ~0x10; 220 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 221 } 222 223 /* 224 * This is how the framebuffer base address is stored in g200 cards: 225 * * Assume @offset is the gpu_addr variable of the framebuffer object 226 * * Then addr is the number of _pixels_ (not bytes) from the start of 227 * VRAM to the first pixel we want to display. (divided by 2 for 32bit 228 * framebuffers) 229 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 230 * addr<20> -> CRTCEXT0<6> 231 * addr<19-16> -> CRTCEXT0<3-0> 232 * addr<15-8> -> CRTCC<7-0> 233 * addr<7-0> -> CRTCD<7-0> 234 * 235 * CRTCEXT0 has to be programmed last to trigger an update and make the 236 * new addr variable take effect. 237 */ 238 static void mgag200_set_startadd(struct mga_device *mdev, 239 unsigned long offset) 240 { 241 struct drm_device *dev = &mdev->base; 242 u32 startadd; 243 u8 crtcc, crtcd, crtcext0; 244 245 startadd = offset / 8; 246 247 if (startadd > 0) 248 drm_WARN_ON_ONCE(dev, mdev->flags & MGAG200_FLAG_HW_BUG_NO_STARTADD); 249 250 /* 251 * Can't store addresses any higher than that, but we also 252 * don't have more than 16 MiB of memory, so it should be fine. 253 */ 254 drm_WARN_ON(dev, startadd > 0x1fffff); 255 256 RREG_ECRT(0x00, crtcext0); 257 258 crtcc = (startadd >> 8) & 0xff; 259 crtcd = startadd & 0xff; 260 crtcext0 &= 0xb0; 261 crtcext0 |= ((startadd >> 14) & BIT(6)) | 262 ((startadd >> 16) & 0x0f); 263 264 WREG_CRT(0x0c, crtcc); 265 WREG_CRT(0x0d, crtcd); 266 WREG_ECRT(0x00, crtcext0); 267 } 268 269 static void mgag200_set_dac_regs(struct mga_device *mdev) 270 { 271 size_t i; 272 u8 dacvalue[] = { 273 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, 274 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, 275 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, 276 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, 277 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 278 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, 279 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, 280 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, 281 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, 282 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 283 }; 284 285 switch (mdev->type) { 286 case G200_PCI: 287 case G200_AGP: 288 dacvalue[MGA1064_SYS_PLL_M] = 0x04; 289 dacvalue[MGA1064_SYS_PLL_N] = 0x2D; 290 dacvalue[MGA1064_SYS_PLL_P] = 0x19; 291 break; 292 case G200_SE_A: 293 case G200_SE_B: 294 dacvalue[MGA1064_VREF_CTL] = 0x03; 295 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 296 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | 297 MGA1064_MISC_CTL_VGA8 | 298 MGA1064_MISC_CTL_DAC_RAM_CS; 299 break; 300 case G200_WB: 301 case G200_EW3: 302 dacvalue[MGA1064_VREF_CTL] = 0x07; 303 break; 304 case G200_EV: 305 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 306 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 307 MGA1064_MISC_CTL_DAC_RAM_CS; 308 break; 309 case G200_EH: 310 case G200_EH3: 311 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 312 MGA1064_MISC_CTL_DAC_RAM_CS; 313 break; 314 case G200_ER: 315 break; 316 } 317 318 for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { 319 if ((i <= 0x17) || 320 (i == 0x1b) || 321 (i == 0x1c) || 322 ((i >= 0x1f) && (i <= 0x29)) || 323 ((i >= 0x30) && (i <= 0x37))) 324 continue; 325 if (IS_G200_SE(mdev) && 326 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) 327 continue; 328 if ((mdev->type == G200_EV || 329 mdev->type == G200_WB || 330 mdev->type == G200_EH || 331 mdev->type == G200_EW3 || 332 mdev->type == G200_EH3) && 333 (i >= 0x44) && (i <= 0x4e)) 334 continue; 335 336 WREG_DAC(i, dacvalue[i]); 337 } 338 339 if (mdev->type == G200_ER) 340 WREG_DAC(0x90, 0); 341 } 342 343 static void mgag200_init_regs(struct mga_device *mdev) 344 { 345 u8 crtc11, misc; 346 347 mgag200_set_dac_regs(mdev); 348 349 WREG_SEQ(2, 0x0f); 350 WREG_SEQ(3, 0x00); 351 WREG_SEQ(4, 0x0e); 352 353 WREG_CRT(10, 0); 354 WREG_CRT(11, 0); 355 WREG_CRT(12, 0); 356 WREG_CRT(13, 0); 357 WREG_CRT(14, 0); 358 WREG_CRT(15, 0); 359 360 RREG_CRT(0x11, crtc11); 361 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | 362 MGAREG_CRTC11_VINTEN | 363 MGAREG_CRTC11_VINTCLR); 364 WREG_CRT(0x11, crtc11); 365 366 if (mdev->type == G200_ER) 367 WREG_ECRT(0x24, 0x5); 368 369 if (mdev->type == G200_EW3) 370 WREG_ECRT(0x34, 0x5); 371 372 misc = RREG8(MGA_MISC_IN); 373 misc |= MGAREG_MISC_IOADSEL; 374 WREG8(MGA_MISC_OUT, misc); 375 } 376 377 static void mgag200_set_mode_regs(struct mga_device *mdev, 378 const struct drm_display_mode *mode) 379 { 380 unsigned int hdisplay, hsyncstart, hsyncend, htotal; 381 unsigned int vdisplay, vsyncstart, vsyncend, vtotal; 382 u8 misc, crtcext1, crtcext2, crtcext5; 383 384 hdisplay = mode->hdisplay / 8 - 1; 385 hsyncstart = mode->hsync_start / 8 - 1; 386 hsyncend = mode->hsync_end / 8 - 1; 387 htotal = mode->htotal / 8 - 1; 388 389 /* Work around hardware quirk */ 390 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 391 htotal++; 392 393 vdisplay = mode->vdisplay - 1; 394 vsyncstart = mode->vsync_start - 1; 395 vsyncend = mode->vsync_end - 1; 396 vtotal = mode->vtotal - 2; 397 398 misc = RREG8(MGA_MISC_IN); 399 400 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 401 misc |= MGAREG_MISC_HSYNCPOL; 402 else 403 misc &= ~MGAREG_MISC_HSYNCPOL; 404 405 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 406 misc |= MGAREG_MISC_VSYNCPOL; 407 else 408 misc &= ~MGAREG_MISC_VSYNCPOL; 409 410 crtcext1 = (((htotal - 4) & 0x100) >> 8) | 411 ((hdisplay & 0x100) >> 7) | 412 ((hsyncstart & 0x100) >> 6) | 413 (htotal & 0x40); 414 if (mdev->type == G200_WB || mdev->type == G200_EW3) 415 crtcext1 |= BIT(7) | /* vrsten */ 416 BIT(3); /* hrsten */ 417 418 crtcext2 = ((vtotal & 0xc00) >> 10) | 419 ((vdisplay & 0x400) >> 8) | 420 ((vdisplay & 0xc00) >> 7) | 421 ((vsyncstart & 0xc00) >> 5) | 422 ((vdisplay & 0x400) >> 3); 423 crtcext5 = 0x00; 424 425 WREG_CRT(0, htotal - 4); 426 WREG_CRT(1, hdisplay); 427 WREG_CRT(2, hdisplay); 428 WREG_CRT(3, (htotal & 0x1F) | 0x80); 429 WREG_CRT(4, hsyncstart); 430 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 431 WREG_CRT(6, vtotal & 0xFF); 432 WREG_CRT(7, ((vtotal & 0x100) >> 8) | 433 ((vdisplay & 0x100) >> 7) | 434 ((vsyncstart & 0x100) >> 6) | 435 ((vdisplay & 0x100) >> 5) | 436 ((vdisplay & 0x100) >> 4) | /* linecomp */ 437 ((vtotal & 0x200) >> 4) | 438 ((vdisplay & 0x200) >> 3) | 439 ((vsyncstart & 0x200) >> 2)); 440 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 441 ((vdisplay & 0x200) >> 3)); 442 WREG_CRT(16, vsyncstart & 0xFF); 443 WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 444 WREG_CRT(18, vdisplay & 0xFF); 445 WREG_CRT(20, 0); 446 WREG_CRT(21, vdisplay & 0xFF); 447 WREG_CRT(22, (vtotal + 1) & 0xFF); 448 WREG_CRT(23, 0xc3); 449 WREG_CRT(24, vdisplay & 0xFF); 450 451 WREG_ECRT(0x01, crtcext1); 452 WREG_ECRT(0x02, crtcext2); 453 WREG_ECRT(0x05, crtcext5); 454 455 WREG8(MGA_MISC_OUT, misc); 456 } 457 458 static u8 mgag200_get_bpp_shift(const struct drm_format_info *format) 459 { 460 static const u8 bpp_shift[] = {0, 1, 0, 2}; 461 462 return bpp_shift[format->cpp[0] - 1]; 463 } 464 465 /* 466 * Calculates the HW offset value from the framebuffer's pitch. The 467 * offset is a multiple of the pixel size and depends on the display 468 * format. 469 */ 470 static u32 mgag200_calculate_offset(struct mga_device *mdev, 471 const struct drm_framebuffer *fb) 472 { 473 u32 offset = fb->pitches[0] / fb->format->cpp[0]; 474 u8 bppshift = mgag200_get_bpp_shift(fb->format); 475 476 if (fb->format->cpp[0] * 8 == 24) 477 offset = (offset * 3) >> (4 - bppshift); 478 else 479 offset = offset >> (4 - bppshift); 480 481 return offset; 482 } 483 484 static void mgag200_set_offset(struct mga_device *mdev, 485 const struct drm_framebuffer *fb) 486 { 487 u8 crtc13, crtcext0; 488 u32 offset = mgag200_calculate_offset(mdev, fb); 489 490 RREG_ECRT(0, crtcext0); 491 492 crtc13 = offset & 0xff; 493 494 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK; 495 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK; 496 497 WREG_CRT(0x13, crtc13); 498 WREG_ECRT(0x00, crtcext0); 499 } 500 501 static void mgag200_set_format_regs(struct mga_device *mdev, 502 const struct drm_framebuffer *fb) 503 { 504 struct drm_device *dev = &mdev->base; 505 const struct drm_format_info *format = fb->format; 506 unsigned int bpp, bppshift, scale; 507 u8 crtcext3, xmulctrl; 508 509 bpp = format->cpp[0] * 8; 510 511 bppshift = mgag200_get_bpp_shift(format); 512 switch (bpp) { 513 case 24: 514 scale = ((1 << bppshift) * 3) - 1; 515 break; 516 default: 517 scale = (1 << bppshift) - 1; 518 break; 519 } 520 521 RREG_ECRT(3, crtcext3); 522 523 switch (bpp) { 524 case 8: 525 xmulctrl = MGA1064_MUL_CTL_8bits; 526 break; 527 case 16: 528 if (format->depth == 15) 529 xmulctrl = MGA1064_MUL_CTL_15bits; 530 else 531 xmulctrl = MGA1064_MUL_CTL_16bits; 532 break; 533 case 24: 534 xmulctrl = MGA1064_MUL_CTL_24bits; 535 break; 536 case 32: 537 xmulctrl = MGA1064_MUL_CTL_32_24bits; 538 break; 539 default: 540 /* BUG: We should have caught this problem already. */ 541 drm_WARN_ON(dev, "invalid format depth\n"); 542 return; 543 } 544 545 crtcext3 &= ~GENMASK(2, 0); 546 crtcext3 |= scale; 547 548 WREG_DAC(MGA1064_MUL_CTL, xmulctrl); 549 550 WREG_GFX(0, 0x00); 551 WREG_GFX(1, 0x00); 552 WREG_GFX(2, 0x00); 553 WREG_GFX(3, 0x00); 554 WREG_GFX(4, 0x00); 555 WREG_GFX(5, 0x40); 556 /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode), 557 * so that it doesn't hang when running kexec/kdump on G200_SE rev42. 558 */ 559 WREG_GFX(6, 0x0d); 560 WREG_GFX(7, 0x0f); 561 WREG_GFX(8, 0x0f); 562 563 WREG_ECRT(3, crtcext3); 564 } 565 566 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev) 567 { 568 static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */ 569 u32 memctl; 570 571 memctl = RREG32(MGAREG_MEMCTL); 572 573 memctl |= RESET_FLAG; 574 WREG32(MGAREG_MEMCTL, memctl); 575 576 udelay(1000); 577 578 memctl &= ~RESET_FLAG; 579 WREG32(MGAREG_MEMCTL, memctl); 580 } 581 582 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev, 583 const struct drm_display_mode *mode, 584 const struct drm_framebuffer *fb) 585 { 586 u32 unique_rev_id = mdev->model.g200se.unique_rev_id; 587 unsigned int hiprilvl; 588 u8 crtcext6; 589 590 if (unique_rev_id >= 0x04) { 591 hiprilvl = 0; 592 } else if (unique_rev_id >= 0x02) { 593 unsigned int bpp; 594 unsigned long mb; 595 596 if (fb->format->cpp[0] * 8 > 16) 597 bpp = 32; 598 else if (fb->format->cpp[0] * 8 > 8) 599 bpp = 16; 600 else 601 bpp = 8; 602 603 mb = (mode->clock * bpp) / 1000; 604 if (mb > 3100) 605 hiprilvl = 0; 606 else if (mb > 2600) 607 hiprilvl = 1; 608 else if (mb > 1900) 609 hiprilvl = 2; 610 else if (mb > 1160) 611 hiprilvl = 3; 612 else if (mb > 440) 613 hiprilvl = 4; 614 else 615 hiprilvl = 5; 616 617 } else if (unique_rev_id >= 0x01) { 618 hiprilvl = 3; 619 } else { 620 hiprilvl = 4; 621 } 622 623 crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */ 624 625 WREG_ECRT(0x06, crtcext6); 626 } 627 628 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev) 629 { 630 WREG_ECRT(0x06, 0x00); 631 } 632 633 static void mgag200_enable_display(struct mga_device *mdev) 634 { 635 u8 seq0, seq1, crtcext1; 636 637 RREG_SEQ(0x00, seq0); 638 seq0 |= MGAREG_SEQ0_SYNCRST | 639 MGAREG_SEQ0_ASYNCRST; 640 WREG_SEQ(0x00, seq0); 641 642 /* 643 * TODO: replace busy waiting with vblank IRQ; put 644 * msleep(50) before changing SCROFF 645 */ 646 mga_wait_vsync(mdev); 647 mga_wait_busy(mdev); 648 649 RREG_SEQ(0x01, seq1); 650 seq1 &= ~MGAREG_SEQ1_SCROFF; 651 WREG_SEQ(0x01, seq1); 652 653 msleep(20); 654 655 RREG_ECRT(0x01, crtcext1); 656 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF; 657 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF; 658 WREG_ECRT(0x01, crtcext1); 659 } 660 661 static void mgag200_disable_display(struct mga_device *mdev) 662 { 663 u8 seq0, seq1, crtcext1; 664 665 RREG_SEQ(0x00, seq0); 666 seq0 &= ~MGAREG_SEQ0_SYNCRST; 667 WREG_SEQ(0x00, seq0); 668 669 /* 670 * TODO: replace busy waiting with vblank IRQ; put 671 * msleep(50) before changing SCROFF 672 */ 673 mga_wait_vsync(mdev); 674 mga_wait_busy(mdev); 675 676 RREG_SEQ(0x01, seq1); 677 seq1 |= MGAREG_SEQ1_SCROFF; 678 WREG_SEQ(0x01, seq1); 679 680 msleep(20); 681 682 RREG_ECRT(0x01, crtcext1); 683 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF | 684 MGAREG_CRTCEXT1_HSYNCOFF; 685 WREG_ECRT(0x01, crtcext1); 686 } 687 688 /* 689 * Connector 690 */ 691 692 static int mga_vga_get_modes(struct drm_connector *connector) 693 { 694 struct mga_connector *mga_connector = to_mga_connector(connector); 695 struct edid *edid; 696 int ret = 0; 697 698 edid = drm_get_edid(connector, &mga_connector->i2c->adapter); 699 if (edid) { 700 drm_connector_update_edid_property(connector, edid); 701 ret = drm_add_edid_modes(connector, edid); 702 kfree(edid); 703 } 704 return ret; 705 } 706 707 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode, 708 int bits_per_pixel) 709 { 710 uint32_t total_area, divisor; 711 uint64_t active_area, pixels_per_second, bandwidth; 712 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 713 714 divisor = 1024; 715 716 if (!mode->htotal || !mode->vtotal || !mode->clock) 717 return 0; 718 719 active_area = mode->hdisplay * mode->vdisplay; 720 total_area = mode->htotal * mode->vtotal; 721 722 pixels_per_second = active_area * mode->clock * 1000; 723 do_div(pixels_per_second, total_area); 724 725 bandwidth = pixels_per_second * bytes_per_pixel * 100; 726 do_div(bandwidth, divisor); 727 728 return (uint32_t)(bandwidth); 729 } 730 731 #define MODE_BANDWIDTH MODE_BAD 732 733 static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector, 734 struct drm_display_mode *mode) 735 { 736 struct drm_device *dev = connector->dev; 737 struct mga_device *mdev = to_mga_device(dev); 738 int bpp = 32; 739 740 if (IS_G200_SE(mdev)) { 741 u32 unique_rev_id = mdev->model.g200se.unique_rev_id; 742 743 if (unique_rev_id == 0x01) { 744 if (mode->hdisplay > 1600) 745 return MODE_VIRTUAL_X; 746 if (mode->vdisplay > 1200) 747 return MODE_VIRTUAL_Y; 748 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 749 > (24400 * 1024)) 750 return MODE_BANDWIDTH; 751 } else if (unique_rev_id == 0x02) { 752 if (mode->hdisplay > 1920) 753 return MODE_VIRTUAL_X; 754 if (mode->vdisplay > 1200) 755 return MODE_VIRTUAL_Y; 756 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 757 > (30100 * 1024)) 758 return MODE_BANDWIDTH; 759 } else { 760 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 761 > (55000 * 1024)) 762 return MODE_BANDWIDTH; 763 } 764 } else if (mdev->type == G200_WB) { 765 if (mode->hdisplay > 1280) 766 return MODE_VIRTUAL_X; 767 if (mode->vdisplay > 1024) 768 return MODE_VIRTUAL_Y; 769 if (mga_vga_calculate_mode_bandwidth(mode, bpp) > 770 (31877 * 1024)) 771 return MODE_BANDWIDTH; 772 } else if (mdev->type == G200_EV && 773 (mga_vga_calculate_mode_bandwidth(mode, bpp) 774 > (32700 * 1024))) { 775 return MODE_BANDWIDTH; 776 } else if (mdev->type == G200_EH && 777 (mga_vga_calculate_mode_bandwidth(mode, bpp) 778 > (37500 * 1024))) { 779 return MODE_BANDWIDTH; 780 } else if (mdev->type == G200_ER && 781 (mga_vga_calculate_mode_bandwidth(mode, 782 bpp) > (55000 * 1024))) { 783 return MODE_BANDWIDTH; 784 } 785 786 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 787 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 788 return MODE_H_ILLEGAL; 789 } 790 791 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 792 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 793 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 794 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 795 return MODE_BAD; 796 } 797 798 /* Validate the mode input by the user */ 799 if (connector->cmdline_mode.specified) { 800 if (connector->cmdline_mode.bpp_specified) 801 bpp = connector->cmdline_mode.bpp; 802 } 803 804 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->vram_fb_available) { 805 if (connector->cmdline_mode.specified) 806 connector->cmdline_mode.specified = false; 807 return MODE_BAD; 808 } 809 810 return MODE_OK; 811 } 812 813 static void mga_connector_destroy(struct drm_connector *connector) 814 { 815 struct mga_connector *mga_connector = to_mga_connector(connector); 816 mgag200_i2c_destroy(mga_connector->i2c); 817 drm_connector_cleanup(connector); 818 } 819 820 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { 821 .get_modes = mga_vga_get_modes, 822 .mode_valid = mga_vga_mode_valid, 823 }; 824 825 static const struct drm_connector_funcs mga_vga_connector_funcs = { 826 .reset = drm_atomic_helper_connector_reset, 827 .fill_modes = drm_helper_probe_single_connector_modes, 828 .destroy = mga_connector_destroy, 829 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 830 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 831 }; 832 833 static int mgag200_vga_connector_init(struct mga_device *mdev) 834 { 835 struct drm_device *dev = &mdev->base; 836 struct mga_connector *mconnector = &mdev->connector; 837 struct drm_connector *connector = &mconnector->base; 838 struct mga_i2c_chan *i2c; 839 int ret; 840 841 i2c = mgag200_i2c_create(dev); 842 if (!i2c) 843 drm_warn(dev, "failed to add DDC bus\n"); 844 845 ret = drm_connector_init_with_ddc(dev, connector, 846 &mga_vga_connector_funcs, 847 DRM_MODE_CONNECTOR_VGA, 848 &i2c->adapter); 849 if (ret) 850 goto err_mgag200_i2c_destroy; 851 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); 852 853 mconnector->i2c = i2c; 854 855 return 0; 856 857 err_mgag200_i2c_destroy: 858 mgag200_i2c_destroy(i2c); 859 return ret; 860 } 861 862 /* 863 * Simple Display Pipe 864 */ 865 866 static enum drm_mode_status 867 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 868 const struct drm_display_mode *mode) 869 { 870 return MODE_OK; 871 } 872 873 static void 874 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb, 875 struct drm_rect *clip, const struct iosys_map *map) 876 { 877 void __iomem *dst = mdev->vram; 878 void *vmap = map->vaddr; /* TODO: Use mapping abstraction properly */ 879 880 dst += drm_fb_clip_offset(fb->pitches[0], fb->format, clip); 881 drm_fb_memcpy_toio(dst, fb->pitches[0], vmap, fb, clip); 882 } 883 884 static void 885 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe, 886 struct drm_crtc_state *crtc_state, 887 struct drm_plane_state *plane_state) 888 { 889 struct drm_crtc *crtc = &pipe->crtc; 890 struct drm_device *dev = crtc->dev; 891 struct mga_device *mdev = to_mga_device(dev); 892 struct mgag200_pll *pixpll = &mdev->pixpll; 893 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 894 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 895 struct drm_framebuffer *fb = plane_state->fb; 896 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 897 struct drm_rect fullscreen = { 898 .x1 = 0, 899 .x2 = fb->width, 900 .y1 = 0, 901 .y2 = fb->height, 902 }; 903 904 /* 905 * Concurrent operations could possibly trigger a call to 906 * drm_connector_helper_funcs.get_modes by trying to read the 907 * display modes. Protect access to I/O registers by acquiring 908 * the I/O-register lock. 909 */ 910 mutex_lock(&mdev->rmmio_lock); 911 912 if (mdev->type == G200_WB || mdev->type == G200_EW3) 913 mgag200_g200wb_hold_bmc(mdev); 914 915 mgag200_set_format_regs(mdev, fb); 916 mgag200_set_mode_regs(mdev, adjusted_mode); 917 918 pixpll->funcs->update(pixpll, &mgag200_crtc_state->pixpllc); 919 920 if (mdev->type == G200_ER) 921 mgag200_g200er_reset_tagfifo(mdev); 922 923 if (IS_G200_SE(mdev)) 924 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb); 925 else if (mdev->type == G200_EV) 926 mgag200_g200ev_set_hiprilvl(mdev); 927 928 if (mdev->type == G200_WB || mdev->type == G200_EW3) 929 mgag200_g200wb_release_bmc(mdev); 930 931 if (crtc_state->gamma_lut) 932 mgag200_crtc_set_gamma(mdev, fb->format, crtc_state->gamma_lut->data); 933 else 934 mgag200_crtc_set_gamma_linear(mdev, fb->format); 935 936 mgag200_enable_display(mdev); 937 938 mgag200_handle_damage(mdev, fb, &fullscreen, &shadow_plane_state->data[0]); 939 940 /* Always scanout image at VRAM offset 0 */ 941 mgag200_set_startadd(mdev, (u32)0); 942 mgag200_set_offset(mdev, fb); 943 944 mutex_unlock(&mdev->rmmio_lock); 945 } 946 947 static void 948 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe) 949 { 950 struct drm_crtc *crtc = &pipe->crtc; 951 struct mga_device *mdev = to_mga_device(crtc->dev); 952 953 mgag200_disable_display(mdev); 954 } 955 956 static int 957 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe, 958 struct drm_plane_state *plane_state, 959 struct drm_crtc_state *crtc_state) 960 { 961 struct drm_plane *plane = plane_state->plane; 962 struct drm_device *dev = plane->dev; 963 struct mga_device *mdev = to_mga_device(dev); 964 struct mgag200_pll *pixpll = &mdev->pixpll; 965 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 966 struct drm_framebuffer *new_fb = plane_state->fb; 967 struct drm_framebuffer *fb = NULL; 968 int ret; 969 970 if (!new_fb) 971 return 0; 972 973 if (plane->state) 974 fb = plane->state->fb; 975 976 if (!fb || (fb->format != new_fb->format)) 977 crtc_state->mode_changed = true; /* update PLL settings */ 978 979 if (crtc_state->mode_changed) { 980 ret = pixpll->funcs->compute(pixpll, crtc_state->mode.clock, 981 &mgag200_crtc_state->pixpllc); 982 if (ret) 983 return ret; 984 } 985 986 if (crtc_state->color_mgmt_changed && crtc_state->gamma_lut) { 987 if (crtc_state->gamma_lut->length != 988 MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) { 989 drm_err(dev, "Wrong size for gamma_lut %zu\n", 990 crtc_state->gamma_lut->length); 991 return -EINVAL; 992 } 993 } 994 return 0; 995 } 996 997 static void 998 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe, 999 struct drm_plane_state *old_state) 1000 { 1001 struct drm_plane *plane = &pipe->plane; 1002 struct drm_crtc *crtc = &pipe->crtc; 1003 struct drm_device *dev = plane->dev; 1004 struct mga_device *mdev = to_mga_device(dev); 1005 struct drm_plane_state *state = plane->state; 1006 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state); 1007 struct drm_framebuffer *fb = state->fb; 1008 struct drm_rect damage; 1009 struct drm_atomic_helper_damage_iter iter; 1010 1011 if (!fb) 1012 return; 1013 1014 mutex_lock(&mdev->rmmio_lock); 1015 1016 if (crtc->state->color_mgmt_changed && crtc->state->gamma_lut) 1017 mgag200_crtc_set_gamma(mdev, fb->format, crtc->state->gamma_lut->data); 1018 1019 drm_atomic_helper_damage_iter_init(&iter, old_state, state); 1020 drm_atomic_for_each_plane_damage(&iter, &damage) { 1021 mgag200_handle_damage(mdev, fb, &damage, &shadow_plane_state->data[0]); 1022 } 1023 /* Always scanout image at VRAM offset 0 */ 1024 mgag200_set_startadd(mdev, (u32)0); 1025 mgag200_set_offset(mdev, fb); 1026 1027 mutex_unlock(&mdev->rmmio_lock); 1028 } 1029 1030 static struct drm_crtc_state * 1031 mgag200_simple_display_pipe_duplicate_crtc_state(struct drm_simple_display_pipe *pipe) 1032 { 1033 struct drm_crtc *crtc = &pipe->crtc; 1034 struct drm_crtc_state *crtc_state = crtc->state; 1035 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 1036 struct mgag200_crtc_state *new_mgag200_crtc_state; 1037 1038 if (!crtc_state) 1039 return NULL; 1040 1041 new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL); 1042 if (!new_mgag200_crtc_state) 1043 return NULL; 1044 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base); 1045 1046 memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc, 1047 sizeof(new_mgag200_crtc_state->pixpllc)); 1048 1049 return &new_mgag200_crtc_state->base; 1050 } 1051 1052 static void mgag200_simple_display_pipe_destroy_crtc_state(struct drm_simple_display_pipe *pipe, 1053 struct drm_crtc_state *crtc_state) 1054 { 1055 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 1056 1057 __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base); 1058 kfree(mgag200_crtc_state); 1059 } 1060 1061 static void mgag200_simple_display_pipe_reset_crtc(struct drm_simple_display_pipe *pipe) 1062 { 1063 struct drm_crtc *crtc = &pipe->crtc; 1064 struct mgag200_crtc_state *mgag200_crtc_state; 1065 1066 if (crtc->state) { 1067 mgag200_simple_display_pipe_destroy_crtc_state(pipe, crtc->state); 1068 crtc->state = NULL; /* must be set to NULL here */ 1069 } 1070 1071 mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL); 1072 if (!mgag200_crtc_state) 1073 return; 1074 __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base); 1075 } 1076 1077 static const struct drm_simple_display_pipe_funcs 1078 mgag200_simple_display_pipe_funcs = { 1079 .mode_valid = mgag200_simple_display_pipe_mode_valid, 1080 .enable = mgag200_simple_display_pipe_enable, 1081 .disable = mgag200_simple_display_pipe_disable, 1082 .check = mgag200_simple_display_pipe_check, 1083 .update = mgag200_simple_display_pipe_update, 1084 .reset_crtc = mgag200_simple_display_pipe_reset_crtc, 1085 .duplicate_crtc_state = mgag200_simple_display_pipe_duplicate_crtc_state, 1086 .destroy_crtc_state = mgag200_simple_display_pipe_destroy_crtc_state, 1087 DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS, 1088 }; 1089 1090 static const uint32_t mgag200_simple_display_pipe_formats[] = { 1091 DRM_FORMAT_XRGB8888, 1092 DRM_FORMAT_RGB565, 1093 DRM_FORMAT_RGB888, 1094 }; 1095 1096 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = { 1097 DRM_FORMAT_MOD_LINEAR, 1098 DRM_FORMAT_MOD_INVALID 1099 }; 1100 1101 /* 1102 * Mode config 1103 */ 1104 1105 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = { 1106 .fb_create = drm_gem_fb_create_with_dirty, 1107 .atomic_check = drm_atomic_helper_check, 1108 .atomic_commit = drm_atomic_helper_commit, 1109 }; 1110 1111 static unsigned int mgag200_preferred_depth(struct mga_device *mdev) 1112 { 1113 if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024)) 1114 return 16; 1115 else 1116 return 32; 1117 } 1118 1119 int mgag200_modeset_init(struct mga_device *mdev) 1120 { 1121 struct drm_device *dev = &mdev->base; 1122 struct drm_connector *connector = &mdev->connector.base; 1123 struct drm_simple_display_pipe *pipe = &mdev->display_pipe; 1124 size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats); 1125 int ret; 1126 1127 mgag200_init_regs(mdev); 1128 1129 ret = drmm_mode_config_init(dev); 1130 if (ret) { 1131 drm_err(dev, "drmm_mode_config_init() failed, error %d\n", 1132 ret); 1133 return ret; 1134 } 1135 1136 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 1137 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 1138 1139 dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev); 1140 1141 dev->mode_config.fb_base = mdev->mc.vram_base; 1142 1143 dev->mode_config.funcs = &mgag200_mode_config_funcs; 1144 1145 ret = mgag200_vga_connector_init(mdev); 1146 if (ret) { 1147 drm_err(dev, 1148 "mgag200_vga_connector_init() failed, error %d\n", 1149 ret); 1150 return ret; 1151 } 1152 1153 ret = mgag200_pixpll_init(&mdev->pixpll, mdev); 1154 if (ret) 1155 return ret; 1156 1157 ret = drm_simple_display_pipe_init(dev, pipe, 1158 &mgag200_simple_display_pipe_funcs, 1159 mgag200_simple_display_pipe_formats, 1160 format_count, 1161 mgag200_simple_display_pipe_fmtmods, 1162 connector); 1163 if (ret) { 1164 drm_err(dev, 1165 "drm_simple_display_pipe_init() failed, error %d\n", 1166 ret); 1167 return ret; 1168 } 1169 1170 drm_plane_enable_fb_damage_clips(&pipe->plane); 1171 1172 /* FIXME: legacy gamma tables, but atomic gamma doesn't work without */ 1173 drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE); 1174 1175 drm_crtc_enable_color_mgmt(&pipe->crtc, 0, false, MGAG200_LUT_SIZE); 1176 1177 drm_mode_config_reset(dev); 1178 1179 return 0; 1180 } 1181