1 /* 2 * Copyright 2010 Matt Turner. 3 * Copyright 2012 Red Hat 4 * 5 * This file is subject to the terms and conditions of the GNU General 6 * Public License version 2. See the file COPYING in the main 7 * directory of this archive for more details. 8 * 9 * Authors: Matthew Garrett 10 * Matt Turner 11 * Dave Airlie 12 */ 13 14 #include <linux/delay.h> 15 16 #include <drm/drmP.h> 17 #include <drm/drm_crtc_helper.h> 18 #include <drm/drm_plane_helper.h> 19 #include <drm/drm_probe_helper.h> 20 21 #include "mgag200_drv.h" 22 23 #define MGAG200_LUT_SIZE 256 24 25 /* 26 * This file contains setup code for the CRTC. 27 */ 28 29 static void mga_crtc_load_lut(struct drm_crtc *crtc) 30 { 31 struct drm_device *dev = crtc->dev; 32 struct mga_device *mdev = dev->dev_private; 33 struct drm_framebuffer *fb = crtc->primary->fb; 34 u16 *r_ptr, *g_ptr, *b_ptr; 35 int i; 36 37 if (!crtc->enabled) 38 return; 39 40 r_ptr = crtc->gamma_store; 41 g_ptr = r_ptr + crtc->gamma_size; 42 b_ptr = g_ptr + crtc->gamma_size; 43 44 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 45 46 if (fb && fb->format->cpp[0] * 8 == 16) { 47 int inc = (fb->format->depth == 15) ? 8 : 4; 48 u8 r, b; 49 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) { 50 if (fb->format->depth == 16) { 51 if (i > (MGAG200_LUT_SIZE >> 1)) { 52 r = b = 0; 53 } else { 54 r = *r_ptr++ >> 8; 55 b = *b_ptr++ >> 8; 56 r_ptr++; 57 b_ptr++; 58 } 59 } else { 60 r = *r_ptr++ >> 8; 61 b = *b_ptr++ >> 8; 62 } 63 /* VGA registers */ 64 WREG8(DAC_INDEX + MGA1064_COL_PAL, r); 65 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); 66 WREG8(DAC_INDEX + MGA1064_COL_PAL, b); 67 } 68 return; 69 } 70 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 71 /* VGA registers */ 72 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8); 73 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); 74 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8); 75 } 76 } 77 78 static inline void mga_wait_vsync(struct mga_device *mdev) 79 { 80 unsigned long timeout = jiffies + HZ/10; 81 unsigned int status = 0; 82 83 do { 84 status = RREG32(MGAREG_Status); 85 } while ((status & 0x08) && time_before(jiffies, timeout)); 86 timeout = jiffies + HZ/10; 87 status = 0; 88 do { 89 status = RREG32(MGAREG_Status); 90 } while (!(status & 0x08) && time_before(jiffies, timeout)); 91 } 92 93 static inline void mga_wait_busy(struct mga_device *mdev) 94 { 95 unsigned long timeout = jiffies + HZ; 96 unsigned int status = 0; 97 do { 98 status = RREG8(MGAREG_Status + 2); 99 } while ((status & 0x01) && time_before(jiffies, timeout)); 100 } 101 102 #define P_ARRAY_SIZE 9 103 104 static int mga_g200se_set_plls(struct mga_device *mdev, long clock) 105 { 106 unsigned int vcomax, vcomin, pllreffreq; 107 unsigned int delta, tmpdelta, permitteddelta; 108 unsigned int testp, testm, testn; 109 unsigned int p, m, n; 110 unsigned int computed; 111 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1}; 112 unsigned int fvv; 113 unsigned int i; 114 115 if (mdev->unique_rev_id <= 0x03) { 116 117 m = n = p = 0; 118 vcomax = 320000; 119 vcomin = 160000; 120 pllreffreq = 25000; 121 122 delta = 0xffffffff; 123 permitteddelta = clock * 5 / 1000; 124 125 for (testp = 8; testp > 0; testp /= 2) { 126 if (clock * testp > vcomax) 127 continue; 128 if (clock * testp < vcomin) 129 continue; 130 131 for (testn = 17; testn < 256; testn++) { 132 for (testm = 1; testm < 32; testm++) { 133 computed = (pllreffreq * testn) / 134 (testm * testp); 135 if (computed > clock) 136 tmpdelta = computed - clock; 137 else 138 tmpdelta = clock - computed; 139 if (tmpdelta < delta) { 140 delta = tmpdelta; 141 m = testm - 1; 142 n = testn - 1; 143 p = testp - 1; 144 } 145 } 146 } 147 } 148 } else { 149 150 151 m = n = p = 0; 152 vcomax = 1600000; 153 vcomin = 800000; 154 pllreffreq = 25000; 155 156 if (clock < 25000) 157 clock = 25000; 158 159 clock = clock * 2; 160 161 delta = 0xFFFFFFFF; 162 /* Permited delta is 0.5% as VESA Specification */ 163 permitteddelta = clock * 5 / 1000; 164 165 for (i = 0 ; i < P_ARRAY_SIZE ; i++) { 166 testp = pvalues_e4[i]; 167 168 if ((clock * testp) > vcomax) 169 continue; 170 if ((clock * testp) < vcomin) 171 continue; 172 173 for (testn = 50; testn <= 256; testn++) { 174 for (testm = 1; testm <= 32; testm++) { 175 computed = (pllreffreq * testn) / 176 (testm * testp); 177 if (computed > clock) 178 tmpdelta = computed - clock; 179 else 180 tmpdelta = clock - computed; 181 182 if (tmpdelta < delta) { 183 delta = tmpdelta; 184 m = testm - 1; 185 n = testn - 1; 186 p = testp - 1; 187 } 188 } 189 } 190 } 191 192 fvv = pllreffreq * (n + 1) / (m + 1); 193 fvv = (fvv - 800000) / 50000; 194 195 if (fvv > 15) 196 fvv = 15; 197 198 p |= (fvv << 4); 199 m |= 0x80; 200 201 clock = clock / 2; 202 } 203 204 if (delta > permitteddelta) { 205 pr_warn("PLL delta too large\n"); 206 return 1; 207 } 208 209 WREG_DAC(MGA1064_PIX_PLLC_M, m); 210 WREG_DAC(MGA1064_PIX_PLLC_N, n); 211 WREG_DAC(MGA1064_PIX_PLLC_P, p); 212 213 if (mdev->unique_rev_id >= 0x04) { 214 WREG_DAC(0x1a, 0x09); 215 msleep(20); 216 WREG_DAC(0x1a, 0x01); 217 218 } 219 220 return 0; 221 } 222 223 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock) 224 { 225 unsigned int vcomax, vcomin, pllreffreq; 226 unsigned int delta, tmpdelta; 227 unsigned int testp, testm, testn, testp2; 228 unsigned int p, m, n; 229 unsigned int computed; 230 int i, j, tmpcount, vcount; 231 bool pll_locked = false; 232 u8 tmp; 233 234 m = n = p = 0; 235 236 delta = 0xffffffff; 237 238 if (mdev->type == G200_EW3) { 239 240 vcomax = 800000; 241 vcomin = 400000; 242 pllreffreq = 25000; 243 244 for (testp = 1; testp < 8; testp++) { 245 for (testp2 = 1; testp2 < 8; testp2++) { 246 if (testp < testp2) 247 continue; 248 if ((clock * testp * testp2) > vcomax) 249 continue; 250 if ((clock * testp * testp2) < vcomin) 251 continue; 252 for (testm = 1; testm < 26; testm++) { 253 for (testn = 32; testn < 2048 ; testn++) { 254 computed = (pllreffreq * testn) / 255 (testm * testp * testp2); 256 if (computed > clock) 257 tmpdelta = computed - clock; 258 else 259 tmpdelta = clock - computed; 260 if (tmpdelta < delta) { 261 delta = tmpdelta; 262 m = ((testn & 0x100) >> 1) | 263 (testm); 264 n = (testn & 0xFF); 265 p = ((testn & 0x600) >> 3) | 266 (testp2 << 3) | 267 (testp); 268 } 269 } 270 } 271 } 272 } 273 } else { 274 275 vcomax = 550000; 276 vcomin = 150000; 277 pllreffreq = 48000; 278 279 for (testp = 1; testp < 9; testp++) { 280 if (clock * testp > vcomax) 281 continue; 282 if (clock * testp < vcomin) 283 continue; 284 285 for (testm = 1; testm < 17; testm++) { 286 for (testn = 1; testn < 151; testn++) { 287 computed = (pllreffreq * testn) / 288 (testm * testp); 289 if (computed > clock) 290 tmpdelta = computed - clock; 291 else 292 tmpdelta = clock - computed; 293 if (tmpdelta < delta) { 294 delta = tmpdelta; 295 n = testn - 1; 296 m = (testm - 1) | 297 ((n >> 1) & 0x80); 298 p = testp - 1; 299 } 300 } 301 } 302 } 303 } 304 305 for (i = 0; i <= 32 && pll_locked == false; i++) { 306 if (i > 0) { 307 WREG8(MGAREG_CRTC_INDEX, 0x1e); 308 tmp = RREG8(MGAREG_CRTC_DATA); 309 if (tmp < 0xff) 310 WREG8(MGAREG_CRTC_DATA, tmp+1); 311 } 312 313 /* set pixclkdis to 1 */ 314 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 315 tmp = RREG8(DAC_DATA); 316 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 317 WREG8(DAC_DATA, tmp); 318 319 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 320 tmp = RREG8(DAC_DATA); 321 tmp |= MGA1064_REMHEADCTL_CLKDIS; 322 WREG8(DAC_DATA, tmp); 323 324 /* select PLL Set C */ 325 tmp = RREG8(MGAREG_MEM_MISC_READ); 326 tmp |= 0x3 << 2; 327 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 328 329 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 330 tmp = RREG8(DAC_DATA); 331 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80; 332 WREG8(DAC_DATA, tmp); 333 334 udelay(500); 335 336 /* reset the PLL */ 337 WREG8(DAC_INDEX, MGA1064_VREF_CTL); 338 tmp = RREG8(DAC_DATA); 339 tmp &= ~0x04; 340 WREG8(DAC_DATA, tmp); 341 342 udelay(50); 343 344 /* program pixel pll register */ 345 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n); 346 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m); 347 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p); 348 349 udelay(50); 350 351 /* turn pll on */ 352 WREG8(DAC_INDEX, MGA1064_VREF_CTL); 353 tmp = RREG8(DAC_DATA); 354 tmp |= 0x04; 355 WREG_DAC(MGA1064_VREF_CTL, tmp); 356 357 udelay(500); 358 359 /* select the pixel pll */ 360 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 361 tmp = RREG8(DAC_DATA); 362 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 363 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 364 WREG8(DAC_DATA, tmp); 365 366 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 367 tmp = RREG8(DAC_DATA); 368 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK; 369 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL; 370 WREG8(DAC_DATA, tmp); 371 372 /* reset dotclock rate bit */ 373 WREG8(MGAREG_SEQ_INDEX, 1); 374 tmp = RREG8(MGAREG_SEQ_DATA); 375 tmp &= ~0x8; 376 WREG8(MGAREG_SEQ_DATA, tmp); 377 378 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 379 tmp = RREG8(DAC_DATA); 380 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 381 WREG8(DAC_DATA, tmp); 382 383 vcount = RREG8(MGAREG_VCOUNT); 384 385 for (j = 0; j < 30 && pll_locked == false; j++) { 386 tmpcount = RREG8(MGAREG_VCOUNT); 387 if (tmpcount < vcount) 388 vcount = 0; 389 if ((tmpcount - vcount) > 2) 390 pll_locked = true; 391 else 392 udelay(5); 393 } 394 } 395 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 396 tmp = RREG8(DAC_DATA); 397 tmp &= ~MGA1064_REMHEADCTL_CLKDIS; 398 WREG_DAC(MGA1064_REMHEADCTL, tmp); 399 return 0; 400 } 401 402 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock) 403 { 404 unsigned int vcomax, vcomin, pllreffreq; 405 unsigned int delta, tmpdelta; 406 unsigned int testp, testm, testn; 407 unsigned int p, m, n; 408 unsigned int computed; 409 u8 tmp; 410 411 m = n = p = 0; 412 vcomax = 550000; 413 vcomin = 150000; 414 pllreffreq = 50000; 415 416 delta = 0xffffffff; 417 418 for (testp = 16; testp > 0; testp--) { 419 if (clock * testp > vcomax) 420 continue; 421 if (clock * testp < vcomin) 422 continue; 423 424 for (testn = 1; testn < 257; testn++) { 425 for (testm = 1; testm < 17; testm++) { 426 computed = (pllreffreq * testn) / 427 (testm * testp); 428 if (computed > clock) 429 tmpdelta = computed - clock; 430 else 431 tmpdelta = clock - computed; 432 if (tmpdelta < delta) { 433 delta = tmpdelta; 434 n = testn - 1; 435 m = testm - 1; 436 p = testp - 1; 437 } 438 } 439 } 440 } 441 442 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 443 tmp = RREG8(DAC_DATA); 444 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 445 WREG8(DAC_DATA, tmp); 446 447 tmp = RREG8(MGAREG_MEM_MISC_READ); 448 tmp |= 0x3 << 2; 449 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 450 451 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 452 tmp = RREG8(DAC_DATA); 453 WREG8(DAC_DATA, tmp & ~0x40); 454 455 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 456 tmp = RREG8(DAC_DATA); 457 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 458 WREG8(DAC_DATA, tmp); 459 460 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m); 461 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n); 462 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p); 463 464 udelay(50); 465 466 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 467 tmp = RREG8(DAC_DATA); 468 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 469 WREG8(DAC_DATA, tmp); 470 471 udelay(500); 472 473 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 474 tmp = RREG8(DAC_DATA); 475 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 476 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 477 WREG8(DAC_DATA, tmp); 478 479 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 480 tmp = RREG8(DAC_DATA); 481 WREG8(DAC_DATA, tmp | 0x40); 482 483 tmp = RREG8(MGAREG_MEM_MISC_READ); 484 tmp |= (0x3 << 2); 485 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 486 487 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 488 tmp = RREG8(DAC_DATA); 489 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 490 WREG8(DAC_DATA, tmp); 491 492 return 0; 493 } 494 495 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock) 496 { 497 unsigned int vcomax, vcomin, pllreffreq; 498 unsigned int delta, tmpdelta; 499 unsigned int testp, testm, testn; 500 unsigned int p, m, n; 501 unsigned int computed; 502 int i, j, tmpcount, vcount; 503 u8 tmp; 504 bool pll_locked = false; 505 506 m = n = p = 0; 507 508 if (mdev->type == G200_EH3) { 509 vcomax = 3000000; 510 vcomin = 1500000; 511 pllreffreq = 25000; 512 513 delta = 0xffffffff; 514 515 testp = 0; 516 517 for (testm = 150; testm >= 6; testm--) { 518 if (clock * testm > vcomax) 519 continue; 520 if (clock * testm < vcomin) 521 continue; 522 for (testn = 120; testn >= 60; testn--) { 523 computed = (pllreffreq * testn) / testm; 524 if (computed > clock) 525 tmpdelta = computed - clock; 526 else 527 tmpdelta = clock - computed; 528 if (tmpdelta < delta) { 529 delta = tmpdelta; 530 n = testn; 531 m = testm; 532 p = testp; 533 } 534 if (delta == 0) 535 break; 536 } 537 if (delta == 0) 538 break; 539 } 540 } else { 541 542 vcomax = 800000; 543 vcomin = 400000; 544 pllreffreq = 33333; 545 546 delta = 0xffffffff; 547 548 for (testp = 16; testp > 0; testp >>= 1) { 549 if (clock * testp > vcomax) 550 continue; 551 if (clock * testp < vcomin) 552 continue; 553 554 for (testm = 1; testm < 33; testm++) { 555 for (testn = 17; testn < 257; testn++) { 556 computed = (pllreffreq * testn) / 557 (testm * testp); 558 if (computed > clock) 559 tmpdelta = computed - clock; 560 else 561 tmpdelta = clock - computed; 562 if (tmpdelta < delta) { 563 delta = tmpdelta; 564 n = testn - 1; 565 m = (testm - 1); 566 p = testp - 1; 567 } 568 if ((clock * testp) >= 600000) 569 p |= 0x80; 570 } 571 } 572 } 573 } 574 for (i = 0; i <= 32 && pll_locked == false; i++) { 575 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 576 tmp = RREG8(DAC_DATA); 577 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 578 WREG8(DAC_DATA, tmp); 579 580 tmp = RREG8(MGAREG_MEM_MISC_READ); 581 tmp |= 0x3 << 2; 582 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 583 584 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 585 tmp = RREG8(DAC_DATA); 586 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 587 WREG8(DAC_DATA, tmp); 588 589 udelay(500); 590 591 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m); 592 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n); 593 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p); 594 595 udelay(500); 596 597 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 598 tmp = RREG8(DAC_DATA); 599 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 600 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 601 WREG8(DAC_DATA, tmp); 602 603 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 604 tmp = RREG8(DAC_DATA); 605 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 606 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 607 WREG8(DAC_DATA, tmp); 608 609 vcount = RREG8(MGAREG_VCOUNT); 610 611 for (j = 0; j < 30 && pll_locked == false; j++) { 612 tmpcount = RREG8(MGAREG_VCOUNT); 613 if (tmpcount < vcount) 614 vcount = 0; 615 if ((tmpcount - vcount) > 2) 616 pll_locked = true; 617 else 618 udelay(5); 619 } 620 } 621 622 return 0; 623 } 624 625 static int mga_g200er_set_plls(struct mga_device *mdev, long clock) 626 { 627 unsigned int vcomax, vcomin, pllreffreq; 628 unsigned int delta, tmpdelta; 629 int testr, testn, testm, testo; 630 unsigned int p, m, n; 631 unsigned int computed, vco; 632 int tmp; 633 const unsigned int m_div_val[] = { 1, 2, 4, 8 }; 634 635 m = n = p = 0; 636 vcomax = 1488000; 637 vcomin = 1056000; 638 pllreffreq = 48000; 639 640 delta = 0xffffffff; 641 642 for (testr = 0; testr < 4; testr++) { 643 if (delta == 0) 644 break; 645 for (testn = 5; testn < 129; testn++) { 646 if (delta == 0) 647 break; 648 for (testm = 3; testm >= 0; testm--) { 649 if (delta == 0) 650 break; 651 for (testo = 5; testo < 33; testo++) { 652 vco = pllreffreq * (testn + 1) / 653 (testr + 1); 654 if (vco < vcomin) 655 continue; 656 if (vco > vcomax) 657 continue; 658 computed = vco / (m_div_val[testm] * (testo + 1)); 659 if (computed > clock) 660 tmpdelta = computed - clock; 661 else 662 tmpdelta = clock - computed; 663 if (tmpdelta < delta) { 664 delta = tmpdelta; 665 m = testm | (testo << 3); 666 n = testn; 667 p = testr | (testr << 3); 668 } 669 } 670 } 671 } 672 } 673 674 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 675 tmp = RREG8(DAC_DATA); 676 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 677 WREG8(DAC_DATA, tmp); 678 679 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 680 tmp = RREG8(DAC_DATA); 681 tmp |= MGA1064_REMHEADCTL_CLKDIS; 682 WREG8(DAC_DATA, tmp); 683 684 tmp = RREG8(MGAREG_MEM_MISC_READ); 685 tmp |= (0x3<<2) | 0xc0; 686 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 687 688 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 689 tmp = RREG8(DAC_DATA); 690 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 691 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 692 WREG8(DAC_DATA, tmp); 693 694 udelay(500); 695 696 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n); 697 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m); 698 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p); 699 700 udelay(50); 701 702 return 0; 703 } 704 705 static int mga_crtc_set_plls(struct mga_device *mdev, long clock) 706 { 707 switch(mdev->type) { 708 case G200_SE_A: 709 case G200_SE_B: 710 return mga_g200se_set_plls(mdev, clock); 711 break; 712 case G200_WB: 713 case G200_EW3: 714 return mga_g200wb_set_plls(mdev, clock); 715 break; 716 case G200_EV: 717 return mga_g200ev_set_plls(mdev, clock); 718 break; 719 case G200_EH: 720 case G200_EH3: 721 return mga_g200eh_set_plls(mdev, clock); 722 break; 723 case G200_ER: 724 return mga_g200er_set_plls(mdev, clock); 725 break; 726 } 727 return 0; 728 } 729 730 static void mga_g200wb_prepare(struct drm_crtc *crtc) 731 { 732 struct mga_device *mdev = crtc->dev->dev_private; 733 u8 tmp; 734 int iter_max; 735 736 /* 1- The first step is to warn the BMC of an upcoming mode change. 737 * We are putting the misc<0> to output.*/ 738 739 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); 740 tmp = RREG8(DAC_DATA); 741 tmp |= 0x10; 742 WREG_DAC(MGA1064_GEN_IO_CTL, tmp); 743 744 /* we are putting a 1 on the misc<0> line */ 745 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 746 tmp = RREG8(DAC_DATA); 747 tmp |= 0x10; 748 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 749 750 /* 2- Second step to mask and further scan request 751 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) 752 */ 753 WREG8(DAC_INDEX, MGA1064_SPAREREG); 754 tmp = RREG8(DAC_DATA); 755 tmp |= 0x80; 756 WREG_DAC(MGA1064_SPAREREG, tmp); 757 758 /* 3a- the third step is to verifu if there is an active scan 759 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) 760 */ 761 iter_max = 300; 762 while (!(tmp & 0x1) && iter_max) { 763 WREG8(DAC_INDEX, MGA1064_SPAREREG); 764 tmp = RREG8(DAC_DATA); 765 udelay(1000); 766 iter_max--; 767 } 768 769 /* 3b- this step occurs only if the remove is actually scanning 770 * we are waiting for the end of the frame which is a 1 on 771 * remvsyncsts (XSPAREREG<1>) 772 */ 773 if (iter_max) { 774 iter_max = 300; 775 while ((tmp & 0x2) && iter_max) { 776 WREG8(DAC_INDEX, MGA1064_SPAREREG); 777 tmp = RREG8(DAC_DATA); 778 udelay(1000); 779 iter_max--; 780 } 781 } 782 } 783 784 static void mga_g200wb_commit(struct drm_crtc *crtc) 785 { 786 u8 tmp; 787 struct mga_device *mdev = crtc->dev->dev_private; 788 789 /* 1- The first step is to ensure that the vrsten and hrsten are set */ 790 WREG8(MGAREG_CRTCEXT_INDEX, 1); 791 tmp = RREG8(MGAREG_CRTCEXT_DATA); 792 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); 793 794 /* 2- second step is to assert the rstlvl2 */ 795 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 796 tmp = RREG8(DAC_DATA); 797 tmp |= 0x8; 798 WREG8(DAC_DATA, tmp); 799 800 /* wait 10 us */ 801 udelay(10); 802 803 /* 3- deassert rstlvl2 */ 804 tmp &= ~0x08; 805 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 806 WREG8(DAC_DATA, tmp); 807 808 /* 4- remove mask of scan request */ 809 WREG8(DAC_INDEX, MGA1064_SPAREREG); 810 tmp = RREG8(DAC_DATA); 811 tmp &= ~0x80; 812 WREG8(DAC_DATA, tmp); 813 814 /* 5- put back a 0 on the misc<0> line */ 815 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 816 tmp = RREG8(DAC_DATA); 817 tmp &= ~0x10; 818 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 819 } 820 821 /* 822 This is how the framebuffer base address is stored in g200 cards: 823 * Assume @offset is the gpu_addr variable of the framebuffer object 824 * Then addr is the number of _pixels_ (not bytes) from the start of 825 VRAM to the first pixel we want to display. (divided by 2 for 32bit 826 framebuffers) 827 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 828 addr<20> -> CRTCEXT0<6> 829 addr<19-16> -> CRTCEXT0<3-0> 830 addr<15-8> -> CRTCC<7-0> 831 addr<7-0> -> CRTCD<7-0> 832 CRTCEXT0 has to be programmed last to trigger an update and make the 833 new addr variable take effect. 834 */ 835 static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset) 836 { 837 struct mga_device *mdev = crtc->dev->dev_private; 838 u32 addr; 839 int count; 840 u8 crtcext0; 841 842 while (RREG8(0x1fda) & 0x08); 843 while (!(RREG8(0x1fda) & 0x08)); 844 845 count = RREG8(MGAREG_VCOUNT) + 2; 846 while (RREG8(MGAREG_VCOUNT) < count); 847 848 WREG8(MGAREG_CRTCEXT_INDEX, 0); 849 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA); 850 crtcext0 &= 0xB0; 851 addr = offset / 8; 852 /* Can't store addresses any higher than that... 853 but we also don't have more than 16MB of memory, so it should be fine. */ 854 WARN_ON(addr > 0x1fffff); 855 crtcext0 |= (!!(addr & (1<<20)))<<6; 856 WREG_CRT(0x0d, (u8)(addr & 0xff)); 857 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff); 858 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0); 859 } 860 861 static int mga_crtc_do_set_base(struct drm_crtc *crtc, 862 struct drm_framebuffer *fb, 863 int x, int y, int atomic) 864 { 865 struct mga_device *mdev = crtc->dev->dev_private; 866 struct drm_gem_object *obj; 867 struct mga_framebuffer *mga_fb; 868 struct drm_gem_vram_object *gbo; 869 int ret; 870 s64 gpu_addr; 871 void *base; 872 873 if (!atomic && fb) { 874 mga_fb = to_mga_framebuffer(fb); 875 obj = mga_fb->obj; 876 gbo = drm_gem_vram_of_gem(obj); 877 878 /* unmap if console */ 879 if (&mdev->mfbdev->mfb == mga_fb) 880 drm_gem_vram_kunmap(gbo); 881 drm_gem_vram_unpin(gbo); 882 } 883 884 mga_fb = to_mga_framebuffer(crtc->primary->fb); 885 obj = mga_fb->obj; 886 gbo = drm_gem_vram_of_gem(obj); 887 888 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM); 889 if (ret) 890 return ret; 891 gpu_addr = drm_gem_vram_offset(gbo); 892 if (gpu_addr < 0) { 893 ret = (int)gpu_addr; 894 goto err_drm_gem_vram_unpin; 895 } 896 897 if (&mdev->mfbdev->mfb == mga_fb) { 898 /* if pushing console in kmap it */ 899 base = drm_gem_vram_kmap(gbo, true, NULL); 900 if (IS_ERR(base)) { 901 ret = PTR_ERR(base); 902 DRM_ERROR("failed to kmap fbcon\n"); 903 } 904 } 905 906 mga_set_start_address(crtc, (u32)gpu_addr); 907 908 return 0; 909 910 err_drm_gem_vram_unpin: 911 drm_gem_vram_unpin(gbo); 912 return ret; 913 } 914 915 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 916 struct drm_framebuffer *old_fb) 917 { 918 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0); 919 } 920 921 static int mga_crtc_mode_set(struct drm_crtc *crtc, 922 struct drm_display_mode *mode, 923 struct drm_display_mode *adjusted_mode, 924 int x, int y, struct drm_framebuffer *old_fb) 925 { 926 struct drm_device *dev = crtc->dev; 927 struct mga_device *mdev = dev->dev_private; 928 const struct drm_framebuffer *fb = crtc->primary->fb; 929 int hdisplay, hsyncstart, hsyncend, htotal; 930 int vdisplay, vsyncstart, vsyncend, vtotal; 931 int pitch; 932 int option = 0, option2 = 0; 933 int i; 934 unsigned char misc = 0; 935 unsigned char ext_vga[6]; 936 u8 bppshift; 937 938 static unsigned char dacvalue[] = { 939 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, 940 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, 941 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, 942 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, 943 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 944 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, 945 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, 946 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, 947 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, 948 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 949 }; 950 951 bppshift = mdev->bpp_shifts[fb->format->cpp[0] - 1]; 952 953 switch (mdev->type) { 954 case G200_SE_A: 955 case G200_SE_B: 956 dacvalue[MGA1064_VREF_CTL] = 0x03; 957 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 958 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | 959 MGA1064_MISC_CTL_VGA8 | 960 MGA1064_MISC_CTL_DAC_RAM_CS; 961 if (mdev->has_sdram) 962 option = 0x40049120; 963 else 964 option = 0x4004d120; 965 option2 = 0x00008000; 966 break; 967 case G200_WB: 968 case G200_EW3: 969 dacvalue[MGA1064_VREF_CTL] = 0x07; 970 option = 0x41049120; 971 option2 = 0x0000b000; 972 break; 973 case G200_EV: 974 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 975 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 976 MGA1064_MISC_CTL_DAC_RAM_CS; 977 option = 0x00000120; 978 option2 = 0x0000b000; 979 break; 980 case G200_EH: 981 case G200_EH3: 982 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 983 MGA1064_MISC_CTL_DAC_RAM_CS; 984 option = 0x00000120; 985 option2 = 0x0000b000; 986 break; 987 case G200_ER: 988 break; 989 } 990 991 switch (fb->format->cpp[0] * 8) { 992 case 8: 993 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits; 994 break; 995 case 16: 996 if (fb->format->depth == 15) 997 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits; 998 else 999 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits; 1000 break; 1001 case 24: 1002 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits; 1003 break; 1004 case 32: 1005 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits; 1006 break; 1007 } 1008 1009 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1010 misc |= 0x40; 1011 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1012 misc |= 0x80; 1013 1014 1015 for (i = 0; i < sizeof(dacvalue); i++) { 1016 if ((i <= 0x17) || 1017 (i == 0x1b) || 1018 (i == 0x1c) || 1019 ((i >= 0x1f) && (i <= 0x29)) || 1020 ((i >= 0x30) && (i <= 0x37))) 1021 continue; 1022 if (IS_G200_SE(mdev) && 1023 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) 1024 continue; 1025 if ((mdev->type == G200_EV || 1026 mdev->type == G200_WB || 1027 mdev->type == G200_EH || 1028 mdev->type == G200_EW3 || 1029 mdev->type == G200_EH3) && 1030 (i >= 0x44) && (i <= 0x4e)) 1031 continue; 1032 1033 WREG_DAC(i, dacvalue[i]); 1034 } 1035 1036 if (mdev->type == G200_ER) 1037 WREG_DAC(0x90, 0); 1038 1039 if (option) 1040 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option); 1041 if (option2) 1042 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2); 1043 1044 WREG_SEQ(2, 0xf); 1045 WREG_SEQ(3, 0); 1046 WREG_SEQ(4, 0xe); 1047 1048 pitch = fb->pitches[0] / fb->format->cpp[0]; 1049 if (fb->format->cpp[0] * 8 == 24) 1050 pitch = (pitch * 3) >> (4 - bppshift); 1051 else 1052 pitch = pitch >> (4 - bppshift); 1053 1054 hdisplay = mode->hdisplay / 8 - 1; 1055 hsyncstart = mode->hsync_start / 8 - 1; 1056 hsyncend = mode->hsync_end / 8 - 1; 1057 htotal = mode->htotal / 8 - 1; 1058 1059 /* Work around hardware quirk */ 1060 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 1061 htotal++; 1062 1063 vdisplay = mode->vdisplay - 1; 1064 vsyncstart = mode->vsync_start - 1; 1065 vsyncend = mode->vsync_end - 1; 1066 vtotal = mode->vtotal - 2; 1067 1068 WREG_GFX(0, 0); 1069 WREG_GFX(1, 0); 1070 WREG_GFX(2, 0); 1071 WREG_GFX(3, 0); 1072 WREG_GFX(4, 0); 1073 WREG_GFX(5, 0x40); 1074 WREG_GFX(6, 0x5); 1075 WREG_GFX(7, 0xf); 1076 WREG_GFX(8, 0xf); 1077 1078 WREG_CRT(0, htotal - 4); 1079 WREG_CRT(1, hdisplay); 1080 WREG_CRT(2, hdisplay); 1081 WREG_CRT(3, (htotal & 0x1F) | 0x80); 1082 WREG_CRT(4, hsyncstart); 1083 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 1084 WREG_CRT(6, vtotal & 0xFF); 1085 WREG_CRT(7, ((vtotal & 0x100) >> 8) | 1086 ((vdisplay & 0x100) >> 7) | 1087 ((vsyncstart & 0x100) >> 6) | 1088 ((vdisplay & 0x100) >> 5) | 1089 ((vdisplay & 0x100) >> 4) | /* linecomp */ 1090 ((vtotal & 0x200) >> 4)| 1091 ((vdisplay & 0x200) >> 3) | 1092 ((vsyncstart & 0x200) >> 2)); 1093 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 1094 ((vdisplay & 0x200) >> 3)); 1095 WREG_CRT(10, 0); 1096 WREG_CRT(11, 0); 1097 WREG_CRT(12, 0); 1098 WREG_CRT(13, 0); 1099 WREG_CRT(14, 0); 1100 WREG_CRT(15, 0); 1101 WREG_CRT(16, vsyncstart & 0xFF); 1102 WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 1103 WREG_CRT(18, vdisplay & 0xFF); 1104 WREG_CRT(19, pitch & 0xFF); 1105 WREG_CRT(20, 0); 1106 WREG_CRT(21, vdisplay & 0xFF); 1107 WREG_CRT(22, (vtotal + 1) & 0xFF); 1108 WREG_CRT(23, 0xc3); 1109 WREG_CRT(24, vdisplay & 0xFF); 1110 1111 ext_vga[0] = 0; 1112 ext_vga[5] = 0; 1113 1114 /* TODO interlace */ 1115 1116 ext_vga[0] |= (pitch & 0x300) >> 4; 1117 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) | 1118 ((hdisplay & 0x100) >> 7) | 1119 ((hsyncstart & 0x100) >> 6) | 1120 (htotal & 0x40); 1121 ext_vga[2] = ((vtotal & 0xc00) >> 10) | 1122 ((vdisplay & 0x400) >> 8) | 1123 ((vdisplay & 0xc00) >> 7) | 1124 ((vsyncstart & 0xc00) >> 5) | 1125 ((vdisplay & 0x400) >> 3); 1126 if (fb->format->cpp[0] * 8 == 24) 1127 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80; 1128 else 1129 ext_vga[3] = ((1 << bppshift) - 1) | 0x80; 1130 ext_vga[4] = 0; 1131 if (mdev->type == G200_WB || mdev->type == G200_EW3) 1132 ext_vga[1] |= 0x88; 1133 1134 /* Set pixel clocks */ 1135 misc = 0x2d; 1136 WREG8(MGA_MISC_OUT, misc); 1137 1138 mga_crtc_set_plls(mdev, mode->clock); 1139 1140 for (i = 0; i < 6; i++) { 1141 WREG_ECRT(i, ext_vga[i]); 1142 } 1143 1144 if (mdev->type == G200_ER) 1145 WREG_ECRT(0x24, 0x5); 1146 1147 if (mdev->type == G200_EW3) 1148 WREG_ECRT(0x34, 0x5); 1149 1150 if (mdev->type == G200_EV) { 1151 WREG_ECRT(6, 0); 1152 } 1153 1154 WREG_ECRT(0, ext_vga[0]); 1155 /* Enable mga pixel clock */ 1156 misc = 0x2d; 1157 1158 WREG8(MGA_MISC_OUT, misc); 1159 1160 if (adjusted_mode) 1161 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode)); 1162 1163 mga_crtc_do_set_base(crtc, old_fb, x, y, 0); 1164 1165 /* reset tagfifo */ 1166 if (mdev->type == G200_ER) { 1167 u32 mem_ctl = RREG32(MGAREG_MEMCTL); 1168 u8 seq1; 1169 1170 /* screen off */ 1171 WREG8(MGAREG_SEQ_INDEX, 0x01); 1172 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20; 1173 WREG8(MGAREG_SEQ_DATA, seq1); 1174 1175 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000); 1176 udelay(1000); 1177 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000); 1178 1179 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20); 1180 } 1181 1182 1183 if (IS_G200_SE(mdev)) { 1184 if (mdev->unique_rev_id >= 0x04) { 1185 WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 1186 WREG8(MGAREG_CRTCEXT_DATA, 0); 1187 } else if (mdev->unique_rev_id >= 0x02) { 1188 u8 hi_pri_lvl; 1189 u32 bpp; 1190 u32 mb; 1191 1192 if (fb->format->cpp[0] * 8 > 16) 1193 bpp = 32; 1194 else if (fb->format->cpp[0] * 8 > 8) 1195 bpp = 16; 1196 else 1197 bpp = 8; 1198 1199 mb = (mode->clock * bpp) / 1000; 1200 if (mb > 3100) 1201 hi_pri_lvl = 0; 1202 else if (mb > 2600) 1203 hi_pri_lvl = 1; 1204 else if (mb > 1900) 1205 hi_pri_lvl = 2; 1206 else if (mb > 1160) 1207 hi_pri_lvl = 3; 1208 else if (mb > 440) 1209 hi_pri_lvl = 4; 1210 else 1211 hi_pri_lvl = 5; 1212 1213 WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 1214 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl); 1215 } else { 1216 WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 1217 if (mdev->unique_rev_id >= 0x01) 1218 WREG8(MGAREG_CRTCEXT_DATA, 0x03); 1219 else 1220 WREG8(MGAREG_CRTCEXT_DATA, 0x04); 1221 } 1222 } 1223 return 0; 1224 } 1225 1226 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */ 1227 static int mga_suspend(struct drm_crtc *crtc) 1228 { 1229 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1230 struct drm_device *dev = crtc->dev; 1231 struct mga_device *mdev = dev->dev_private; 1232 struct pci_dev *pdev = dev->pdev; 1233 int option; 1234 1235 if (mdev->suspended) 1236 return 0; 1237 1238 WREG_SEQ(1, 0x20); 1239 WREG_ECRT(1, 0x30); 1240 /* Disable the pixel clock */ 1241 WREG_DAC(0x1a, 0x05); 1242 /* Power down the DAC */ 1243 WREG_DAC(0x1e, 0x18); 1244 /* Power down the pixel PLL */ 1245 WREG_DAC(0x1a, 0x0d); 1246 1247 /* Disable PLLs and clocks */ 1248 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); 1249 option &= ~(0x1F8024); 1250 pci_write_config_dword(pdev, PCI_MGA_OPTION, option); 1251 pci_set_power_state(pdev, PCI_D3hot); 1252 pci_disable_device(pdev); 1253 1254 mdev->suspended = true; 1255 1256 return 0; 1257 } 1258 1259 static int mga_resume(struct drm_crtc *crtc) 1260 { 1261 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1262 struct drm_device *dev = crtc->dev; 1263 struct mga_device *mdev = dev->dev_private; 1264 struct pci_dev *pdev = dev->pdev; 1265 int option; 1266 1267 if (!mdev->suspended) 1268 return 0; 1269 1270 pci_set_power_state(pdev, PCI_D0); 1271 pci_enable_device(pdev); 1272 1273 /* Disable sysclk */ 1274 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); 1275 option &= ~(0x4); 1276 pci_write_config_dword(pdev, PCI_MGA_OPTION, option); 1277 1278 mdev->suspended = false; 1279 1280 return 0; 1281 } 1282 1283 #endif 1284 1285 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode) 1286 { 1287 struct drm_device *dev = crtc->dev; 1288 struct mga_device *mdev = dev->dev_private; 1289 u8 seq1 = 0, crtcext1 = 0; 1290 1291 switch (mode) { 1292 case DRM_MODE_DPMS_ON: 1293 seq1 = 0; 1294 crtcext1 = 0; 1295 mga_crtc_load_lut(crtc); 1296 break; 1297 case DRM_MODE_DPMS_STANDBY: 1298 seq1 = 0x20; 1299 crtcext1 = 0x10; 1300 break; 1301 case DRM_MODE_DPMS_SUSPEND: 1302 seq1 = 0x20; 1303 crtcext1 = 0x20; 1304 break; 1305 case DRM_MODE_DPMS_OFF: 1306 seq1 = 0x20; 1307 crtcext1 = 0x30; 1308 break; 1309 } 1310 1311 #if 0 1312 if (mode == DRM_MODE_DPMS_OFF) { 1313 mga_suspend(crtc); 1314 } 1315 #endif 1316 WREG8(MGAREG_SEQ_INDEX, 0x01); 1317 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20; 1318 mga_wait_vsync(mdev); 1319 mga_wait_busy(mdev); 1320 WREG8(MGAREG_SEQ_DATA, seq1); 1321 msleep(20); 1322 WREG8(MGAREG_CRTCEXT_INDEX, 0x01); 1323 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30; 1324 WREG8(MGAREG_CRTCEXT_DATA, crtcext1); 1325 1326 #if 0 1327 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) { 1328 mga_resume(crtc); 1329 drm_helper_resume_force_mode(dev); 1330 } 1331 #endif 1332 } 1333 1334 /* 1335 * This is called before a mode is programmed. A typical use might be to 1336 * enable DPMS during the programming to avoid seeing intermediate stages, 1337 * but that's not relevant to us 1338 */ 1339 static void mga_crtc_prepare(struct drm_crtc *crtc) 1340 { 1341 struct drm_device *dev = crtc->dev; 1342 struct mga_device *mdev = dev->dev_private; 1343 u8 tmp; 1344 1345 /* mga_resume(crtc);*/ 1346 1347 WREG8(MGAREG_CRTC_INDEX, 0x11); 1348 tmp = RREG8(MGAREG_CRTC_DATA); 1349 WREG_CRT(0x11, tmp | 0x80); 1350 1351 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { 1352 WREG_SEQ(0, 1); 1353 msleep(50); 1354 WREG_SEQ(1, 0x20); 1355 msleep(20); 1356 } else { 1357 WREG8(MGAREG_SEQ_INDEX, 0x1); 1358 tmp = RREG8(MGAREG_SEQ_DATA); 1359 1360 /* start sync reset */ 1361 WREG_SEQ(0, 1); 1362 WREG_SEQ(1, tmp | 0x20); 1363 } 1364 1365 if (mdev->type == G200_WB || mdev->type == G200_EW3) 1366 mga_g200wb_prepare(crtc); 1367 1368 WREG_CRT(17, 0); 1369 } 1370 1371 /* 1372 * This is called after a mode is programmed. It should reverse anything done 1373 * by the prepare function 1374 */ 1375 static void mga_crtc_commit(struct drm_crtc *crtc) 1376 { 1377 struct drm_device *dev = crtc->dev; 1378 struct mga_device *mdev = dev->dev_private; 1379 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 1380 u8 tmp; 1381 1382 if (mdev->type == G200_WB || mdev->type == G200_EW3) 1383 mga_g200wb_commit(crtc); 1384 1385 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { 1386 msleep(50); 1387 WREG_SEQ(1, 0x0); 1388 msleep(20); 1389 WREG_SEQ(0, 0x3); 1390 } else { 1391 WREG8(MGAREG_SEQ_INDEX, 0x1); 1392 tmp = RREG8(MGAREG_SEQ_DATA); 1393 1394 tmp &= ~0x20; 1395 WREG_SEQ(0x1, tmp); 1396 WREG_SEQ(0, 3); 1397 } 1398 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 1399 } 1400 1401 /* 1402 * The core can pass us a set of gamma values to program. We actually only 1403 * use this for 8-bit mode so can't perform smooth fades on deeper modes, 1404 * but it's a requirement that we provide the function 1405 */ 1406 static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 1407 u16 *blue, uint32_t size, 1408 struct drm_modeset_acquire_ctx *ctx) 1409 { 1410 mga_crtc_load_lut(crtc); 1411 1412 return 0; 1413 } 1414 1415 /* Simple cleanup function */ 1416 static void mga_crtc_destroy(struct drm_crtc *crtc) 1417 { 1418 struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1419 1420 drm_crtc_cleanup(crtc); 1421 kfree(mga_crtc); 1422 } 1423 1424 static void mga_crtc_disable(struct drm_crtc *crtc) 1425 { 1426 DRM_DEBUG_KMS("\n"); 1427 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1428 if (crtc->primary->fb) { 1429 struct mga_device *mdev = crtc->dev->dev_private; 1430 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb); 1431 struct drm_gem_object *obj = mga_fb->obj; 1432 struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(obj); 1433 1434 /* unmap if console */ 1435 if (&mdev->mfbdev->mfb == mga_fb) 1436 drm_gem_vram_kunmap(gbo); 1437 drm_gem_vram_unpin(gbo); 1438 } 1439 crtc->primary->fb = NULL; 1440 } 1441 1442 /* These provide the minimum set of functions required to handle a CRTC */ 1443 static const struct drm_crtc_funcs mga_crtc_funcs = { 1444 .cursor_set = mga_crtc_cursor_set, 1445 .cursor_move = mga_crtc_cursor_move, 1446 .gamma_set = mga_crtc_gamma_set, 1447 .set_config = drm_crtc_helper_set_config, 1448 .destroy = mga_crtc_destroy, 1449 }; 1450 1451 static const struct drm_crtc_helper_funcs mga_helper_funcs = { 1452 .disable = mga_crtc_disable, 1453 .dpms = mga_crtc_dpms, 1454 .mode_set = mga_crtc_mode_set, 1455 .mode_set_base = mga_crtc_mode_set_base, 1456 .prepare = mga_crtc_prepare, 1457 .commit = mga_crtc_commit, 1458 }; 1459 1460 /* CRTC setup */ 1461 static void mga_crtc_init(struct mga_device *mdev) 1462 { 1463 struct mga_crtc *mga_crtc; 1464 1465 mga_crtc = kzalloc(sizeof(struct mga_crtc) + 1466 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)), 1467 GFP_KERNEL); 1468 1469 if (mga_crtc == NULL) 1470 return; 1471 1472 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs); 1473 1474 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE); 1475 mdev->mode_info.crtc = mga_crtc; 1476 1477 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs); 1478 } 1479 1480 /* 1481 * The encoder comes after the CRTC in the output pipeline, but before 1482 * the connector. It's responsible for ensuring that the digital 1483 * stream is appropriately converted into the output format. Setup is 1484 * very simple in this case - all we have to do is inform qemu of the 1485 * colour depth in order to ensure that it displays appropriately 1486 */ 1487 1488 /* 1489 * These functions are analagous to those in the CRTC code, but are intended 1490 * to handle any encoder-specific limitations 1491 */ 1492 static void mga_encoder_mode_set(struct drm_encoder *encoder, 1493 struct drm_display_mode *mode, 1494 struct drm_display_mode *adjusted_mode) 1495 { 1496 1497 } 1498 1499 static void mga_encoder_dpms(struct drm_encoder *encoder, int state) 1500 { 1501 return; 1502 } 1503 1504 static void mga_encoder_prepare(struct drm_encoder *encoder) 1505 { 1506 } 1507 1508 static void mga_encoder_commit(struct drm_encoder *encoder) 1509 { 1510 } 1511 1512 static void mga_encoder_destroy(struct drm_encoder *encoder) 1513 { 1514 struct mga_encoder *mga_encoder = to_mga_encoder(encoder); 1515 drm_encoder_cleanup(encoder); 1516 kfree(mga_encoder); 1517 } 1518 1519 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = { 1520 .dpms = mga_encoder_dpms, 1521 .mode_set = mga_encoder_mode_set, 1522 .prepare = mga_encoder_prepare, 1523 .commit = mga_encoder_commit, 1524 }; 1525 1526 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = { 1527 .destroy = mga_encoder_destroy, 1528 }; 1529 1530 static struct drm_encoder *mga_encoder_init(struct drm_device *dev) 1531 { 1532 struct drm_encoder *encoder; 1533 struct mga_encoder *mga_encoder; 1534 1535 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL); 1536 if (!mga_encoder) 1537 return NULL; 1538 1539 encoder = &mga_encoder->base; 1540 encoder->possible_crtcs = 0x1; 1541 1542 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs, 1543 DRM_MODE_ENCODER_DAC, NULL); 1544 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs); 1545 1546 return encoder; 1547 } 1548 1549 1550 static int mga_vga_get_modes(struct drm_connector *connector) 1551 { 1552 struct mga_connector *mga_connector = to_mga_connector(connector); 1553 struct edid *edid; 1554 int ret = 0; 1555 1556 edid = drm_get_edid(connector, &mga_connector->i2c->adapter); 1557 if (edid) { 1558 drm_connector_update_edid_property(connector, edid); 1559 ret = drm_add_edid_modes(connector, edid); 1560 kfree(edid); 1561 } 1562 return ret; 1563 } 1564 1565 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode, 1566 int bits_per_pixel) 1567 { 1568 uint32_t total_area, divisor; 1569 uint64_t active_area, pixels_per_second, bandwidth; 1570 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 1571 1572 divisor = 1024; 1573 1574 if (!mode->htotal || !mode->vtotal || !mode->clock) 1575 return 0; 1576 1577 active_area = mode->hdisplay * mode->vdisplay; 1578 total_area = mode->htotal * mode->vtotal; 1579 1580 pixels_per_second = active_area * mode->clock * 1000; 1581 do_div(pixels_per_second, total_area); 1582 1583 bandwidth = pixels_per_second * bytes_per_pixel * 100; 1584 do_div(bandwidth, divisor); 1585 1586 return (uint32_t)(bandwidth); 1587 } 1588 1589 #define MODE_BANDWIDTH MODE_BAD 1590 1591 static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector, 1592 struct drm_display_mode *mode) 1593 { 1594 struct drm_device *dev = connector->dev; 1595 struct mga_device *mdev = (struct mga_device*)dev->dev_private; 1596 int bpp = 32; 1597 1598 if (IS_G200_SE(mdev)) { 1599 if (mdev->unique_rev_id == 0x01) { 1600 if (mode->hdisplay > 1600) 1601 return MODE_VIRTUAL_X; 1602 if (mode->vdisplay > 1200) 1603 return MODE_VIRTUAL_Y; 1604 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1605 > (24400 * 1024)) 1606 return MODE_BANDWIDTH; 1607 } else if (mdev->unique_rev_id == 0x02) { 1608 if (mode->hdisplay > 1920) 1609 return MODE_VIRTUAL_X; 1610 if (mode->vdisplay > 1200) 1611 return MODE_VIRTUAL_Y; 1612 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1613 > (30100 * 1024)) 1614 return MODE_BANDWIDTH; 1615 } else { 1616 if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1617 > (55000 * 1024)) 1618 return MODE_BANDWIDTH; 1619 } 1620 } else if (mdev->type == G200_WB) { 1621 if (mode->hdisplay > 1280) 1622 return MODE_VIRTUAL_X; 1623 if (mode->vdisplay > 1024) 1624 return MODE_VIRTUAL_Y; 1625 if (mga_vga_calculate_mode_bandwidth(mode, bpp) > 1626 (31877 * 1024)) 1627 return MODE_BANDWIDTH; 1628 } else if (mdev->type == G200_EV && 1629 (mga_vga_calculate_mode_bandwidth(mode, bpp) 1630 > (32700 * 1024))) { 1631 return MODE_BANDWIDTH; 1632 } else if (mdev->type == G200_EH && 1633 (mga_vga_calculate_mode_bandwidth(mode, bpp) 1634 > (37500 * 1024))) { 1635 return MODE_BANDWIDTH; 1636 } else if (mdev->type == G200_ER && 1637 (mga_vga_calculate_mode_bandwidth(mode, 1638 bpp) > (55000 * 1024))) { 1639 return MODE_BANDWIDTH; 1640 } 1641 1642 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 1643 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 1644 return MODE_H_ILLEGAL; 1645 } 1646 1647 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 1648 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 1649 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 1650 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 1651 return MODE_BAD; 1652 } 1653 1654 /* Validate the mode input by the user */ 1655 if (connector->cmdline_mode.specified) { 1656 if (connector->cmdline_mode.bpp_specified) 1657 bpp = connector->cmdline_mode.bpp; 1658 } 1659 1660 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) { 1661 if (connector->cmdline_mode.specified) 1662 connector->cmdline_mode.specified = false; 1663 return MODE_BAD; 1664 } 1665 1666 return MODE_OK; 1667 } 1668 1669 static struct drm_encoder *mga_connector_best_encoder(struct drm_connector 1670 *connector) 1671 { 1672 int enc_id = connector->encoder_ids[0]; 1673 /* pick the encoder ids */ 1674 if (enc_id) 1675 return drm_encoder_find(connector->dev, NULL, enc_id); 1676 return NULL; 1677 } 1678 1679 static void mga_connector_destroy(struct drm_connector *connector) 1680 { 1681 struct mga_connector *mga_connector = to_mga_connector(connector); 1682 mgag200_i2c_destroy(mga_connector->i2c); 1683 drm_connector_cleanup(connector); 1684 kfree(connector); 1685 } 1686 1687 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { 1688 .get_modes = mga_vga_get_modes, 1689 .mode_valid = mga_vga_mode_valid, 1690 .best_encoder = mga_connector_best_encoder, 1691 }; 1692 1693 static const struct drm_connector_funcs mga_vga_connector_funcs = { 1694 .dpms = drm_helper_connector_dpms, 1695 .fill_modes = drm_helper_probe_single_connector_modes, 1696 .destroy = mga_connector_destroy, 1697 }; 1698 1699 static struct drm_connector *mga_vga_init(struct drm_device *dev) 1700 { 1701 struct drm_connector *connector; 1702 struct mga_connector *mga_connector; 1703 1704 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL); 1705 if (!mga_connector) 1706 return NULL; 1707 1708 connector = &mga_connector->base; 1709 1710 drm_connector_init(dev, connector, 1711 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA); 1712 1713 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); 1714 1715 drm_connector_register(connector); 1716 1717 mga_connector->i2c = mgag200_i2c_create(dev); 1718 if (!mga_connector->i2c) 1719 DRM_ERROR("failed to add ddc bus\n"); 1720 1721 return connector; 1722 } 1723 1724 1725 int mgag200_modeset_init(struct mga_device *mdev) 1726 { 1727 struct drm_encoder *encoder; 1728 struct drm_connector *connector; 1729 int ret; 1730 1731 mdev->mode_info.mode_config_initialized = true; 1732 1733 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 1734 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 1735 1736 mdev->dev->mode_config.fb_base = mdev->mc.vram_base; 1737 1738 mga_crtc_init(mdev); 1739 1740 encoder = mga_encoder_init(mdev->dev); 1741 if (!encoder) { 1742 DRM_ERROR("mga_encoder_init failed\n"); 1743 return -1; 1744 } 1745 1746 connector = mga_vga_init(mdev->dev); 1747 if (!connector) { 1748 DRM_ERROR("mga_vga_init failed\n"); 1749 return -1; 1750 } 1751 1752 drm_connector_attach_encoder(connector, encoder); 1753 1754 ret = mgag200_fbdev_init(mdev); 1755 if (ret) { 1756 DRM_ERROR("mga_fbdev_init failed\n"); 1757 return ret; 1758 } 1759 1760 return 0; 1761 } 1762 1763 void mgag200_modeset_fini(struct mga_device *mdev) 1764 { 1765 1766 } 1767