1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/iosys-map.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_atomic_state_helper.h> 16 #include <drm/drm_crtc_helper.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_format_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem_atomic_helper.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_print.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_simple_kms_helper.h> 26 27 #include "mgag200_drv.h" 28 29 #define MGAG200_LUT_SIZE 256 30 31 /* 32 * This file contains setup code for the CRTC. 33 */ 34 35 static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, 36 const struct drm_format_info *format) 37 { 38 int i; 39 40 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 41 42 switch (format->format) { 43 case DRM_FORMAT_RGB565: 44 /* Use better interpolation, to take 32 values from 0 to 255 */ 45 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 46 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 47 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 48 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 49 } 50 /* Green has one more bit, so add padding with 0 for red and blue. */ 51 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 52 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 53 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 54 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 55 } 56 break; 57 case DRM_FORMAT_RGB888: 58 case DRM_FORMAT_XRGB8888: 59 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 60 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 61 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 62 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 63 } 64 break; 65 default: 66 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 67 &format->format); 68 break; 69 } 70 } 71 72 static void mgag200_crtc_set_gamma(struct mga_device *mdev, 73 const struct drm_format_info *format, 74 struct drm_color_lut *lut) 75 { 76 int i; 77 78 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 79 80 switch (format->format) { 81 case DRM_FORMAT_RGB565: 82 /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ 83 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 84 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].red >> 8); 85 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 86 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].blue >> 8); 87 } 88 /* Green has one more bit, so add padding with 0 for red and blue. */ 89 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 90 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 91 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 92 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 93 } 94 break; 95 case DRM_FORMAT_RGB888: 96 case DRM_FORMAT_XRGB8888: 97 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 98 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].red >> 8); 99 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].green >> 8); 100 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].blue >> 8); 101 } 102 break; 103 default: 104 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 105 &format->format); 106 break; 107 } 108 } 109 110 static inline void mga_wait_vsync(struct mga_device *mdev) 111 { 112 unsigned long timeout = jiffies + HZ/10; 113 unsigned int status = 0; 114 115 do { 116 status = RREG32(MGAREG_Status); 117 } while ((status & 0x08) && time_before(jiffies, timeout)); 118 timeout = jiffies + HZ/10; 119 status = 0; 120 do { 121 status = RREG32(MGAREG_Status); 122 } while (!(status & 0x08) && time_before(jiffies, timeout)); 123 } 124 125 static inline void mga_wait_busy(struct mga_device *mdev) 126 { 127 unsigned long timeout = jiffies + HZ; 128 unsigned int status = 0; 129 do { 130 status = RREG8(MGAREG_Status + 2); 131 } while ((status & 0x01) && time_before(jiffies, timeout)); 132 } 133 134 static void mgag200_g200wb_hold_bmc(struct mga_device *mdev) 135 { 136 u8 tmp; 137 int iter_max; 138 139 /* 1- The first step is to warn the BMC of an upcoming mode change. 140 * We are putting the misc<0> to output.*/ 141 142 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); 143 tmp = RREG8(DAC_DATA); 144 tmp |= 0x10; 145 WREG_DAC(MGA1064_GEN_IO_CTL, tmp); 146 147 /* we are putting a 1 on the misc<0> line */ 148 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 149 tmp = RREG8(DAC_DATA); 150 tmp |= 0x10; 151 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 152 153 /* 2- Second step to mask and further scan request 154 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) 155 */ 156 WREG8(DAC_INDEX, MGA1064_SPAREREG); 157 tmp = RREG8(DAC_DATA); 158 tmp |= 0x80; 159 WREG_DAC(MGA1064_SPAREREG, tmp); 160 161 /* 3a- the third step is to verifu if there is an active scan 162 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) 163 */ 164 iter_max = 300; 165 while (!(tmp & 0x1) && iter_max) { 166 WREG8(DAC_INDEX, MGA1064_SPAREREG); 167 tmp = RREG8(DAC_DATA); 168 udelay(1000); 169 iter_max--; 170 } 171 172 /* 3b- this step occurs only if the remove is actually scanning 173 * we are waiting for the end of the frame which is a 1 on 174 * remvsyncsts (XSPAREREG<1>) 175 */ 176 if (iter_max) { 177 iter_max = 300; 178 while ((tmp & 0x2) && iter_max) { 179 WREG8(DAC_INDEX, MGA1064_SPAREREG); 180 tmp = RREG8(DAC_DATA); 181 udelay(1000); 182 iter_max--; 183 } 184 } 185 } 186 187 static void mgag200_g200wb_release_bmc(struct mga_device *mdev) 188 { 189 u8 tmp; 190 191 /* 1- The first step is to ensure that the vrsten and hrsten are set */ 192 WREG8(MGAREG_CRTCEXT_INDEX, 1); 193 tmp = RREG8(MGAREG_CRTCEXT_DATA); 194 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); 195 196 /* 2- second step is to assert the rstlvl2 */ 197 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 198 tmp = RREG8(DAC_DATA); 199 tmp |= 0x8; 200 WREG8(DAC_DATA, tmp); 201 202 /* wait 10 us */ 203 udelay(10); 204 205 /* 3- deassert rstlvl2 */ 206 tmp &= ~0x08; 207 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 208 WREG8(DAC_DATA, tmp); 209 210 /* 4- remove mask of scan request */ 211 WREG8(DAC_INDEX, MGA1064_SPAREREG); 212 tmp = RREG8(DAC_DATA); 213 tmp &= ~0x80; 214 WREG8(DAC_DATA, tmp); 215 216 /* 5- put back a 0 on the misc<0> line */ 217 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 218 tmp = RREG8(DAC_DATA); 219 tmp &= ~0x10; 220 WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 221 } 222 223 /* 224 * This is how the framebuffer base address is stored in g200 cards: 225 * * Assume @offset is the gpu_addr variable of the framebuffer object 226 * * Then addr is the number of _pixels_ (not bytes) from the start of 227 * VRAM to the first pixel we want to display. (divided by 2 for 32bit 228 * framebuffers) 229 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 230 * addr<20> -> CRTCEXT0<6> 231 * addr<19-16> -> CRTCEXT0<3-0> 232 * addr<15-8> -> CRTCC<7-0> 233 * addr<7-0> -> CRTCD<7-0> 234 * 235 * CRTCEXT0 has to be programmed last to trigger an update and make the 236 * new addr variable take effect. 237 */ 238 static void mgag200_set_startadd(struct mga_device *mdev, 239 unsigned long offset) 240 { 241 struct drm_device *dev = &mdev->base; 242 u32 startadd; 243 u8 crtcc, crtcd, crtcext0; 244 245 startadd = offset / 8; 246 247 if (startadd > 0) 248 drm_WARN_ON_ONCE(dev, mdev->info->bug_no_startadd); 249 250 /* 251 * Can't store addresses any higher than that, but we also 252 * don't have more than 16 MiB of memory, so it should be fine. 253 */ 254 drm_WARN_ON(dev, startadd > 0x1fffff); 255 256 RREG_ECRT(0x00, crtcext0); 257 258 crtcc = (startadd >> 8) & 0xff; 259 crtcd = startadd & 0xff; 260 crtcext0 &= 0xb0; 261 crtcext0 |= ((startadd >> 14) & BIT(6)) | 262 ((startadd >> 16) & 0x0f); 263 264 WREG_CRT(0x0c, crtcc); 265 WREG_CRT(0x0d, crtcd); 266 WREG_ECRT(0x00, crtcext0); 267 } 268 269 static void mgag200_set_dac_regs(struct mga_device *mdev) 270 { 271 size_t i; 272 u8 dacvalue[] = { 273 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, 274 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, 275 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, 276 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, 277 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 278 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, 279 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, 280 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, 281 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, 282 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 283 }; 284 285 switch (mdev->type) { 286 case G200_PCI: 287 case G200_AGP: 288 dacvalue[MGA1064_SYS_PLL_M] = 0x04; 289 dacvalue[MGA1064_SYS_PLL_N] = 0x2D; 290 dacvalue[MGA1064_SYS_PLL_P] = 0x19; 291 break; 292 case G200_SE_A: 293 case G200_SE_B: 294 dacvalue[MGA1064_VREF_CTL] = 0x03; 295 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 296 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | 297 MGA1064_MISC_CTL_VGA8 | 298 MGA1064_MISC_CTL_DAC_RAM_CS; 299 break; 300 case G200_WB: 301 case G200_EW3: 302 dacvalue[MGA1064_VREF_CTL] = 0x07; 303 break; 304 case G200_EV: 305 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 306 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 307 MGA1064_MISC_CTL_DAC_RAM_CS; 308 break; 309 case G200_EH: 310 case G200_EH3: 311 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 312 MGA1064_MISC_CTL_DAC_RAM_CS; 313 break; 314 case G200_ER: 315 break; 316 } 317 318 for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { 319 if ((i <= 0x17) || 320 (i == 0x1b) || 321 (i == 0x1c) || 322 ((i >= 0x1f) && (i <= 0x29)) || 323 ((i >= 0x30) && (i <= 0x37))) 324 continue; 325 if (IS_G200_SE(mdev) && 326 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) 327 continue; 328 if ((mdev->type == G200_EV || 329 mdev->type == G200_WB || 330 mdev->type == G200_EH || 331 mdev->type == G200_EW3 || 332 mdev->type == G200_EH3) && 333 (i >= 0x44) && (i <= 0x4e)) 334 continue; 335 336 WREG_DAC(i, dacvalue[i]); 337 } 338 339 if (mdev->type == G200_ER) 340 WREG_DAC(0x90, 0); 341 } 342 343 static void mgag200_init_regs(struct mga_device *mdev) 344 { 345 u8 crtc11, misc; 346 347 mgag200_set_dac_regs(mdev); 348 349 WREG_SEQ(2, 0x0f); 350 WREG_SEQ(3, 0x00); 351 WREG_SEQ(4, 0x0e); 352 353 WREG_CRT(10, 0); 354 WREG_CRT(11, 0); 355 WREG_CRT(12, 0); 356 WREG_CRT(13, 0); 357 WREG_CRT(14, 0); 358 WREG_CRT(15, 0); 359 360 RREG_CRT(0x11, crtc11); 361 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | 362 MGAREG_CRTC11_VINTEN | 363 MGAREG_CRTC11_VINTCLR); 364 WREG_CRT(0x11, crtc11); 365 366 if (mdev->type == G200_ER) 367 WREG_ECRT(0x24, 0x5); 368 369 if (mdev->type == G200_EW3) 370 WREG_ECRT(0x34, 0x5); 371 372 misc = RREG8(MGA_MISC_IN); 373 misc |= MGAREG_MISC_IOADSEL; 374 WREG8(MGA_MISC_OUT, misc); 375 } 376 377 static void mgag200_set_mode_regs(struct mga_device *mdev, 378 const struct drm_display_mode *mode) 379 { 380 const struct mgag200_device_info *info = mdev->info; 381 unsigned int hdisplay, hsyncstart, hsyncend, htotal; 382 unsigned int vdisplay, vsyncstart, vsyncend, vtotal; 383 u8 misc, crtcext1, crtcext2, crtcext5; 384 385 hdisplay = mode->hdisplay / 8 - 1; 386 hsyncstart = mode->hsync_start / 8 - 1; 387 hsyncend = mode->hsync_end / 8 - 1; 388 htotal = mode->htotal / 8 - 1; 389 390 /* Work around hardware quirk */ 391 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 392 htotal++; 393 394 vdisplay = mode->vdisplay - 1; 395 vsyncstart = mode->vsync_start - 1; 396 vsyncend = mode->vsync_end - 1; 397 vtotal = mode->vtotal - 2; 398 399 misc = RREG8(MGA_MISC_IN); 400 401 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 402 misc |= MGAREG_MISC_HSYNCPOL; 403 else 404 misc &= ~MGAREG_MISC_HSYNCPOL; 405 406 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 407 misc |= MGAREG_MISC_VSYNCPOL; 408 else 409 misc &= ~MGAREG_MISC_VSYNCPOL; 410 411 crtcext1 = (((htotal - 4) & 0x100) >> 8) | 412 ((hdisplay & 0x100) >> 7) | 413 ((hsyncstart & 0x100) >> 6) | 414 (htotal & 0x40); 415 if (info->has_vidrst) 416 crtcext1 |= MGAREG_CRTCEXT1_VRSTEN | 417 MGAREG_CRTCEXT1_HRSTEN; 418 419 crtcext2 = ((vtotal & 0xc00) >> 10) | 420 ((vdisplay & 0x400) >> 8) | 421 ((vdisplay & 0xc00) >> 7) | 422 ((vsyncstart & 0xc00) >> 5) | 423 ((vdisplay & 0x400) >> 3); 424 crtcext5 = 0x00; 425 426 WREG_CRT(0, htotal - 4); 427 WREG_CRT(1, hdisplay); 428 WREG_CRT(2, hdisplay); 429 WREG_CRT(3, (htotal & 0x1F) | 0x80); 430 WREG_CRT(4, hsyncstart); 431 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 432 WREG_CRT(6, vtotal & 0xFF); 433 WREG_CRT(7, ((vtotal & 0x100) >> 8) | 434 ((vdisplay & 0x100) >> 7) | 435 ((vsyncstart & 0x100) >> 6) | 436 ((vdisplay & 0x100) >> 5) | 437 ((vdisplay & 0x100) >> 4) | /* linecomp */ 438 ((vtotal & 0x200) >> 4) | 439 ((vdisplay & 0x200) >> 3) | 440 ((vsyncstart & 0x200) >> 2)); 441 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 442 ((vdisplay & 0x200) >> 3)); 443 WREG_CRT(16, vsyncstart & 0xFF); 444 WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 445 WREG_CRT(18, vdisplay & 0xFF); 446 WREG_CRT(20, 0); 447 WREG_CRT(21, vdisplay & 0xFF); 448 WREG_CRT(22, (vtotal + 1) & 0xFF); 449 WREG_CRT(23, 0xc3); 450 WREG_CRT(24, vdisplay & 0xFF); 451 452 WREG_ECRT(0x01, crtcext1); 453 WREG_ECRT(0x02, crtcext2); 454 WREG_ECRT(0x05, crtcext5); 455 456 WREG8(MGA_MISC_OUT, misc); 457 } 458 459 static u8 mgag200_get_bpp_shift(const struct drm_format_info *format) 460 { 461 static const u8 bpp_shift[] = {0, 1, 0, 2}; 462 463 return bpp_shift[format->cpp[0] - 1]; 464 } 465 466 /* 467 * Calculates the HW offset value from the framebuffer's pitch. The 468 * offset is a multiple of the pixel size and depends on the display 469 * format. 470 */ 471 static u32 mgag200_calculate_offset(struct mga_device *mdev, 472 const struct drm_framebuffer *fb) 473 { 474 u32 offset = fb->pitches[0] / fb->format->cpp[0]; 475 u8 bppshift = mgag200_get_bpp_shift(fb->format); 476 477 if (fb->format->cpp[0] * 8 == 24) 478 offset = (offset * 3) >> (4 - bppshift); 479 else 480 offset = offset >> (4 - bppshift); 481 482 return offset; 483 } 484 485 static void mgag200_set_offset(struct mga_device *mdev, 486 const struct drm_framebuffer *fb) 487 { 488 u8 crtc13, crtcext0; 489 u32 offset = mgag200_calculate_offset(mdev, fb); 490 491 RREG_ECRT(0, crtcext0); 492 493 crtc13 = offset & 0xff; 494 495 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK; 496 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK; 497 498 WREG_CRT(0x13, crtc13); 499 WREG_ECRT(0x00, crtcext0); 500 } 501 502 static void mgag200_set_format_regs(struct mga_device *mdev, 503 const struct drm_framebuffer *fb) 504 { 505 struct drm_device *dev = &mdev->base; 506 const struct drm_format_info *format = fb->format; 507 unsigned int bpp, bppshift, scale; 508 u8 crtcext3, xmulctrl; 509 510 bpp = format->cpp[0] * 8; 511 512 bppshift = mgag200_get_bpp_shift(format); 513 switch (bpp) { 514 case 24: 515 scale = ((1 << bppshift) * 3) - 1; 516 break; 517 default: 518 scale = (1 << bppshift) - 1; 519 break; 520 } 521 522 RREG_ECRT(3, crtcext3); 523 524 switch (bpp) { 525 case 8: 526 xmulctrl = MGA1064_MUL_CTL_8bits; 527 break; 528 case 16: 529 if (format->depth == 15) 530 xmulctrl = MGA1064_MUL_CTL_15bits; 531 else 532 xmulctrl = MGA1064_MUL_CTL_16bits; 533 break; 534 case 24: 535 xmulctrl = MGA1064_MUL_CTL_24bits; 536 break; 537 case 32: 538 xmulctrl = MGA1064_MUL_CTL_32_24bits; 539 break; 540 default: 541 /* BUG: We should have caught this problem already. */ 542 drm_WARN_ON(dev, "invalid format depth\n"); 543 return; 544 } 545 546 crtcext3 &= ~GENMASK(2, 0); 547 crtcext3 |= scale; 548 549 WREG_DAC(MGA1064_MUL_CTL, xmulctrl); 550 551 WREG_GFX(0, 0x00); 552 WREG_GFX(1, 0x00); 553 WREG_GFX(2, 0x00); 554 WREG_GFX(3, 0x00); 555 WREG_GFX(4, 0x00); 556 WREG_GFX(5, 0x40); 557 /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode), 558 * so that it doesn't hang when running kexec/kdump on G200_SE rev42. 559 */ 560 WREG_GFX(6, 0x0d); 561 WREG_GFX(7, 0x0f); 562 WREG_GFX(8, 0x0f); 563 564 WREG_ECRT(3, crtcext3); 565 } 566 567 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev) 568 { 569 static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */ 570 u32 memctl; 571 572 memctl = RREG32(MGAREG_MEMCTL); 573 574 memctl |= RESET_FLAG; 575 WREG32(MGAREG_MEMCTL, memctl); 576 577 udelay(1000); 578 579 memctl &= ~RESET_FLAG; 580 WREG32(MGAREG_MEMCTL, memctl); 581 } 582 583 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev, 584 const struct drm_display_mode *mode, 585 const struct drm_framebuffer *fb) 586 { 587 struct mgag200_g200se_device *g200se = to_mgag200_g200se_device(&mdev->base); 588 unsigned int hiprilvl; 589 u8 crtcext6; 590 591 if (g200se->unique_rev_id >= 0x04) { 592 hiprilvl = 0; 593 } else if (g200se->unique_rev_id >= 0x02) { 594 unsigned int bpp; 595 unsigned long mb; 596 597 if (fb->format->cpp[0] * 8 > 16) 598 bpp = 32; 599 else if (fb->format->cpp[0] * 8 > 8) 600 bpp = 16; 601 else 602 bpp = 8; 603 604 mb = (mode->clock * bpp) / 1000; 605 if (mb > 3100) 606 hiprilvl = 0; 607 else if (mb > 2600) 608 hiprilvl = 1; 609 else if (mb > 1900) 610 hiprilvl = 2; 611 else if (mb > 1160) 612 hiprilvl = 3; 613 else if (mb > 440) 614 hiprilvl = 4; 615 else 616 hiprilvl = 5; 617 618 } else if (g200se->unique_rev_id >= 0x01) { 619 hiprilvl = 3; 620 } else { 621 hiprilvl = 4; 622 } 623 624 crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */ 625 626 WREG_ECRT(0x06, crtcext6); 627 } 628 629 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev) 630 { 631 WREG_ECRT(0x06, 0x00); 632 } 633 634 static void mgag200_enable_display(struct mga_device *mdev) 635 { 636 u8 seq0, seq1, crtcext1; 637 638 RREG_SEQ(0x00, seq0); 639 seq0 |= MGAREG_SEQ0_SYNCRST | 640 MGAREG_SEQ0_ASYNCRST; 641 WREG_SEQ(0x00, seq0); 642 643 /* 644 * TODO: replace busy waiting with vblank IRQ; put 645 * msleep(50) before changing SCROFF 646 */ 647 mga_wait_vsync(mdev); 648 mga_wait_busy(mdev); 649 650 RREG_SEQ(0x01, seq1); 651 seq1 &= ~MGAREG_SEQ1_SCROFF; 652 WREG_SEQ(0x01, seq1); 653 654 msleep(20); 655 656 RREG_ECRT(0x01, crtcext1); 657 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF; 658 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF; 659 WREG_ECRT(0x01, crtcext1); 660 } 661 662 static void mgag200_disable_display(struct mga_device *mdev) 663 { 664 u8 seq0, seq1, crtcext1; 665 666 RREG_SEQ(0x00, seq0); 667 seq0 &= ~MGAREG_SEQ0_SYNCRST; 668 WREG_SEQ(0x00, seq0); 669 670 /* 671 * TODO: replace busy waiting with vblank IRQ; put 672 * msleep(50) before changing SCROFF 673 */ 674 mga_wait_vsync(mdev); 675 mga_wait_busy(mdev); 676 677 RREG_SEQ(0x01, seq1); 678 seq1 |= MGAREG_SEQ1_SCROFF; 679 WREG_SEQ(0x01, seq1); 680 681 msleep(20); 682 683 RREG_ECRT(0x01, crtcext1); 684 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF | 685 MGAREG_CRTCEXT1_HSYNCOFF; 686 WREG_ECRT(0x01, crtcext1); 687 } 688 689 /* 690 * Connector 691 */ 692 693 static int mgag200_vga_connector_helper_get_modes(struct drm_connector *connector) 694 { 695 struct mga_device *mdev = to_mga_device(connector->dev); 696 int ret; 697 698 /* 699 * Protect access to I/O registers from concurrent modesetting 700 * by acquiring the I/O-register lock. 701 */ 702 mutex_lock(&mdev->rmmio_lock); 703 ret = drm_connector_helper_get_modes_from_ddc(connector); 704 mutex_unlock(&mdev->rmmio_lock); 705 706 return ret; 707 } 708 709 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { 710 .get_modes = mgag200_vga_connector_helper_get_modes, 711 }; 712 713 static const struct drm_connector_funcs mga_vga_connector_funcs = { 714 .reset = drm_atomic_helper_connector_reset, 715 .fill_modes = drm_helper_probe_single_connector_modes, 716 .destroy = drm_connector_cleanup, 717 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 718 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 719 }; 720 721 /* 722 * Simple Display Pipe 723 */ 724 725 static enum drm_mode_status 726 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 727 const struct drm_display_mode *mode) 728 { 729 struct mga_device *mdev = to_mga_device(pipe->crtc.dev); 730 const struct mgag200_device_info *info = mdev->info; 731 732 /* 733 * Some devices have additional limits on the size of the 734 * display mode. 735 */ 736 if (mode->hdisplay > info->max_hdisplay) 737 return MODE_VIRTUAL_X; 738 if (mode->vdisplay > info->max_vdisplay) 739 return MODE_VIRTUAL_Y; 740 741 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 742 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 743 return MODE_H_ILLEGAL; 744 } 745 746 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 747 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 748 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 749 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 750 return MODE_BAD; 751 } 752 753 return MODE_OK; 754 } 755 756 static void 757 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb, 758 struct drm_rect *clip, const struct iosys_map *map) 759 { 760 void __iomem *dst = mdev->vram; 761 void *vmap = map->vaddr; /* TODO: Use mapping abstraction properly */ 762 763 dst += drm_fb_clip_offset(fb->pitches[0], fb->format, clip); 764 drm_fb_memcpy_toio(dst, fb->pitches[0], vmap, fb, clip); 765 } 766 767 static void 768 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe, 769 struct drm_crtc_state *crtc_state, 770 struct drm_plane_state *plane_state) 771 { 772 struct drm_crtc *crtc = &pipe->crtc; 773 struct drm_device *dev = crtc->dev; 774 struct mga_device *mdev = to_mga_device(dev); 775 struct mgag200_pll *pixpll = &mdev->pixpll; 776 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 777 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 778 struct drm_framebuffer *fb = plane_state->fb; 779 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 780 struct drm_rect fullscreen = { 781 .x1 = 0, 782 .x2 = fb->width, 783 .y1 = 0, 784 .y2 = fb->height, 785 }; 786 787 /* 788 * Concurrent operations could possibly trigger a call to 789 * drm_connector_helper_funcs.get_modes by trying to read the 790 * display modes. Protect access to I/O registers by acquiring 791 * the I/O-register lock. 792 */ 793 mutex_lock(&mdev->rmmio_lock); 794 795 if (mdev->type == G200_WB || mdev->type == G200_EW3) 796 mgag200_g200wb_hold_bmc(mdev); 797 798 mgag200_set_format_regs(mdev, fb); 799 mgag200_set_mode_regs(mdev, adjusted_mode); 800 801 pixpll->funcs->update(pixpll, &mgag200_crtc_state->pixpllc); 802 803 if (mdev->type == G200_ER) 804 mgag200_g200er_reset_tagfifo(mdev); 805 806 if (IS_G200_SE(mdev)) 807 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb); 808 else if (mdev->type == G200_EV) 809 mgag200_g200ev_set_hiprilvl(mdev); 810 811 if (mdev->type == G200_WB || mdev->type == G200_EW3) 812 mgag200_g200wb_release_bmc(mdev); 813 814 if (crtc_state->gamma_lut) 815 mgag200_crtc_set_gamma(mdev, fb->format, crtc_state->gamma_lut->data); 816 else 817 mgag200_crtc_set_gamma_linear(mdev, fb->format); 818 819 mgag200_enable_display(mdev); 820 821 mgag200_handle_damage(mdev, fb, &fullscreen, &shadow_plane_state->data[0]); 822 823 /* Always scanout image at VRAM offset 0 */ 824 mgag200_set_startadd(mdev, (u32)0); 825 mgag200_set_offset(mdev, fb); 826 827 mutex_unlock(&mdev->rmmio_lock); 828 } 829 830 static void 831 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe) 832 { 833 struct drm_crtc *crtc = &pipe->crtc; 834 struct mga_device *mdev = to_mga_device(crtc->dev); 835 836 mgag200_disable_display(mdev); 837 } 838 839 static int 840 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe, 841 struct drm_plane_state *plane_state, 842 struct drm_crtc_state *crtc_state) 843 { 844 struct drm_plane *plane = plane_state->plane; 845 struct drm_device *dev = plane->dev; 846 struct mga_device *mdev = to_mga_device(dev); 847 struct mgag200_pll *pixpll = &mdev->pixpll; 848 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 849 struct drm_framebuffer *new_fb = plane_state->fb; 850 struct drm_framebuffer *fb = NULL; 851 int ret; 852 853 if (!new_fb) 854 return 0; 855 856 if (plane->state) 857 fb = plane->state->fb; 858 859 if (!fb || (fb->format != new_fb->format)) 860 crtc_state->mode_changed = true; /* update PLL settings */ 861 862 if (crtc_state->mode_changed) { 863 ret = pixpll->funcs->compute(pixpll, crtc_state->mode.clock, 864 &mgag200_crtc_state->pixpllc); 865 if (ret) 866 return ret; 867 } 868 869 if (crtc_state->color_mgmt_changed && crtc_state->gamma_lut) { 870 if (crtc_state->gamma_lut->length != 871 MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) { 872 drm_err(dev, "Wrong size for gamma_lut %zu\n", 873 crtc_state->gamma_lut->length); 874 return -EINVAL; 875 } 876 } 877 return 0; 878 } 879 880 static void 881 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe, 882 struct drm_plane_state *old_state) 883 { 884 struct drm_plane *plane = &pipe->plane; 885 struct drm_crtc *crtc = &pipe->crtc; 886 struct drm_device *dev = plane->dev; 887 struct mga_device *mdev = to_mga_device(dev); 888 struct drm_plane_state *state = plane->state; 889 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state); 890 struct drm_framebuffer *fb = state->fb; 891 struct drm_rect damage; 892 struct drm_atomic_helper_damage_iter iter; 893 894 if (!fb) 895 return; 896 897 mutex_lock(&mdev->rmmio_lock); 898 899 if (crtc->state->color_mgmt_changed && crtc->state->gamma_lut) 900 mgag200_crtc_set_gamma(mdev, fb->format, crtc->state->gamma_lut->data); 901 902 drm_atomic_helper_damage_iter_init(&iter, old_state, state); 903 drm_atomic_for_each_plane_damage(&iter, &damage) { 904 mgag200_handle_damage(mdev, fb, &damage, &shadow_plane_state->data[0]); 905 } 906 /* Always scanout image at VRAM offset 0 */ 907 mgag200_set_startadd(mdev, (u32)0); 908 mgag200_set_offset(mdev, fb); 909 910 mutex_unlock(&mdev->rmmio_lock); 911 } 912 913 static struct drm_crtc_state * 914 mgag200_simple_display_pipe_duplicate_crtc_state(struct drm_simple_display_pipe *pipe) 915 { 916 struct drm_crtc *crtc = &pipe->crtc; 917 struct drm_crtc_state *crtc_state = crtc->state; 918 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 919 struct mgag200_crtc_state *new_mgag200_crtc_state; 920 921 if (!crtc_state) 922 return NULL; 923 924 new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL); 925 if (!new_mgag200_crtc_state) 926 return NULL; 927 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base); 928 929 memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc, 930 sizeof(new_mgag200_crtc_state->pixpllc)); 931 932 return &new_mgag200_crtc_state->base; 933 } 934 935 static void mgag200_simple_display_pipe_destroy_crtc_state(struct drm_simple_display_pipe *pipe, 936 struct drm_crtc_state *crtc_state) 937 { 938 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 939 940 __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base); 941 kfree(mgag200_crtc_state); 942 } 943 944 static void mgag200_simple_display_pipe_reset_crtc(struct drm_simple_display_pipe *pipe) 945 { 946 struct drm_crtc *crtc = &pipe->crtc; 947 struct mgag200_crtc_state *mgag200_crtc_state; 948 949 if (crtc->state) { 950 mgag200_simple_display_pipe_destroy_crtc_state(pipe, crtc->state); 951 crtc->state = NULL; /* must be set to NULL here */ 952 } 953 954 mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL); 955 if (!mgag200_crtc_state) 956 return; 957 __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base); 958 } 959 960 static const struct drm_simple_display_pipe_funcs 961 mgag200_simple_display_pipe_funcs = { 962 .mode_valid = mgag200_simple_display_pipe_mode_valid, 963 .enable = mgag200_simple_display_pipe_enable, 964 .disable = mgag200_simple_display_pipe_disable, 965 .check = mgag200_simple_display_pipe_check, 966 .update = mgag200_simple_display_pipe_update, 967 .reset_crtc = mgag200_simple_display_pipe_reset_crtc, 968 .duplicate_crtc_state = mgag200_simple_display_pipe_duplicate_crtc_state, 969 .destroy_crtc_state = mgag200_simple_display_pipe_destroy_crtc_state, 970 DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS, 971 }; 972 973 static const uint32_t mgag200_simple_display_pipe_formats[] = { 974 DRM_FORMAT_XRGB8888, 975 DRM_FORMAT_RGB565, 976 DRM_FORMAT_RGB888, 977 }; 978 979 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = { 980 DRM_FORMAT_MOD_LINEAR, 981 DRM_FORMAT_MOD_INVALID 982 }; 983 984 /* 985 * Mode config 986 */ 987 988 /* Calculates a mode's required memory bandwidth (in KiB/sec). */ 989 static uint32_t mgag200_calculate_mode_bandwidth(const struct drm_display_mode *mode, 990 unsigned int bits_per_pixel) 991 { 992 uint32_t total_area, divisor; 993 uint64_t active_area, pixels_per_second, bandwidth; 994 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 995 996 divisor = 1024; 997 998 if (!mode->htotal || !mode->vtotal || !mode->clock) 999 return 0; 1000 1001 active_area = mode->hdisplay * mode->vdisplay; 1002 total_area = mode->htotal * mode->vtotal; 1003 1004 pixels_per_second = active_area * mode->clock * 1000; 1005 do_div(pixels_per_second, total_area); 1006 1007 bandwidth = pixels_per_second * bytes_per_pixel * 100; 1008 do_div(bandwidth, divisor); 1009 1010 return (uint32_t)bandwidth; 1011 } 1012 1013 static enum drm_mode_status mgag200_mode_config_mode_valid(struct drm_device *dev, 1014 const struct drm_display_mode *mode) 1015 { 1016 static const unsigned int max_bpp = 4; // DRM_FORMAT_XRGB8888 1017 struct mga_device *mdev = to_mga_device(dev); 1018 unsigned long fbsize, fbpages, max_fbpages; 1019 const struct mgag200_device_info *info = mdev->info; 1020 1021 max_fbpages = mdev->vram_available >> PAGE_SHIFT; 1022 1023 fbsize = mode->hdisplay * mode->vdisplay * max_bpp; 1024 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); 1025 1026 if (fbpages > max_fbpages) 1027 return MODE_MEM; 1028 1029 /* 1030 * Test the mode's required memory bandwidth if the device 1031 * specifies a maximum. Not all devices do though. 1032 */ 1033 if (info->max_mem_bandwidth) { 1034 uint32_t mode_bandwidth = mgag200_calculate_mode_bandwidth(mode, max_bpp * 8); 1035 1036 if (mode_bandwidth > (info->max_mem_bandwidth * 1024)) 1037 return MODE_BAD; 1038 } 1039 1040 return MODE_OK; 1041 } 1042 1043 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = { 1044 .fb_create = drm_gem_fb_create_with_dirty, 1045 .mode_valid = mgag200_mode_config_mode_valid, 1046 .atomic_check = drm_atomic_helper_check, 1047 .atomic_commit = drm_atomic_helper_commit, 1048 }; 1049 1050 int mgag200_modeset_init(struct mga_device *mdev, resource_size_t vram_available) 1051 { 1052 struct drm_device *dev = &mdev->base; 1053 struct mga_i2c_chan *i2c = &mdev->i2c; 1054 struct drm_connector *connector = &mdev->connector; 1055 struct drm_simple_display_pipe *pipe = &mdev->display_pipe; 1056 size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats); 1057 int ret; 1058 1059 mgag200_init_regs(mdev); 1060 1061 mdev->vram_available = vram_available; 1062 1063 ret = drmm_mode_config_init(dev); 1064 if (ret) { 1065 drm_err(dev, "drmm_mode_config_init() failed, error %d\n", 1066 ret); 1067 return ret; 1068 } 1069 1070 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 1071 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 1072 dev->mode_config.preferred_depth = 24; 1073 dev->mode_config.fb_base = mdev->vram_res->start; 1074 dev->mode_config.funcs = &mgag200_mode_config_funcs; 1075 1076 ret = mgag200_i2c_init(mdev, i2c); 1077 if (ret) { 1078 drm_err(dev, "failed to add DDC bus: %d\n", ret); 1079 return ret; 1080 } 1081 1082 ret = drm_connector_init_with_ddc(dev, connector, 1083 &mga_vga_connector_funcs, 1084 DRM_MODE_CONNECTOR_VGA, 1085 &i2c->adapter); 1086 if (ret) { 1087 drm_err(dev, "drm_connector_init_with_ddc() failed: %d\n", ret); 1088 return ret; 1089 } 1090 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); 1091 1092 ret = mgag200_pixpll_init(&mdev->pixpll, mdev); 1093 if (ret) 1094 return ret; 1095 1096 ret = drm_simple_display_pipe_init(dev, pipe, 1097 &mgag200_simple_display_pipe_funcs, 1098 mgag200_simple_display_pipe_formats, 1099 format_count, 1100 mgag200_simple_display_pipe_fmtmods, 1101 connector); 1102 if (ret) { 1103 drm_err(dev, 1104 "drm_simple_display_pipe_init() failed, error %d\n", 1105 ret); 1106 return ret; 1107 } 1108 1109 drm_plane_enable_fb_damage_clips(&pipe->plane); 1110 1111 /* FIXME: legacy gamma tables, but atomic gamma doesn't work without */ 1112 drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE); 1113 1114 drm_crtc_enable_color_mgmt(&pipe->crtc, 0, false, MGAG200_LUT_SIZE); 1115 1116 drm_mode_config_reset(dev); 1117 1118 return 0; 1119 } 1120