1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright 2010 Matt Turner.
4  * Copyright 2012 Red Hat
5  *
6  * Authors: Matthew Garrett
7  * 	    Matt Turner
8  *	    Dave Airlie
9  */
10 #ifndef __MGAG200_DRV_H__
11 #define __MGAG200_DRV_H__
12 
13 #include <linux/i2c-algo-bit.h>
14 #include <linux/i2c.h>
15 
16 #include <video/vga.h>
17 
18 #include <drm/drm_encoder.h>
19 #include <drm/drm_fb_helper.h>
20 #include <drm/drm_gem.h>
21 #include <drm/drm_gem_shmem_helper.h>
22 #include <drm/drm_simple_kms_helper.h>
23 
24 #include "mgag200_reg.h"
25 
26 #define DRIVER_AUTHOR		"Matthew Garrett"
27 
28 #define DRIVER_NAME		"mgag200"
29 #define DRIVER_DESC		"MGA G200 SE"
30 #define DRIVER_DATE		"20110418"
31 
32 #define DRIVER_MAJOR		1
33 #define DRIVER_MINOR		0
34 #define DRIVER_PATCHLEVEL	0
35 
36 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg))
37 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
38 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg))
39 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
40 
41 #define ATTR_INDEX 0x1fc0
42 #define ATTR_DATA 0x1fc1
43 
44 #define WREG_ATTR(reg, v)					\
45 	do {							\
46 		RREG8(0x1fda);					\
47 		WREG8(ATTR_INDEX, reg);				\
48 		WREG8(ATTR_DATA, v);				\
49 	} while (0)						\
50 
51 #define RREG_SEQ(reg, v)					\
52 	do {							\
53 		WREG8(MGAREG_SEQ_INDEX, reg);			\
54 		v = RREG8(MGAREG_SEQ_DATA);			\
55 	} while (0)						\
56 
57 #define WREG_SEQ(reg, v)					\
58 	do {							\
59 		WREG8(MGAREG_SEQ_INDEX, reg);			\
60 		WREG8(MGAREG_SEQ_DATA, v);			\
61 	} while (0)						\
62 
63 #define RREG_CRT(reg, v)					\
64 	do {							\
65 		WREG8(MGAREG_CRTC_INDEX, reg);			\
66 		v = RREG8(MGAREG_CRTC_DATA);			\
67 	} while (0)						\
68 
69 #define WREG_CRT(reg, v)					\
70 	do {							\
71 		WREG8(MGAREG_CRTC_INDEX, reg);			\
72 		WREG8(MGAREG_CRTC_DATA, v);			\
73 	} while (0)						\
74 
75 #define RREG_ECRT(reg, v)					\
76 	do {							\
77 		WREG8(MGAREG_CRTCEXT_INDEX, reg);		\
78 		v = RREG8(MGAREG_CRTCEXT_DATA);			\
79 	} while (0)						\
80 
81 #define WREG_ECRT(reg, v)					\
82 	do {							\
83 		WREG8(MGAREG_CRTCEXT_INDEX, reg);				\
84 		WREG8(MGAREG_CRTCEXT_DATA, v);				\
85 	} while (0)						\
86 
87 #define GFX_INDEX 0x1fce
88 #define GFX_DATA 0x1fcf
89 
90 #define WREG_GFX(reg, v)					\
91 	do {							\
92 		WREG8(GFX_INDEX, reg);				\
93 		WREG8(GFX_DATA, v);				\
94 	} while (0)						\
95 
96 #define DAC_INDEX 0x3c00
97 #define DAC_DATA 0x3c0a
98 
99 #define WREG_DAC(reg, v)					\
100 	do {							\
101 		WREG8(DAC_INDEX, reg);				\
102 		WREG8(DAC_DATA, v);				\
103 	} while (0)						\
104 
105 #define MGA_MISC_OUT 0x1fc2
106 #define MGA_MISC_IN 0x1fcc
107 
108 #define MGAG200_MAX_FB_HEIGHT 4096
109 #define MGAG200_MAX_FB_WIDTH 4096
110 
111 #define to_mga_connector(x) container_of(x, struct mga_connector, base)
112 
113 struct mga_i2c_chan {
114 	struct i2c_adapter adapter;
115 	struct drm_device *dev;
116 	struct i2c_algo_bit_data bit;
117 	int data, clock;
118 };
119 
120 struct mga_connector {
121 	struct drm_connector base;
122 	struct mga_i2c_chan *i2c;
123 };
124 
125 struct mga_mc {
126 	resource_size_t			vram_size;
127 	resource_size_t			vram_base;
128 	resource_size_t			vram_window;
129 };
130 
131 enum mga_type {
132 	G200_SE_A,
133 	G200_SE_B,
134 	G200_WB,
135 	G200_EV,
136 	G200_EH,
137 	G200_EH3,
138 	G200_ER,
139 	G200_EW3,
140 };
141 
142 /* HW does not handle 'startadd' field correct. */
143 #define MGAG200_FLAG_HW_BUG_NO_STARTADD	(1ul << 8)
144 
145 #define MGAG200_TYPE_MASK	(0x000000ff)
146 #define MGAG200_FLAG_MASK	(0x00ffff00)
147 
148 #define IS_G200_SE(mdev) (mdev->type == G200_SE_A || mdev->type == G200_SE_B)
149 
150 struct mga_device {
151 	struct drm_device		base;
152 	unsigned long			flags;
153 
154 	resource_size_t			rmmio_base;
155 	resource_size_t			rmmio_size;
156 	void __iomem			*rmmio;
157 
158 	struct mga_mc			mc;
159 
160 	void __iomem			*vram;
161 	size_t				vram_fb_available;
162 
163 	enum mga_type			type;
164 	int				has_sdram;
165 
166 	int bpp_shifts[4];
167 
168 	int fb_mtrr;
169 
170 	/* SE model number stored in reg 0x1e24 */
171 	u32 unique_rev_id;
172 
173 	struct mga_connector connector;
174 	struct drm_simple_display_pipe display_pipe;
175 };
176 
177 static inline struct mga_device *to_mga_device(struct drm_device *dev)
178 {
179 	return container_of(dev, struct mga_device, base);
180 }
181 
182 static inline enum mga_type
183 mgag200_type_from_driver_data(kernel_ulong_t driver_data)
184 {
185 	return (enum mga_type)(driver_data & MGAG200_TYPE_MASK);
186 }
187 
188 static inline unsigned long
189 mgag200_flags_from_driver_data(kernel_ulong_t driver_data)
190 {
191 	return driver_data & MGAG200_FLAG_MASK;
192 }
193 
194 				/* mgag200_mode.c */
195 int mgag200_modeset_init(struct mga_device *mdev);
196 
197 				/* mgag200_i2c.c */
198 struct mga_i2c_chan *mgag200_i2c_create(struct drm_device *dev);
199 void mgag200_i2c_destroy(struct mga_i2c_chan *i2c);
200 
201 				/* mgag200_mm.c */
202 int mgag200_mm_init(struct mga_device *mdev);
203 
204 #endif				/* __MGAG200_DRV_H__ */
205