1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 #ifndef __MGAG200_DRV_H__ 11 #define __MGAG200_DRV_H__ 12 13 #include <linux/i2c-algo-bit.h> 14 #include <linux/i2c.h> 15 16 #include <video/vga.h> 17 18 #include <drm/drm_connector.h> 19 #include <drm/drm_crtc.h> 20 #include <drm/drm_encoder.h> 21 #include <drm/drm_fb_helper.h> 22 #include <drm/drm_gem.h> 23 #include <drm/drm_gem_shmem_helper.h> 24 #include <drm/drm_plane.h> 25 26 #include "mgag200_reg.h" 27 28 #define DRIVER_AUTHOR "Matthew Garrett" 29 30 #define DRIVER_NAME "mgag200" 31 #define DRIVER_DESC "MGA G200 SE" 32 #define DRIVER_DATE "20110418" 33 34 #define DRIVER_MAJOR 1 35 #define DRIVER_MINOR 0 36 #define DRIVER_PATCHLEVEL 0 37 38 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) 39 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) 40 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg)) 41 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg)) 42 43 #define MGA_BIOS_OFFSET 0x7ffc 44 45 #define ATTR_INDEX 0x1fc0 46 #define ATTR_DATA 0x1fc1 47 48 #define WREG_MISC(v) \ 49 WREG8(MGA_MISC_OUT, v) 50 51 #define RREG_MISC(v) \ 52 ((v) = RREG8(MGA_MISC_IN)) 53 54 #define WREG_MISC_MASKED(v, mask) \ 55 do { \ 56 u8 misc_; \ 57 u8 mask_ = (mask); \ 58 RREG_MISC(misc_); \ 59 misc_ &= ~mask_; \ 60 misc_ |= ((v) & mask_); \ 61 WREG_MISC(misc_); \ 62 } while (0) 63 64 #define WREG_ATTR(reg, v) \ 65 do { \ 66 RREG8(0x1fda); \ 67 WREG8(ATTR_INDEX, reg); \ 68 WREG8(ATTR_DATA, v); \ 69 } while (0) \ 70 71 #define RREG_SEQ(reg, v) \ 72 do { \ 73 WREG8(MGAREG_SEQ_INDEX, reg); \ 74 v = RREG8(MGAREG_SEQ_DATA); \ 75 } while (0) \ 76 77 #define WREG_SEQ(reg, v) \ 78 do { \ 79 WREG8(MGAREG_SEQ_INDEX, reg); \ 80 WREG8(MGAREG_SEQ_DATA, v); \ 81 } while (0) \ 82 83 #define RREG_CRT(reg, v) \ 84 do { \ 85 WREG8(MGAREG_CRTC_INDEX, reg); \ 86 v = RREG8(MGAREG_CRTC_DATA); \ 87 } while (0) \ 88 89 #define WREG_CRT(reg, v) \ 90 do { \ 91 WREG8(MGAREG_CRTC_INDEX, reg); \ 92 WREG8(MGAREG_CRTC_DATA, v); \ 93 } while (0) \ 94 95 #define RREG_ECRT(reg, v) \ 96 do { \ 97 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 98 v = RREG8(MGAREG_CRTCEXT_DATA); \ 99 } while (0) \ 100 101 #define WREG_ECRT(reg, v) \ 102 do { \ 103 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 104 WREG8(MGAREG_CRTCEXT_DATA, v); \ 105 } while (0) \ 106 107 #define GFX_INDEX 0x1fce 108 #define GFX_DATA 0x1fcf 109 110 #define WREG_GFX(reg, v) \ 111 do { \ 112 WREG8(GFX_INDEX, reg); \ 113 WREG8(GFX_DATA, v); \ 114 } while (0) \ 115 116 #define DAC_INDEX 0x3c00 117 #define DAC_DATA 0x3c0a 118 119 #define WREG_DAC(reg, v) \ 120 do { \ 121 WREG8(DAC_INDEX, reg); \ 122 WREG8(DAC_DATA, v); \ 123 } while (0) \ 124 125 #define MGA_MISC_OUT 0x1fc2 126 #define MGA_MISC_IN 0x1fcc 127 128 /* 129 * TODO: This is a pretty large set of default values for all kinds of 130 * settings. It should be split and set in the various DRM helpers, 131 * such as the CRTC reset or atomic_enable helpers. The PLL values 132 * probably belong to each model's PLL code. 133 */ 134 #define MGAG200_DAC_DEFAULT(xvrefctrl, xpixclkctrl, xmiscctrl, xsyspllm, xsysplln, xsyspllp) \ 135 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, \ 136 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, \ 137 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, \ 138 /* 0x18: */ (xvrefctrl), \ 139 /* 0x19: */ 0, \ 140 /* 0x1a: */ (xpixclkctrl), \ 141 /* 0x1b: */ 0xff, 0xbf, 0x20, \ 142 /* 0x1e: */ (xmiscctrl), \ 143 /* 0x1f: */ 0x20, \ 144 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ 145 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, \ 146 /* 0x2c: */ (xsyspllm), \ 147 /* 0x2d: */ (xsysplln), \ 148 /* 0x2e: */ (xsyspllp), \ 149 /* 0x2f: */ 0x40, \ 150 /* 0x30: */ 0x00, 0xb0, 0x00, 0xc2, 0x34, 0x14, 0x02, 0x83, \ 151 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3a, \ 152 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, \ 153 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 \ 154 155 #define MGAG200_LUT_SIZE 256 156 157 #define MGAG200_MAX_FB_HEIGHT 4096 158 #define MGAG200_MAX_FB_WIDTH 4096 159 160 struct mga_device; 161 162 /* 163 * Stores parameters for programming the PLLs 164 * 165 * Fref: reference frequency (A: 25.175 Mhz, B: 28.361, C: XX Mhz) 166 * Fo: output frequency 167 * Fvco = Fref * (N / M) 168 * Fo = Fvco / P 169 * 170 * S = [0..3] 171 */ 172 struct mgag200_pll_values { 173 unsigned int m; 174 unsigned int n; 175 unsigned int p; 176 unsigned int s; 177 }; 178 179 struct mgag200_crtc_state { 180 struct drm_crtc_state base; 181 182 /* Primary-plane format; required for modesetting and color mgmt. */ 183 const struct drm_format_info *format; 184 185 struct mgag200_pll_values pixpllc; 186 }; 187 188 static inline struct mgag200_crtc_state *to_mgag200_crtc_state(struct drm_crtc_state *base) 189 { 190 return container_of(base, struct mgag200_crtc_state, base); 191 } 192 193 struct mga_i2c_chan { 194 struct i2c_adapter adapter; 195 struct drm_device *dev; 196 struct i2c_algo_bit_data bit; 197 int data, clock; 198 }; 199 200 enum mga_type { 201 G200_PCI, 202 G200_AGP, 203 G200_SE_A, 204 G200_SE_B, 205 G200_WB, 206 G200_EV, 207 G200_EH, 208 G200_EH3, 209 G200_ER, 210 G200_EW3, 211 }; 212 213 struct mgag200_device_info { 214 u16 max_hdisplay; 215 u16 max_vdisplay; 216 217 /* 218 * Maximum memory bandwidth (MiB/sec). Setting this to zero disables 219 * the rsp test during mode validation. 220 */ 221 unsigned long max_mem_bandwidth; 222 223 /* HW has external source (e.g., BMC) to synchronize with */ 224 bool has_vidrst:1; 225 226 struct { 227 unsigned data_bit:3; 228 unsigned clock_bit:3; 229 } i2c; 230 231 /* 232 * HW does not handle 'startadd' register correctly. Always set 233 * it's value to 0. 234 */ 235 bool bug_no_startadd:1; 236 }; 237 238 #define MGAG200_DEVICE_INFO_INIT(_max_hdisplay, _max_vdisplay, _max_mem_bandwidth, \ 239 _has_vidrst, _i2c_data_bit, _i2c_clock_bit, \ 240 _bug_no_startadd) \ 241 { \ 242 .max_hdisplay = (_max_hdisplay), \ 243 .max_vdisplay = (_max_vdisplay), \ 244 .max_mem_bandwidth = (_max_mem_bandwidth), \ 245 .has_vidrst = (_has_vidrst), \ 246 .i2c = { \ 247 .data_bit = (_i2c_data_bit), \ 248 .clock_bit = (_i2c_clock_bit), \ 249 }, \ 250 .bug_no_startadd = (_bug_no_startadd), \ 251 } 252 253 struct mgag200_device_funcs { 254 /* 255 * Disables an external reset source (i.e., BMC) before programming 256 * a new display mode. 257 */ 258 void (*disable_vidrst)(struct mga_device *mdev); 259 260 /* 261 * Enables an external reset source (i.e., BMC) after programming 262 * a new display mode. 263 */ 264 void (*enable_vidrst)(struct mga_device *mdev); 265 266 /* 267 * Validate that the given state can be programmed into PIXPLLC. On 268 * success, the calculated parameters should be stored in the CRTC's 269 * state in struct @mgag200_crtc_state.pixpllc. 270 */ 271 int (*pixpllc_atomic_check)(struct drm_crtc *crtc, struct drm_atomic_state *new_state); 272 273 /* 274 * Program PIXPLLC from the CRTC state. The parameters should have been 275 * stored in struct @mgag200_crtc_state.pixpllc by the corresponding 276 * implementation of @pixpllc_atomic_check. 277 */ 278 void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 279 }; 280 281 struct mga_device { 282 struct drm_device base; 283 284 const struct mgag200_device_info *info; 285 const struct mgag200_device_funcs *funcs; 286 287 struct resource *rmmio_res; 288 void __iomem *rmmio; 289 struct mutex rmmio_lock; /* Protects access to rmmio */ 290 291 struct resource *vram_res; 292 void __iomem *vram; 293 resource_size_t vram_available; 294 295 struct drm_plane primary_plane; 296 struct drm_crtc crtc; 297 struct drm_encoder encoder; 298 struct mga_i2c_chan i2c; 299 struct drm_connector connector; 300 }; 301 302 static inline struct mga_device *to_mga_device(struct drm_device *dev) 303 { 304 return container_of(dev, struct mga_device, base); 305 } 306 307 struct mgag200_g200_device { 308 struct mga_device base; 309 310 /* PLL constants */ 311 long ref_clk; 312 long pclk_min; 313 long pclk_max; 314 }; 315 316 static inline struct mgag200_g200_device *to_mgag200_g200_device(struct drm_device *dev) 317 { 318 return container_of(to_mga_device(dev), struct mgag200_g200_device, base); 319 } 320 321 struct mgag200_g200se_device { 322 struct mga_device base; 323 324 /* SE model number stored in reg 0x1e24 */ 325 u32 unique_rev_id; 326 }; 327 328 static inline struct mgag200_g200se_device *to_mgag200_g200se_device(struct drm_device *dev) 329 { 330 return container_of(to_mga_device(dev), struct mgag200_g200se_device, base); 331 } 332 333 /* mgag200_drv.c */ 334 int mgag200_init_pci_options(struct pci_dev *pdev, u32 option, u32 option2); 335 resource_size_t mgag200_probe_vram(void __iomem *mem, resource_size_t size); 336 resource_size_t mgag200_device_probe_vram(struct mga_device *mdev); 337 int mgag200_device_preinit(struct mga_device *mdev); 338 int mgag200_device_init(struct mga_device *mdev, 339 const struct mgag200_device_info *info, 340 const struct mgag200_device_funcs *funcs); 341 342 /* mgag200_<device type>.c */ 343 struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct drm_driver *drv); 344 struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 345 enum mga_type type); 346 void mgag200_g200wb_init_registers(struct mga_device *mdev); 347 void mgag200_g200wb_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 348 struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv); 349 struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv); 350 void mgag200_g200eh_init_registers(struct mga_device *mdev); 351 void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 352 struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, 353 const struct drm_driver *drv); 354 struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev, 355 const struct drm_driver *drv); 356 struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev, 357 const struct drm_driver *drv); 358 struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev, 359 const struct drm_driver *drv); 360 361 /* 362 * mgag200_mode.c 363 */ 364 365 struct drm_crtc; 366 struct drm_crtc_state; 367 struct drm_display_mode; 368 struct drm_plane; 369 struct drm_atomic_state; 370 371 extern const uint32_t mgag200_primary_plane_formats[]; 372 extern const size_t mgag200_primary_plane_formats_size; 373 extern const uint64_t mgag200_primary_plane_fmtmods[]; 374 375 int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, 376 struct drm_atomic_state *new_state); 377 void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, 378 struct drm_atomic_state *old_state); 379 void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane, 380 struct drm_atomic_state *old_state); 381 #define MGAG200_PRIMARY_PLANE_HELPER_FUNCS \ 382 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, \ 383 .atomic_check = mgag200_primary_plane_helper_atomic_check, \ 384 .atomic_update = mgag200_primary_plane_helper_atomic_update, \ 385 .atomic_disable = mgag200_primary_plane_helper_atomic_disable 386 387 #define MGAG200_PRIMARY_PLANE_FUNCS \ 388 .update_plane = drm_atomic_helper_update_plane, \ 389 .disable_plane = drm_atomic_helper_disable_plane, \ 390 .destroy = drm_plane_cleanup, \ 391 DRM_GEM_SHADOW_PLANE_FUNCS 392 393 enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc, 394 const struct drm_display_mode *mode); 395 int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state); 396 void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 397 void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 398 void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 399 400 #define MGAG200_CRTC_HELPER_FUNCS \ 401 .mode_valid = mgag200_crtc_helper_mode_valid, \ 402 .atomic_check = mgag200_crtc_helper_atomic_check, \ 403 .atomic_flush = mgag200_crtc_helper_atomic_flush, \ 404 .atomic_enable = mgag200_crtc_helper_atomic_enable, \ 405 .atomic_disable = mgag200_crtc_helper_atomic_disable 406 407 void mgag200_crtc_reset(struct drm_crtc *crtc); 408 struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc); 409 void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state); 410 411 #define MGAG200_CRTC_FUNCS \ 412 .reset = mgag200_crtc_reset, \ 413 .destroy = drm_crtc_cleanup, \ 414 .set_config = drm_atomic_helper_set_config, \ 415 .page_flip = drm_atomic_helper_page_flip, \ 416 .atomic_duplicate_state = mgag200_crtc_atomic_duplicate_state, \ 417 .atomic_destroy_state = mgag200_crtc_atomic_destroy_state 418 419 #define MGAG200_DAC_ENCODER_FUNCS \ 420 .destroy = drm_encoder_cleanup 421 422 int mgag200_vga_connector_helper_get_modes(struct drm_connector *connector); 423 424 #define MGAG200_VGA_CONNECTOR_HELPER_FUNCS \ 425 .get_modes = mgag200_vga_connector_helper_get_modes 426 427 #define MGAG200_VGA_CONNECTOR_FUNCS \ 428 .reset = drm_atomic_helper_connector_reset, \ 429 .fill_modes = drm_helper_probe_single_connector_modes, \ 430 .destroy = drm_connector_cleanup, \ 431 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, \ 432 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state 433 434 void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode); 435 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format); 436 void mgag200_enable_display(struct mga_device *mdev); 437 void mgag200_init_registers(struct mga_device *mdev); 438 int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available); 439 440 /* mgag200_bmc.c */ 441 void mgag200_bmc_disable_vidrst(struct mga_device *mdev); 442 void mgag200_bmc_enable_vidrst(struct mga_device *mdev); 443 444 /* mgag200_i2c.c */ 445 int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c); 446 447 #endif /* __MGAG200_DRV_H__ */ 448