1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 6 * Copyright (C) 2014 Endless Mobile 7 */ 8 9 #include <linux/export.h> 10 11 #include "meson_drv.h" 12 #include "meson_registers.h" 13 #include "meson_vpp.h" 14 15 /** 16 * DOC: Video Post Processing 17 * 18 * VPP Handles all the Post Processing after the Scanout from the VIU 19 * We handle the following post processings : 20 * 21 * - Postblend, Blends the OSD1 only 22 * We exclude OSD2, VS1, VS1 and Preblend output 23 * - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and 24 * use it only for interlace scanout 25 * - Intermediate FIFO with default Amlogic values 26 * 27 * What is missing : 28 * 29 * - Preblend for video overlay pre-scaling 30 * - OSD2 support for cursor framebuffer 31 * - Video pre-scaling before postblend 32 * - Full Vertical/Horizontal OSD scaling to support TV overscan 33 * - HDR conversion 34 */ 35 36 void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux) 37 { 38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); 39 } 40 41 static unsigned int vpp_filter_coefs_4point_bspline[] = { 42 0x15561500, 0x14561600, 0x13561700, 0x12561800, 43 0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00, 44 0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200, 45 0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700, 46 0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01, 47 0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201, 48 0x05473301, 0x05463401, 0x04453601, 0x04433702, 49 0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02, 50 0x033d3d03 51 }; 52 53 static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv, 54 const unsigned int *coefs, 55 bool is_horizontal) 56 { 57 int i; 58 59 writel_relaxed(is_horizontal ? BIT(8) : 0, 60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); 61 for (i = 0; i < 33; i++) 62 writel_relaxed(coefs[i], 63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); 64 } 65 66 static const uint32_t vpp_filter_coefs_bicubic[] = { 67 0x00800000, 0x007f0100, 0xff7f0200, 0xfe7f0300, 68 0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900, 69 0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff, 70 0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe, 71 0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd, 72 0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb, 73 0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa, 74 0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9, 75 0xf84848f8 76 }; 77 78 static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv, 79 const unsigned int *coefs, 80 bool is_horizontal) 81 { 82 int i; 83 84 writel_relaxed(is_horizontal ? BIT(8) : 0, 85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); 86 for (i = 0; i < 33; i++) 87 writel_relaxed(coefs[i], 88 priv->io_base + _REG(VPP_SCALE_COEF)); 89 } 90 91 void meson_vpp_init(struct meson_drm *priv) 92 { 93 /* set dummy data default YUV black */ 94 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) 95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); 96 else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) { 97 writel_bits_relaxed(0xff << 16, 0xff << 16, 98 priv->io_base + _REG(VIU_MISC_CTRL1)); 99 writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL)); 100 writel_relaxed(0x1020080, 101 priv->io_base + _REG(VPP_DUMMY_DATA1)); 102 } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 103 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); 104 105 /* Initialize vpu fifo control registers */ 106 if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 107 writel_relaxed(0xfff << 20 | 0x1000, 108 priv->io_base + _REG(VPP_OFIFO_SIZE)); 109 else 110 writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) | 111 0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE)); 112 writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES)); 113 114 if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 115 /* Turn off preblend */ 116 writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, 117 priv->io_base + _REG(VPP_MISC)); 118 119 /* Turn off POSTBLEND */ 120 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0, 121 priv->io_base + _REG(VPP_MISC)); 122 123 /* Force all planes off */ 124 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | 125 VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND | 126 VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0, 127 priv->io_base + _REG(VPP_MISC)); 128 129 /* Setup default VD settings */ 130 writel_relaxed(4096, 131 priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END)); 132 writel_relaxed(4096, 133 priv->io_base + _REG(VPP_BLEND_VD2_H_START_END)); 134 } 135 136 /* Disable Scalers */ 137 writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); 138 writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); 139 writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); 140 writel_relaxed(4 | (4 << 8) | BIT(15), 141 priv->io_base + _REG(VPP_SC_MISC)); 142 143 writel_relaxed(1, priv->io_base + _REG(VPP_VADJ_CTRL)); 144 145 /* Write in the proper filter coefficients. */ 146 meson_vpp_write_scaling_filter_coefs(priv, 147 vpp_filter_coefs_4point_bspline, false); 148 meson_vpp_write_scaling_filter_coefs(priv, 149 vpp_filter_coefs_4point_bspline, true); 150 151 /* Write the VD proper filter coefficients. */ 152 meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic, 153 false); 154 meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic, 155 true); 156 } 157