1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <drm/drmP.h> 23 #include "meson_drv.h" 24 #include "meson_venc.h" 25 #include "meson_vpp.h" 26 #include "meson_vclk.h" 27 #include "meson_registers.h" 28 29 /** 30 * DOC: Video Encoder 31 * 32 * VENC Handle the pixels encoding to the output formats. 33 * We handle the following encodings : 34 * 35 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter 36 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP 37 * - Setup of more clock rates for HDMI modes 38 * 39 * What is missing : 40 * 41 * - LCD Panel encoding via ENCL 42 * - TV Panel encoding via ENCT 43 * 44 * VENC paths : 45 * 46 * .. code:: 47 * 48 * _____ _____ ____________________ 49 * vd1---| |-| | | VENC /---------|----VDAC 50 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-| 51 * osd1--| |-| | | \ | X--HDMI-TX 52 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-| 53 * | | | 54 * | \--ENCL-----------|----LVDS 55 * |____________________| 56 * 57 * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC 58 * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI. 59 * The ENCP is designed for Progressive encoding but can also generate 60 * 1080i interlaced pixels, and was initialy desined to encode pixels for 61 * VDAC to output RGB ou YUV analog outputs. 62 * It's output is only used through the ENCP_DVI encoder for HDMI. 63 * The ENCL LVDS encoder is not implemented. 64 * 65 * The ENCI and ENCP encoders needs specially defined parameters for each 66 * supported mode and thus cannot be determined from standard video timings. 67 * 68 * The ENCI end ENCP DVI encoders are more generic and can generate any timings 69 * from the pixel data generated by ENCI or ENCP, so can use the standard video 70 * timings are source for HW parameters. 71 */ 72 73 /* HHI Registers */ 74 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ 75 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ 76 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */ 77 78 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = { 79 .mode_tag = MESON_VENC_MODE_CVBS_PAL, 80 .hso_begin = 3, 81 .hso_end = 129, 82 .vso_even = 3, 83 .vso_odd = 260, 84 .macv_max_amp = 7, 85 .video_prog_mode = 0xff, 86 .video_mode = 0x13, 87 .sch_adjust = 0x28, 88 .yc_delay = 0x343, 89 .pixel_start = 251, 90 .pixel_end = 1691, 91 .top_field_line_start = 22, 92 .top_field_line_end = 310, 93 .bottom_field_line_start = 23, 94 .bottom_field_line_end = 311, 95 .video_saturation = 9, 96 .video_contrast = 0, 97 .video_brightness = 0, 98 .video_hue = 0, 99 .analog_sync_adj = 0x8080, 100 }; 101 102 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = { 103 .mode_tag = MESON_VENC_MODE_CVBS_NTSC, 104 .hso_begin = 5, 105 .hso_end = 129, 106 .vso_even = 3, 107 .vso_odd = 260, 108 .macv_max_amp = 0xb, 109 .video_prog_mode = 0xf0, 110 .video_mode = 0x8, 111 .sch_adjust = 0x20, 112 .yc_delay = 0x333, 113 .pixel_start = 227, 114 .pixel_end = 1667, 115 .top_field_line_start = 18, 116 .top_field_line_end = 258, 117 .bottom_field_line_start = 19, 118 .bottom_field_line_end = 259, 119 .video_saturation = 18, 120 .video_contrast = 3, 121 .video_brightness = 0, 122 .video_hue = 0, 123 .analog_sync_adj = 0x9c00, 124 }; 125 126 union meson_hdmi_venc_mode { 127 struct { 128 unsigned int mode_tag; 129 unsigned int hso_begin; 130 unsigned int hso_end; 131 unsigned int vso_even; 132 unsigned int vso_odd; 133 unsigned int macv_max_amp; 134 unsigned int video_prog_mode; 135 unsigned int video_mode; 136 unsigned int sch_adjust; 137 unsigned int yc_delay; 138 unsigned int pixel_start; 139 unsigned int pixel_end; 140 unsigned int top_field_line_start; 141 unsigned int top_field_line_end; 142 unsigned int bottom_field_line_start; 143 unsigned int bottom_field_line_end; 144 } enci; 145 struct { 146 unsigned int dvi_settings; 147 unsigned int video_mode; 148 unsigned int video_mode_adv; 149 unsigned int video_prog_mode; 150 bool video_prog_mode_present; 151 unsigned int video_sync_mode; 152 bool video_sync_mode_present; 153 unsigned int video_yc_dly; 154 bool video_yc_dly_present; 155 unsigned int video_rgb_ctrl; 156 bool video_rgb_ctrl_present; 157 unsigned int video_filt_ctrl; 158 bool video_filt_ctrl_present; 159 unsigned int video_ofld_voav_ofst; 160 bool video_ofld_voav_ofst_present; 161 unsigned int yfp1_htime; 162 unsigned int yfp2_htime; 163 unsigned int max_pxcnt; 164 unsigned int hspuls_begin; 165 unsigned int hspuls_end; 166 unsigned int hspuls_switch; 167 unsigned int vspuls_begin; 168 unsigned int vspuls_end; 169 unsigned int vspuls_bline; 170 unsigned int vspuls_eline; 171 unsigned int eqpuls_begin; 172 bool eqpuls_begin_present; 173 unsigned int eqpuls_end; 174 bool eqpuls_end_present; 175 unsigned int eqpuls_bline; 176 bool eqpuls_bline_present; 177 unsigned int eqpuls_eline; 178 bool eqpuls_eline_present; 179 unsigned int havon_begin; 180 unsigned int havon_end; 181 unsigned int vavon_bline; 182 unsigned int vavon_eline; 183 unsigned int hso_begin; 184 unsigned int hso_end; 185 unsigned int vso_begin; 186 unsigned int vso_end; 187 unsigned int vso_bline; 188 unsigned int vso_eline; 189 bool vso_eline_present; 190 unsigned int sy_val; 191 bool sy_val_present; 192 unsigned int sy2_val; 193 bool sy2_val_present; 194 unsigned int max_lncnt; 195 } encp; 196 }; 197 198 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = { 199 .enci = { 200 .hso_begin = 5, 201 .hso_end = 129, 202 .vso_even = 3, 203 .vso_odd = 260, 204 .macv_max_amp = 0x810b, 205 .video_prog_mode = 0xf0, 206 .video_mode = 0x8, 207 .sch_adjust = 0x20, 208 .yc_delay = 0, 209 .pixel_start = 227, 210 .pixel_end = 1667, 211 .top_field_line_start = 18, 212 .top_field_line_end = 258, 213 .bottom_field_line_start = 19, 214 .bottom_field_line_end = 259, 215 }, 216 }; 217 218 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = { 219 .enci = { 220 .hso_begin = 3, 221 .hso_end = 129, 222 .vso_even = 3, 223 .vso_odd = 260, 224 .macv_max_amp = 8107, 225 .video_prog_mode = 0xff, 226 .video_mode = 0x13, 227 .sch_adjust = 0x28, 228 .yc_delay = 0x333, 229 .pixel_start = 251, 230 .pixel_end = 1691, 231 .top_field_line_start = 22, 232 .top_field_line_end = 310, 233 .bottom_field_line_start = 23, 234 .bottom_field_line_end = 311, 235 }, 236 }; 237 238 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = { 239 .encp = { 240 .dvi_settings = 0x21, 241 .video_mode = 0x4000, 242 .video_mode_adv = 0x9, 243 .video_prog_mode = 0, 244 .video_prog_mode_present = true, 245 .video_sync_mode = 7, 246 .video_sync_mode_present = true, 247 /* video_yc_dly */ 248 /* video_rgb_ctrl */ 249 .video_filt_ctrl = 0x2052, 250 .video_filt_ctrl_present = true, 251 /* video_ofld_voav_ofst */ 252 .yfp1_htime = 244, 253 .yfp2_htime = 1630, 254 .max_pxcnt = 1715, 255 .hspuls_begin = 0x22, 256 .hspuls_end = 0xa0, 257 .hspuls_switch = 88, 258 .vspuls_begin = 0, 259 .vspuls_end = 1589, 260 .vspuls_bline = 0, 261 .vspuls_eline = 5, 262 .havon_begin = 249, 263 .havon_end = 1689, 264 .vavon_bline = 42, 265 .vavon_eline = 521, 266 /* eqpuls_begin */ 267 /* eqpuls_end */ 268 /* eqpuls_bline */ 269 /* eqpuls_eline */ 270 .hso_begin = 3, 271 .hso_end = 5, 272 .vso_begin = 3, 273 .vso_end = 5, 274 .vso_bline = 0, 275 /* vso_eline */ 276 .sy_val = 8, 277 .sy_val_present = true, 278 .sy2_val = 0x1d8, 279 .sy2_val_present = true, 280 .max_lncnt = 524, 281 }, 282 }; 283 284 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = { 285 .encp = { 286 .dvi_settings = 0x21, 287 .video_mode = 0x4000, 288 .video_mode_adv = 0x9, 289 .video_prog_mode = 0, 290 .video_prog_mode_present = true, 291 .video_sync_mode = 7, 292 .video_sync_mode_present = true, 293 /* video_yc_dly */ 294 /* video_rgb_ctrl */ 295 .video_filt_ctrl = 0x52, 296 .video_filt_ctrl_present = true, 297 /* video_ofld_voav_ofst */ 298 .yfp1_htime = 235, 299 .yfp2_htime = 1674, 300 .max_pxcnt = 1727, 301 .hspuls_begin = 0, 302 .hspuls_end = 0x80, 303 .hspuls_switch = 88, 304 .vspuls_begin = 0, 305 .vspuls_end = 1599, 306 .vspuls_bline = 0, 307 .vspuls_eline = 4, 308 .havon_begin = 235, 309 .havon_end = 1674, 310 .vavon_bline = 44, 311 .vavon_eline = 619, 312 /* eqpuls_begin */ 313 /* eqpuls_end */ 314 /* eqpuls_bline */ 315 /* eqpuls_eline */ 316 .hso_begin = 0x80, 317 .hso_end = 0, 318 .vso_begin = 0, 319 .vso_end = 5, 320 .vso_bline = 0, 321 /* vso_eline */ 322 .sy_val = 8, 323 .sy_val_present = true, 324 .sy2_val = 0x1d8, 325 .sy2_val_present = true, 326 .max_lncnt = 624, 327 }, 328 }; 329 330 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = { 331 .encp = { 332 .dvi_settings = 0x2029, 333 .video_mode = 0x4040, 334 .video_mode_adv = 0x19, 335 /* video_prog_mode */ 336 /* video_sync_mode */ 337 /* video_yc_dly */ 338 /* video_rgb_ctrl */ 339 /* video_filt_ctrl */ 340 /* video_ofld_voav_ofst */ 341 .yfp1_htime = 648, 342 .yfp2_htime = 3207, 343 .max_pxcnt = 3299, 344 .hspuls_begin = 80, 345 .hspuls_end = 240, 346 .hspuls_switch = 80, 347 .vspuls_begin = 688, 348 .vspuls_end = 3248, 349 .vspuls_bline = 4, 350 .vspuls_eline = 8, 351 .havon_begin = 648, 352 .havon_end = 3207, 353 .vavon_bline = 29, 354 .vavon_eline = 748, 355 /* eqpuls_begin */ 356 /* eqpuls_end */ 357 /* eqpuls_bline */ 358 /* eqpuls_eline */ 359 .hso_begin = 256, 360 .hso_end = 168, 361 .vso_begin = 168, 362 .vso_end = 256, 363 .vso_bline = 0, 364 .vso_eline = 5, 365 .vso_eline_present = true, 366 /* sy_val */ 367 /* sy2_val */ 368 .max_lncnt = 749, 369 }, 370 }; 371 372 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = { 373 .encp = { 374 .dvi_settings = 0x202d, 375 .video_mode = 0x4040, 376 .video_mode_adv = 0x19, 377 .video_prog_mode = 0x100, 378 .video_prog_mode_present = true, 379 .video_sync_mode = 0x407, 380 .video_sync_mode_present = true, 381 .video_yc_dly = 0, 382 .video_yc_dly_present = true, 383 /* video_rgb_ctrl */ 384 /* video_filt_ctrl */ 385 /* video_ofld_voav_ofst */ 386 .yfp1_htime = 648, 387 .yfp2_htime = 3207, 388 .max_pxcnt = 3959, 389 .hspuls_begin = 80, 390 .hspuls_end = 240, 391 .hspuls_switch = 80, 392 .vspuls_begin = 688, 393 .vspuls_end = 3248, 394 .vspuls_bline = 4, 395 .vspuls_eline = 8, 396 .havon_begin = 648, 397 .havon_end = 3207, 398 .vavon_bline = 29, 399 .vavon_eline = 748, 400 /* eqpuls_begin */ 401 /* eqpuls_end */ 402 /* eqpuls_bline */ 403 /* eqpuls_eline */ 404 .hso_begin = 128, 405 .hso_end = 208, 406 .vso_begin = 128, 407 .vso_end = 128, 408 .vso_bline = 0, 409 .vso_eline = 5, 410 .vso_eline_present = true, 411 /* sy_val */ 412 /* sy2_val */ 413 .max_lncnt = 749, 414 }, 415 }; 416 417 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = { 418 .encp = { 419 .dvi_settings = 0x2029, 420 .video_mode = 0x5ffc, 421 .video_mode_adv = 0x19, 422 .video_prog_mode = 0x100, 423 .video_prog_mode_present = true, 424 .video_sync_mode = 0x207, 425 .video_sync_mode_present = true, 426 /* video_yc_dly */ 427 /* video_rgb_ctrl */ 428 /* video_filt_ctrl */ 429 .video_ofld_voav_ofst = 0x11, 430 .video_ofld_voav_ofst_present = true, 431 .yfp1_htime = 516, 432 .yfp2_htime = 4355, 433 .max_pxcnt = 4399, 434 .hspuls_begin = 88, 435 .hspuls_end = 264, 436 .hspuls_switch = 88, 437 .vspuls_begin = 440, 438 .vspuls_end = 2200, 439 .vspuls_bline = 0, 440 .vspuls_eline = 4, 441 .havon_begin = 516, 442 .havon_end = 4355, 443 .vavon_bline = 20, 444 .vavon_eline = 559, 445 .eqpuls_begin = 2288, 446 .eqpuls_begin_present = true, 447 .eqpuls_end = 2464, 448 .eqpuls_end_present = true, 449 .eqpuls_bline = 0, 450 .eqpuls_bline_present = true, 451 .eqpuls_eline = 4, 452 .eqpuls_eline_present = true, 453 .hso_begin = 264, 454 .hso_end = 176, 455 .vso_begin = 88, 456 .vso_end = 88, 457 .vso_bline = 0, 458 .vso_eline = 5, 459 .vso_eline_present = true, 460 /* sy_val */ 461 /* sy2_val */ 462 .max_lncnt = 1124, 463 }, 464 }; 465 466 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = { 467 .encp = { 468 .dvi_settings = 0x202d, 469 .video_mode = 0x5ffc, 470 .video_mode_adv = 0x19, 471 .video_prog_mode = 0x100, 472 .video_prog_mode_present = true, 473 .video_sync_mode = 0x7, 474 .video_sync_mode_present = true, 475 /* video_yc_dly */ 476 /* video_rgb_ctrl */ 477 /* video_filt_ctrl */ 478 .video_ofld_voav_ofst = 0x11, 479 .video_ofld_voav_ofst_present = true, 480 .yfp1_htime = 526, 481 .yfp2_htime = 4365, 482 .max_pxcnt = 5279, 483 .hspuls_begin = 88, 484 .hspuls_end = 264, 485 .hspuls_switch = 88, 486 .vspuls_begin = 440, 487 .vspuls_end = 2200, 488 .vspuls_bline = 0, 489 .vspuls_eline = 4, 490 .havon_begin = 526, 491 .havon_end = 4365, 492 .vavon_bline = 20, 493 .vavon_eline = 559, 494 .eqpuls_begin = 2288, 495 .eqpuls_begin_present = true, 496 .eqpuls_end = 2464, 497 .eqpuls_end_present = true, 498 .eqpuls_bline = 0, 499 .eqpuls_bline_present = true, 500 .eqpuls_eline = 4, 501 .eqpuls_eline_present = true, 502 .hso_begin = 142, 503 .hso_end = 230, 504 .vso_begin = 142, 505 .vso_end = 142, 506 .vso_bline = 0, 507 .vso_eline = 5, 508 .vso_eline_present = true, 509 /* sy_val */ 510 /* sy2_val */ 511 .max_lncnt = 1124, 512 }, 513 }; 514 515 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = { 516 .encp = { 517 .dvi_settings = 0xd, 518 .video_mode = 0x4040, 519 .video_mode_adv = 0x18, 520 .video_prog_mode = 0x100, 521 .video_prog_mode_present = true, 522 .video_sync_mode = 0x7, 523 .video_sync_mode_present = true, 524 .video_yc_dly = 0, 525 .video_yc_dly_present = true, 526 .video_rgb_ctrl = 2, 527 .video_rgb_ctrl_present = true, 528 .video_filt_ctrl = 0x1052, 529 .video_filt_ctrl_present = true, 530 /* video_ofld_voav_ofst */ 531 .yfp1_htime = 271, 532 .yfp2_htime = 2190, 533 .max_pxcnt = 2749, 534 .hspuls_begin = 44, 535 .hspuls_end = 132, 536 .hspuls_switch = 44, 537 .vspuls_begin = 220, 538 .vspuls_end = 2140, 539 .vspuls_bline = 0, 540 .vspuls_eline = 4, 541 .havon_begin = 271, 542 .havon_end = 2190, 543 .vavon_bline = 41, 544 .vavon_eline = 1120, 545 /* eqpuls_begin */ 546 /* eqpuls_end */ 547 .eqpuls_bline = 0, 548 .eqpuls_bline_present = true, 549 .eqpuls_eline = 4, 550 .eqpuls_eline_present = true, 551 .hso_begin = 79, 552 .hso_end = 123, 553 .vso_begin = 79, 554 .vso_end = 79, 555 .vso_bline = 0, 556 .vso_eline = 5, 557 .vso_eline_present = true, 558 /* sy_val */ 559 /* sy2_val */ 560 .max_lncnt = 1124, 561 }, 562 }; 563 564 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = { 565 .encp = { 566 .dvi_settings = 0x1, 567 .video_mode = 0x4040, 568 .video_mode_adv = 0x18, 569 .video_prog_mode = 0x100, 570 .video_prog_mode_present = true, 571 /* video_sync_mode */ 572 /* video_yc_dly */ 573 /* video_rgb_ctrl */ 574 .video_filt_ctrl = 0x1052, 575 .video_filt_ctrl_present = true, 576 /* video_ofld_voav_ofst */ 577 .yfp1_htime = 140, 578 .yfp2_htime = 2060, 579 .max_pxcnt = 2199, 580 .hspuls_begin = 2156, 581 .hspuls_end = 44, 582 .hspuls_switch = 44, 583 .vspuls_begin = 140, 584 .vspuls_end = 2059, 585 .vspuls_bline = 0, 586 .vspuls_eline = 4, 587 .havon_begin = 148, 588 .havon_end = 2067, 589 .vavon_bline = 41, 590 .vavon_eline = 1120, 591 /* eqpuls_begin */ 592 /* eqpuls_end */ 593 /* eqpuls_bline */ 594 /* eqpuls_eline */ 595 .hso_begin = 44, 596 .hso_end = 2156, 597 .vso_begin = 2100, 598 .vso_end = 2164, 599 .vso_bline = 0, 600 .vso_eline = 5, 601 .vso_eline_present = true, 602 /* sy_val */ 603 /* sy2_val */ 604 .max_lncnt = 1124, 605 }, 606 }; 607 608 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = { 609 .encp = { 610 .dvi_settings = 0xd, 611 .video_mode = 0x4040, 612 .video_mode_adv = 0x18, 613 .video_prog_mode = 0x100, 614 .video_prog_mode_present = true, 615 .video_sync_mode = 0x7, 616 .video_sync_mode_present = true, 617 .video_yc_dly = 0, 618 .video_yc_dly_present = true, 619 .video_rgb_ctrl = 2, 620 .video_rgb_ctrl_present = true, 621 /* video_filt_ctrl */ 622 /* video_ofld_voav_ofst */ 623 .yfp1_htime = 271, 624 .yfp2_htime = 2190, 625 .max_pxcnt = 2639, 626 .hspuls_begin = 44, 627 .hspuls_end = 132, 628 .hspuls_switch = 44, 629 .vspuls_begin = 220, 630 .vspuls_end = 2140, 631 .vspuls_bline = 0, 632 .vspuls_eline = 4, 633 .havon_begin = 271, 634 .havon_end = 2190, 635 .vavon_bline = 41, 636 .vavon_eline = 1120, 637 /* eqpuls_begin */ 638 /* eqpuls_end */ 639 .eqpuls_bline = 0, 640 .eqpuls_bline_present = true, 641 .eqpuls_eline = 4, 642 .eqpuls_eline_present = true, 643 .hso_begin = 79, 644 .hso_end = 123, 645 .vso_begin = 79, 646 .vso_end = 79, 647 .vso_bline = 0, 648 .vso_eline = 5, 649 .vso_eline_present = true, 650 /* sy_val */ 651 /* sy2_val */ 652 .max_lncnt = 1124, 653 }, 654 }; 655 656 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = { 657 .encp = { 658 .dvi_settings = 0x1, 659 .video_mode = 0x4040, 660 .video_mode_adv = 0x18, 661 .video_prog_mode = 0x100, 662 .video_prog_mode_present = true, 663 /* video_sync_mode */ 664 /* video_yc_dly */ 665 /* video_rgb_ctrl */ 666 .video_filt_ctrl = 0x1052, 667 .video_filt_ctrl_present = true, 668 /* video_ofld_voav_ofst */ 669 .yfp1_htime = 140, 670 .yfp2_htime = 2060, 671 .max_pxcnt = 2199, 672 .hspuls_begin = 2156, 673 .hspuls_end = 44, 674 .hspuls_switch = 44, 675 .vspuls_begin = 140, 676 .vspuls_end = 2059, 677 .vspuls_bline = 0, 678 .vspuls_eline = 4, 679 .havon_begin = 148, 680 .havon_end = 2067, 681 .vavon_bline = 41, 682 .vavon_eline = 1120, 683 /* eqpuls_begin */ 684 /* eqpuls_end */ 685 /* eqpuls_bline */ 686 /* eqpuls_eline */ 687 .hso_begin = 44, 688 .hso_end = 2156, 689 .vso_begin = 2100, 690 .vso_end = 2164, 691 .vso_bline = 0, 692 .vso_eline = 5, 693 .vso_eline_present = true, 694 /* sy_val */ 695 /* sy2_val */ 696 .max_lncnt = 1124, 697 }, 698 }; 699 700 struct meson_hdmi_venc_vic_mode { 701 unsigned int vic; 702 union meson_hdmi_venc_mode *mode; 703 } meson_hdmi_venc_vic_modes[] = { 704 { 6, &meson_hdmi_enci_mode_480i }, 705 { 7, &meson_hdmi_enci_mode_480i }, 706 { 21, &meson_hdmi_enci_mode_576i }, 707 { 22, &meson_hdmi_enci_mode_576i }, 708 { 2, &meson_hdmi_encp_mode_480p }, 709 { 3, &meson_hdmi_encp_mode_480p }, 710 { 17, &meson_hdmi_encp_mode_576p }, 711 { 18, &meson_hdmi_encp_mode_576p }, 712 { 4, &meson_hdmi_encp_mode_720p60 }, 713 { 19, &meson_hdmi_encp_mode_720p50 }, 714 { 5, &meson_hdmi_encp_mode_1080i60 }, 715 { 20, &meson_hdmi_encp_mode_1080i50 }, 716 { 32, &meson_hdmi_encp_mode_1080p24 }, 717 { 34, &meson_hdmi_encp_mode_1080p30 }, 718 { 31, &meson_hdmi_encp_mode_1080p50 }, 719 { 16, &meson_hdmi_encp_mode_1080p60 }, 720 { 0, NULL}, /* sentinel */ 721 }; 722 723 static signed int to_signed(unsigned int a) 724 { 725 if (a <= 7) 726 return a; 727 else 728 return a - 16; 729 } 730 731 static unsigned long modulo(unsigned long a, unsigned long b) 732 { 733 if (a >= b) 734 return a - b; 735 else 736 return a; 737 } 738 739 enum drm_mode_status 740 meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode) 741 { 742 if (mode->flags & ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | 743 DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)) 744 return MODE_BAD; 745 746 if (mode->hdisplay < 640 || mode->hdisplay > 1920) 747 return MODE_BAD_HVALUE; 748 749 if (mode->vdisplay < 480 || mode->vdisplay > 1200) 750 return MODE_BAD_VVALUE; 751 752 return MODE_OK; 753 } 754 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode); 755 756 bool meson_venc_hdmi_supported_vic(int vic) 757 { 758 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; 759 760 while (vmode->vic && vmode->mode) { 761 if (vmode->vic == vic) 762 return true; 763 vmode++; 764 } 765 766 return false; 767 } 768 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic); 769 770 void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode, 771 union meson_hdmi_venc_mode *dmt_mode) 772 { 773 memset(dmt_mode, 0, sizeof(*dmt_mode)); 774 775 dmt_mode->encp.dvi_settings = 0x21; 776 dmt_mode->encp.video_mode = 0x4040; 777 dmt_mode->encp.video_mode_adv = 0x18; 778 dmt_mode->encp.max_pxcnt = mode->htotal - 1; 779 dmt_mode->encp.havon_begin = mode->htotal - mode->hsync_start; 780 dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin + 781 mode->hdisplay - 1; 782 dmt_mode->encp.vavon_bline = mode->vtotal - mode->vsync_start; 783 dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline + 784 mode->vdisplay - 1; 785 dmt_mode->encp.hso_begin = 0; 786 dmt_mode->encp.hso_end = mode->hsync_end - mode->hsync_start; 787 dmt_mode->encp.vso_begin = 30; 788 dmt_mode->encp.vso_end = 50; 789 dmt_mode->encp.vso_bline = 0; 790 dmt_mode->encp.vso_eline = mode->vsync_end - mode->vsync_start; 791 dmt_mode->encp.vso_eline_present = true; 792 dmt_mode->encp.max_lncnt = mode->vtotal - 1; 793 } 794 795 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic) 796 { 797 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; 798 799 while (vmode->vic && vmode->mode) { 800 if (vmode->vic == vic) 801 return vmode->mode; 802 vmode++; 803 } 804 805 return NULL; 806 } 807 808 bool meson_venc_hdmi_venc_repeat(int vic) 809 { 810 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ 811 if (vic == 6 || vic == 7 || /* 480i */ 812 vic == 21 || vic == 22 || /* 576i */ 813 vic == 17 || vic == 18 || /* 576p */ 814 vic == 2 || vic == 3 || /* 480p */ 815 vic == 4 || /* 720p60 */ 816 vic == 19 || /* 720p50 */ 817 vic == 5 || /* 1080i60 */ 818 vic == 20) /* 1080i50 */ 819 return true; 820 821 return false; 822 } 823 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat); 824 825 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, 826 struct drm_display_mode *mode) 827 { 828 union meson_hdmi_venc_mode *vmode = NULL; 829 union meson_hdmi_venc_mode vmode_dmt; 830 bool use_enci = false; 831 bool venc_repeat = false; 832 bool hdmi_repeat = false; 833 unsigned int venc_hdmi_latency = 2; 834 unsigned long total_pixels_venc = 0; 835 unsigned long active_pixels_venc = 0; 836 unsigned long front_porch_venc = 0; 837 unsigned long hsync_pixels_venc = 0; 838 unsigned long de_h_begin = 0; 839 unsigned long de_h_end = 0; 840 unsigned long de_v_begin_even = 0; 841 unsigned long de_v_end_even = 0; 842 unsigned long de_v_begin_odd = 0; 843 unsigned long de_v_end_odd = 0; 844 unsigned long hs_begin = 0; 845 unsigned long hs_end = 0; 846 unsigned long vs_adjust = 0; 847 unsigned long vs_bline_evn = 0; 848 unsigned long vs_eline_evn = 0; 849 unsigned long vs_bline_odd = 0; 850 unsigned long vs_eline_odd = 0; 851 unsigned long vso_begin_evn = 0; 852 unsigned long vso_begin_odd = 0; 853 unsigned int eof_lines; 854 unsigned int sof_lines; 855 unsigned int vsync_lines; 856 857 /* Use VENCI for 480i and 576i and double HDMI pixels */ 858 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 859 hdmi_repeat = true; 860 use_enci = true; 861 venc_hdmi_latency = 1; 862 } 863 864 if (meson_venc_hdmi_supported_vic(vic)) { 865 vmode = meson_venc_hdmi_get_vic_vmode(vic); 866 if (!vmode) { 867 dev_err(priv->dev, "%s: Fatal Error, unsupported mode " 868 DRM_MODE_FMT "\n", __func__, 869 DRM_MODE_ARG(mode)); 870 return; 871 } 872 } else { 873 meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt); 874 vmode = &vmode_dmt; 875 use_enci = false; 876 } 877 878 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ 879 if (meson_venc_hdmi_venc_repeat(vic)) 880 venc_repeat = true; 881 882 eof_lines = mode->vsync_start - mode->vdisplay; 883 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 884 eof_lines /= 2; 885 sof_lines = mode->vtotal - mode->vsync_end; 886 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 887 sof_lines /= 2; 888 vsync_lines = mode->vsync_end - mode->vsync_start; 889 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 890 vsync_lines /= 2; 891 892 total_pixels_venc = mode->htotal; 893 if (hdmi_repeat) 894 total_pixels_venc /= 2; 895 if (venc_repeat) 896 total_pixels_venc *= 2; 897 898 active_pixels_venc = mode->hdisplay; 899 if (hdmi_repeat) 900 active_pixels_venc /= 2; 901 if (venc_repeat) 902 active_pixels_venc *= 2; 903 904 front_porch_venc = (mode->hsync_start - mode->hdisplay); 905 if (hdmi_repeat) 906 front_porch_venc /= 2; 907 if (venc_repeat) 908 front_porch_venc *= 2; 909 910 hsync_pixels_venc = (mode->hsync_end - mode->hsync_start); 911 if (hdmi_repeat) 912 hsync_pixels_venc /= 2; 913 if (venc_repeat) 914 hsync_pixels_venc *= 2; 915 916 /* Disable VDACs */ 917 writel_bits_relaxed(0xff, 0xff, 918 priv->io_base + _REG(VENC_VDAC_SETTING)); 919 920 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 921 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 922 923 if (use_enci) { 924 unsigned int lines_f0; 925 unsigned int lines_f1; 926 927 /* CVBS Filter settings */ 928 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 929 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 930 931 /* Digital Video Select : Interlace, clk27 clk, external */ 932 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); 933 934 /* Reset Video Mode */ 935 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); 936 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 937 938 /* Horizontal sync signal output */ 939 writel_relaxed(vmode->enci.hso_begin, 940 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); 941 writel_relaxed(vmode->enci.hso_end, 942 priv->io_base + _REG(ENCI_SYNC_HSO_END)); 943 944 /* Vertical Sync lines */ 945 writel_relaxed(vmode->enci.vso_even, 946 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN)); 947 writel_relaxed(vmode->enci.vso_odd, 948 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 949 950 /* Macrovision max amplitude change */ 951 writel_relaxed(vmode->enci.macv_max_amp, 952 priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 953 954 /* Video mode */ 955 writel_relaxed(vmode->enci.video_prog_mode, 956 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 957 writel_relaxed(vmode->enci.video_mode, 958 priv->io_base + _REG(ENCI_VIDEO_MODE)); 959 960 /* Advanced Video Mode : 961 * Demux shifting 0x2 962 * Blank line end at line17/22 963 * High bandwidth Luma Filter 964 * Low bandwidth Chroma Filter 965 * Bypass luma low pass filter 966 * No macrovision on CSYNC 967 */ 968 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 969 970 writel(vmode->enci.sch_adjust, 971 priv->io_base + _REG(ENCI_VIDEO_SCH)); 972 973 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */ 974 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE)); 975 976 if (vmode->enci.yc_delay) 977 writel_relaxed(vmode->enci.yc_delay, 978 priv->io_base + _REG(ENCI_YC_DELAY)); 979 980 981 /* UNreset Interlaced TV Encoder */ 982 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 983 984 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 985 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 986 987 /* Timings */ 988 writel_relaxed(vmode->enci.pixel_start, 989 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START)); 990 writel_relaxed(vmode->enci.pixel_end, 991 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END)); 992 993 writel_relaxed(vmode->enci.top_field_line_start, 994 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 995 writel_relaxed(vmode->enci.top_field_line_end, 996 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END)); 997 998 writel_relaxed(vmode->enci.bottom_field_line_start, 999 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1000 writel_relaxed(vmode->enci.bottom_field_line_end, 1001 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END)); 1002 1003 /* Select ENCI for VIU */ 1004 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1005 1006 /* Interlace video enable */ 1007 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1008 1009 lines_f0 = mode->vtotal >> 1; 1010 lines_f1 = lines_f0 + 1; 1011 1012 de_h_begin = modulo(readl_relaxed(priv->io_base + 1013 _REG(ENCI_VFIFO2VD_PIXEL_START)) 1014 + venc_hdmi_latency, 1015 total_pixels_venc); 1016 de_h_end = modulo(de_h_begin + active_pixels_venc, 1017 total_pixels_venc); 1018 1019 writel_relaxed(de_h_begin, 1020 priv->io_base + _REG(ENCI_DE_H_BEGIN)); 1021 writel_relaxed(de_h_end, 1022 priv->io_base + _REG(ENCI_DE_H_END)); 1023 1024 de_v_begin_even = readl_relaxed(priv->io_base + 1025 _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1026 de_v_end_even = de_v_begin_even + mode->vdisplay; 1027 de_v_begin_odd = readl_relaxed(priv->io_base + 1028 _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1029 de_v_end_odd = de_v_begin_odd + mode->vdisplay; 1030 1031 writel_relaxed(de_v_begin_even, 1032 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN)); 1033 writel_relaxed(de_v_end_even, 1034 priv->io_base + _REG(ENCI_DE_V_END_EVEN)); 1035 writel_relaxed(de_v_begin_odd, 1036 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD)); 1037 writel_relaxed(de_v_end_odd, 1038 priv->io_base + _REG(ENCI_DE_V_END_ODD)); 1039 1040 /* Program Hsync timing */ 1041 hs_begin = de_h_end + front_porch_venc; 1042 if (de_h_end + front_porch_venc >= total_pixels_venc) { 1043 hs_begin -= total_pixels_venc; 1044 vs_adjust = 1; 1045 } else { 1046 hs_begin = de_h_end + front_porch_venc; 1047 vs_adjust = 0; 1048 } 1049 1050 hs_end = modulo(hs_begin + hsync_pixels_venc, 1051 total_pixels_venc); 1052 writel_relaxed(hs_begin, 1053 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN)); 1054 writel_relaxed(hs_end, 1055 priv->io_base + _REG(ENCI_DVI_HSO_END)); 1056 1057 /* Program Vsync timing for even field */ 1058 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) { 1059 vs_bline_evn = (de_v_end_odd - 1) 1060 + eof_lines 1061 + vs_adjust 1062 - lines_f1; 1063 vs_eline_evn = vs_bline_evn + vsync_lines; 1064 1065 writel_relaxed(vs_bline_evn, 1066 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN)); 1067 1068 writel_relaxed(vs_eline_evn, 1069 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1070 1071 writel_relaxed(hs_begin, 1072 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN)); 1073 writel_relaxed(hs_begin, 1074 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN)); 1075 } else { 1076 vs_bline_odd = (de_v_end_odd - 1) 1077 + eof_lines 1078 + vs_adjust; 1079 1080 writel_relaxed(vs_bline_odd, 1081 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD)); 1082 1083 writel_relaxed(hs_begin, 1084 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD)); 1085 1086 if ((vs_bline_odd + vsync_lines) >= lines_f1) { 1087 vs_eline_evn = vs_bline_odd 1088 + vsync_lines 1089 - lines_f1; 1090 1091 writel_relaxed(vs_eline_evn, priv->io_base 1092 + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1093 1094 writel_relaxed(hs_begin, priv->io_base 1095 + _REG(ENCI_DVI_VSO_END_EVN)); 1096 } else { 1097 vs_eline_odd = vs_bline_odd 1098 + vsync_lines; 1099 1100 writel_relaxed(vs_eline_odd, priv->io_base 1101 + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1102 1103 writel_relaxed(hs_begin, priv->io_base 1104 + _REG(ENCI_DVI_VSO_END_ODD)); 1105 } 1106 } 1107 1108 /* Program Vsync timing for odd field */ 1109 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) { 1110 vs_bline_odd = (de_v_end_even - 1) 1111 + (eof_lines + 1) 1112 - lines_f0; 1113 vs_eline_odd = vs_bline_odd + vsync_lines; 1114 1115 writel_relaxed(vs_bline_odd, 1116 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD)); 1117 1118 writel_relaxed(vs_eline_odd, 1119 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1120 1121 vso_begin_odd = modulo(hs_begin 1122 + (total_pixels_venc >> 1), 1123 total_pixels_venc); 1124 1125 writel_relaxed(vso_begin_odd, 1126 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD)); 1127 writel_relaxed(vso_begin_odd, 1128 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD)); 1129 } else { 1130 vs_bline_evn = (de_v_end_even - 1) 1131 + (eof_lines + 1); 1132 1133 writel_relaxed(vs_bline_evn, 1134 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN)); 1135 1136 vso_begin_evn = modulo(hs_begin 1137 + (total_pixels_venc >> 1), 1138 total_pixels_venc); 1139 1140 writel_relaxed(vso_begin_evn, priv->io_base 1141 + _REG(ENCI_DVI_VSO_BEGIN_EVN)); 1142 1143 if (vs_bline_evn + vsync_lines >= lines_f0) { 1144 vs_eline_odd = vs_bline_evn 1145 + vsync_lines 1146 - lines_f0; 1147 1148 writel_relaxed(vs_eline_odd, priv->io_base 1149 + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1150 1151 writel_relaxed(vso_begin_evn, priv->io_base 1152 + _REG(ENCI_DVI_VSO_END_ODD)); 1153 } else { 1154 vs_eline_evn = vs_bline_evn + vsync_lines; 1155 1156 writel_relaxed(vs_eline_evn, priv->io_base 1157 + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1158 1159 writel_relaxed(vso_begin_evn, priv->io_base 1160 + _REG(ENCI_DVI_VSO_END_EVN)); 1161 } 1162 } 1163 } else { 1164 writel_relaxed(vmode->encp.dvi_settings, 1165 priv->io_base + _REG(VENC_DVI_SETTING)); 1166 writel_relaxed(vmode->encp.video_mode, 1167 priv->io_base + _REG(ENCP_VIDEO_MODE)); 1168 writel_relaxed(vmode->encp.video_mode_adv, 1169 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV)); 1170 if (vmode->encp.video_prog_mode_present) 1171 writel_relaxed(vmode->encp.video_prog_mode, 1172 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1173 if (vmode->encp.video_sync_mode_present) 1174 writel_relaxed(vmode->encp.video_sync_mode, 1175 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE)); 1176 if (vmode->encp.video_yc_dly_present) 1177 writel_relaxed(vmode->encp.video_yc_dly, 1178 priv->io_base + _REG(ENCP_VIDEO_YC_DLY)); 1179 if (vmode->encp.video_rgb_ctrl_present) 1180 writel_relaxed(vmode->encp.video_rgb_ctrl, 1181 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL)); 1182 if (vmode->encp.video_filt_ctrl_present) 1183 writel_relaxed(vmode->encp.video_filt_ctrl, 1184 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL)); 1185 if (vmode->encp.video_ofld_voav_ofst_present) 1186 writel_relaxed(vmode->encp.video_ofld_voav_ofst, 1187 priv->io_base 1188 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST)); 1189 writel_relaxed(vmode->encp.yfp1_htime, 1190 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME)); 1191 writel_relaxed(vmode->encp.yfp2_htime, 1192 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME)); 1193 writel_relaxed(vmode->encp.max_pxcnt, 1194 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT)); 1195 writel_relaxed(vmode->encp.hspuls_begin, 1196 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN)); 1197 writel_relaxed(vmode->encp.hspuls_end, 1198 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END)); 1199 writel_relaxed(vmode->encp.hspuls_switch, 1200 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH)); 1201 writel_relaxed(vmode->encp.vspuls_begin, 1202 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN)); 1203 writel_relaxed(vmode->encp.vspuls_end, 1204 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END)); 1205 writel_relaxed(vmode->encp.vspuls_bline, 1206 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE)); 1207 writel_relaxed(vmode->encp.vspuls_eline, 1208 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE)); 1209 if (vmode->encp.eqpuls_begin_present) 1210 writel_relaxed(vmode->encp.eqpuls_begin, 1211 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN)); 1212 if (vmode->encp.eqpuls_end_present) 1213 writel_relaxed(vmode->encp.eqpuls_end, 1214 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END)); 1215 if (vmode->encp.eqpuls_bline_present) 1216 writel_relaxed(vmode->encp.eqpuls_bline, 1217 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE)); 1218 if (vmode->encp.eqpuls_eline_present) 1219 writel_relaxed(vmode->encp.eqpuls_eline, 1220 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE)); 1221 writel_relaxed(vmode->encp.havon_begin, 1222 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN)); 1223 writel_relaxed(vmode->encp.havon_end, 1224 priv->io_base + _REG(ENCP_VIDEO_HAVON_END)); 1225 writel_relaxed(vmode->encp.vavon_bline, 1226 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE)); 1227 writel_relaxed(vmode->encp.vavon_eline, 1228 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE)); 1229 writel_relaxed(vmode->encp.hso_begin, 1230 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN)); 1231 writel_relaxed(vmode->encp.hso_end, 1232 priv->io_base + _REG(ENCP_VIDEO_HSO_END)); 1233 writel_relaxed(vmode->encp.vso_begin, 1234 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN)); 1235 writel_relaxed(vmode->encp.vso_end, 1236 priv->io_base + _REG(ENCP_VIDEO_VSO_END)); 1237 writel_relaxed(vmode->encp.vso_bline, 1238 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE)); 1239 if (vmode->encp.vso_eline_present) 1240 writel_relaxed(vmode->encp.vso_eline, 1241 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE)); 1242 if (vmode->encp.sy_val_present) 1243 writel_relaxed(vmode->encp.sy_val, 1244 priv->io_base + _REG(ENCP_VIDEO_SY_VAL)); 1245 if (vmode->encp.sy2_val_present) 1246 writel_relaxed(vmode->encp.sy2_val, 1247 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL)); 1248 writel_relaxed(vmode->encp.max_lncnt, 1249 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT)); 1250 1251 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); 1252 1253 /* Set DE signal’s polarity is active high */ 1254 writel_bits_relaxed(BIT(14), BIT(14), 1255 priv->io_base + _REG(ENCP_VIDEO_MODE)); 1256 1257 /* Program DE timing */ 1258 de_h_begin = modulo(readl_relaxed(priv->io_base + 1259 _REG(ENCP_VIDEO_HAVON_BEGIN)) 1260 + venc_hdmi_latency, 1261 total_pixels_venc); 1262 de_h_end = modulo(de_h_begin + active_pixels_venc, 1263 total_pixels_venc); 1264 1265 writel_relaxed(de_h_begin, 1266 priv->io_base + _REG(ENCP_DE_H_BEGIN)); 1267 writel_relaxed(de_h_end, 1268 priv->io_base + _REG(ENCP_DE_H_END)); 1269 1270 /* Program DE timing for even field */ 1271 de_v_begin_even = readl_relaxed(priv->io_base 1272 + _REG(ENCP_VIDEO_VAVON_BLINE)); 1273 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1274 de_v_end_even = de_v_begin_even + 1275 (mode->vdisplay / 2); 1276 else 1277 de_v_end_even = de_v_begin_even + mode->vdisplay; 1278 1279 writel_relaxed(de_v_begin_even, 1280 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN)); 1281 writel_relaxed(de_v_end_even, 1282 priv->io_base + _REG(ENCP_DE_V_END_EVEN)); 1283 1284 /* Program DE timing for odd field if needed */ 1285 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1286 unsigned int ofld_voav_ofst = 1287 readl_relaxed(priv->io_base + 1288 _REG(ENCP_VIDEO_OFLD_VOAV_OFST)); 1289 de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4) 1290 + de_v_begin_even 1291 + ((mode->vtotal - 1) / 2); 1292 de_v_end_odd = de_v_begin_odd + (mode->vdisplay / 2); 1293 1294 writel_relaxed(de_v_begin_odd, 1295 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD)); 1296 writel_relaxed(de_v_end_odd, 1297 priv->io_base + _REG(ENCP_DE_V_END_ODD)); 1298 } 1299 1300 /* Program Hsync timing */ 1301 if ((de_h_end + front_porch_venc) >= total_pixels_venc) { 1302 hs_begin = de_h_end 1303 + front_porch_venc 1304 - total_pixels_venc; 1305 vs_adjust = 1; 1306 } else { 1307 hs_begin = de_h_end 1308 + front_porch_venc; 1309 vs_adjust = 0; 1310 } 1311 1312 hs_end = modulo(hs_begin + hsync_pixels_venc, 1313 total_pixels_venc); 1314 1315 writel_relaxed(hs_begin, 1316 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN)); 1317 writel_relaxed(hs_end, 1318 priv->io_base + _REG(ENCP_DVI_HSO_END)); 1319 1320 /* Program Vsync timing for even field */ 1321 if (de_v_begin_even >= 1322 (sof_lines + vsync_lines + (1 - vs_adjust))) 1323 vs_bline_evn = de_v_begin_even 1324 - sof_lines 1325 - vsync_lines 1326 - (1 - vs_adjust); 1327 else 1328 vs_bline_evn = mode->vtotal 1329 + de_v_begin_even 1330 - sof_lines 1331 - vsync_lines 1332 - (1 - vs_adjust); 1333 1334 vs_eline_evn = modulo(vs_bline_evn + vsync_lines, 1335 mode->vtotal); 1336 1337 writel_relaxed(vs_bline_evn, 1338 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN)); 1339 writel_relaxed(vs_eline_evn, 1340 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN)); 1341 1342 vso_begin_evn = hs_begin; 1343 writel_relaxed(vso_begin_evn, 1344 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN)); 1345 writel_relaxed(vso_begin_evn, 1346 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN)); 1347 1348 /* Program Vsync timing for odd field if needed */ 1349 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1350 vs_bline_odd = (de_v_begin_odd - 1) 1351 - sof_lines 1352 - vsync_lines; 1353 vs_eline_odd = (de_v_begin_odd - 1) 1354 - vsync_lines; 1355 vso_begin_odd = modulo(hs_begin 1356 + (total_pixels_venc >> 1), 1357 total_pixels_venc); 1358 1359 writel_relaxed(vs_bline_odd, 1360 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD)); 1361 writel_relaxed(vs_eline_odd, 1362 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD)); 1363 writel_relaxed(vso_begin_odd, 1364 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD)); 1365 writel_relaxed(vso_begin_odd, 1366 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD)); 1367 } 1368 1369 /* Select ENCP for VIU */ 1370 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP); 1371 } 1372 1373 writel_relaxed((use_enci ? 1 : 2) | 1374 (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) | 1375 (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) | 1376 4 << 5 | 1377 (venc_repeat ? 1 << 8 : 0) | 1378 (hdmi_repeat ? 1 << 12 : 0), 1379 priv->io_base + _REG(VPU_HDMI_SETTING)); 1380 1381 priv->venc.hdmi_repeat = hdmi_repeat; 1382 priv->venc.venc_repeat = venc_repeat; 1383 priv->venc.hdmi_use_enci = use_enci; 1384 1385 priv->venc.current_mode = MESON_VENC_MODE_HDMI; 1386 } 1387 EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set); 1388 1389 void meson_venci_cvbs_mode_set(struct meson_drm *priv, 1390 struct meson_cvbs_enci_mode *mode) 1391 { 1392 if (mode->mode_tag == priv->venc.current_mode) 1393 return; 1394 1395 /* CVBS Filter settings */ 1396 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 1397 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1398 1399 /* Digital Video Select : Interlace, clk27 clk, external */ 1400 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); 1401 1402 /* Reset Video Mode */ 1403 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); 1404 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1405 1406 /* Horizontal sync signal output */ 1407 writel_relaxed(mode->hso_begin, 1408 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); 1409 writel_relaxed(mode->hso_end, 1410 priv->io_base + _REG(ENCI_SYNC_HSO_END)); 1411 1412 /* Vertical Sync lines */ 1413 writel_relaxed(mode->vso_even, 1414 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN)); 1415 writel_relaxed(mode->vso_odd, 1416 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 1417 1418 /* Macrovision max amplitude change */ 1419 writel_relaxed(0x8100 + mode->macv_max_amp, 1420 priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1421 1422 /* Video mode */ 1423 writel_relaxed(mode->video_prog_mode, 1424 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1425 writel_relaxed(mode->video_mode, 1426 priv->io_base + _REG(ENCI_VIDEO_MODE)); 1427 1428 /* Advanced Video Mode : 1429 * Demux shifting 0x2 1430 * Blank line end at line17/22 1431 * High bandwidth Luma Filter 1432 * Low bandwidth Chroma Filter 1433 * Bypass luma low pass filter 1434 * No macrovision on CSYNC 1435 */ 1436 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1437 1438 writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH)); 1439 1440 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */ 1441 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE)); 1442 1443 /* 0x3 Y, C, and Component Y delay */ 1444 writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY)); 1445 1446 /* Timings */ 1447 writel_relaxed(mode->pixel_start, 1448 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START)); 1449 writel_relaxed(mode->pixel_end, 1450 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END)); 1451 1452 writel_relaxed(mode->top_field_line_start, 1453 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1454 writel_relaxed(mode->top_field_line_end, 1455 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END)); 1456 1457 writel_relaxed(mode->bottom_field_line_start, 1458 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1459 writel_relaxed(mode->bottom_field_line_end, 1460 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END)); 1461 1462 /* Internal Venc, Internal VIU Sync, Internal Vencoder */ 1463 writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE)); 1464 1465 /* UNreset Interlaced TV Encoder */ 1466 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 1467 1468 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 1469 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1470 1471 /* Power UP Dacs */ 1472 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING)); 1473 1474 /* Video Upsampling */ 1475 writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0)); 1476 writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1)); 1477 writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2)); 1478 1479 /* Select Interlace Y DACs */ 1480 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0)); 1481 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1)); 1482 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2)); 1483 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3)); 1484 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4)); 1485 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5)); 1486 1487 /* Select ENCI for VIU */ 1488 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1489 1490 /* Enable ENCI FIFO */ 1491 writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL)); 1492 1493 /* Select ENCI DACs 0, 1, 4, and 5 */ 1494 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0)); 1495 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1)); 1496 1497 /* Interlace video enable */ 1498 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1499 1500 /* Configure Video Saturation / Contrast / Brightness / Hue */ 1501 writel_relaxed(mode->video_saturation, 1502 priv->io_base + _REG(ENCI_VIDEO_SAT)); 1503 writel_relaxed(mode->video_contrast, 1504 priv->io_base + _REG(ENCI_VIDEO_CONT)); 1505 writel_relaxed(mode->video_brightness, 1506 priv->io_base + _REG(ENCI_VIDEO_BRIGHT)); 1507 writel_relaxed(mode->video_hue, 1508 priv->io_base + _REG(ENCI_VIDEO_HUE)); 1509 1510 /* Enable DAC0 Filter */ 1511 writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0)); 1512 writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1)); 1513 1514 /* 0 in Macrovision register 0 */ 1515 writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0)); 1516 1517 /* Analog Synchronization and color burst value adjust */ 1518 writel_relaxed(mode->analog_sync_adj, 1519 priv->io_base + _REG(ENCI_SYNC_ADJ)); 1520 1521 priv->venc.current_mode = mode->mode_tag; 1522 } 1523 1524 /* Returns the current ENCI field polarity */ 1525 unsigned int meson_venci_get_field(struct meson_drm *priv) 1526 { 1527 return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29); 1528 } 1529 1530 void meson_venc_enable_vsync(struct meson_drm *priv) 1531 { 1532 writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL)); 1533 } 1534 1535 void meson_venc_disable_vsync(struct meson_drm *priv) 1536 { 1537 writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL)); 1538 } 1539 1540 void meson_venc_init(struct meson_drm *priv) 1541 { 1542 /* Disable CVBS VDAC */ 1543 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); 1544 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); 1545 1546 /* Power Down Dacs */ 1547 writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); 1548 1549 /* Disable HDMI PHY */ 1550 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); 1551 1552 /* Disable HDMI */ 1553 writel_bits_relaxed(0x3, 0, 1554 priv->io_base + _REG(VPU_HDMI_SETTING)); 1555 1556 /* Disable all encoders */ 1557 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 1558 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 1559 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); 1560 1561 /* Disable VSync IRQ */ 1562 meson_venc_disable_vsync(priv); 1563 1564 priv->venc.current_mode = MESON_VENC_MODE_NONE; 1565 } 1566