1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <drm/drmP.h> 23 #include "meson_drv.h" 24 #include "meson_venc.h" 25 #include "meson_vpp.h" 26 #include "meson_vclk.h" 27 #include "meson_registers.h" 28 29 /** 30 * DOC: Video Encoder 31 * 32 * VENC Handle the pixels encoding to the output formats. 33 * We handle the following encodings : 34 * 35 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter 36 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP 37 * - Setup of more clock rates for HDMI modes 38 * 39 * What is missing : 40 * 41 * - LCD Panel encoding via ENCL 42 * - TV Panel encoding via ENCT 43 * 44 * VENC paths : 45 * 46 * .. code:: 47 * 48 * _____ _____ ____________________ 49 * vd1---| |-| | | VENC /---------|----VDAC 50 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-| 51 * osd1--| |-| | | \ | X--HDMI-TX 52 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-| 53 * | | | 54 * | \--ENCL-----------|----LVDS 55 * |____________________| 56 * 57 * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC 58 * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI. 59 * The ENCP is designed for Progressive encoding but can also generate 60 * 1080i interlaced pixels, and was initialy desined to encode pixels for 61 * VDAC to output RGB ou YUV analog outputs. 62 * It's output is only used through the ENCP_DVI encoder for HDMI. 63 * The ENCL LVDS encoder is not implemented. 64 * 65 * The ENCI and ENCP encoders needs specially defined parameters for each 66 * supported mode and thus cannot be determined from standard video timings. 67 * 68 * The ENCI end ENCP DVI encoders are more generic and can generate any timings 69 * from the pixel data generated by ENCI or ENCP, so can use the standard video 70 * timings are source for HW parameters. 71 */ 72 73 /* HHI Registers */ 74 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 75 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ 76 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ 77 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */ 78 79 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = { 80 .mode_tag = MESON_VENC_MODE_CVBS_PAL, 81 .hso_begin = 3, 82 .hso_end = 129, 83 .vso_even = 3, 84 .vso_odd = 260, 85 .macv_max_amp = 7, 86 .video_prog_mode = 0xff, 87 .video_mode = 0x13, 88 .sch_adjust = 0x28, 89 .yc_delay = 0x343, 90 .pixel_start = 251, 91 .pixel_end = 1691, 92 .top_field_line_start = 22, 93 .top_field_line_end = 310, 94 .bottom_field_line_start = 23, 95 .bottom_field_line_end = 311, 96 .video_saturation = 9, 97 .video_contrast = 0, 98 .video_brightness = 0, 99 .video_hue = 0, 100 .analog_sync_adj = 0x8080, 101 }; 102 103 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = { 104 .mode_tag = MESON_VENC_MODE_CVBS_NTSC, 105 .hso_begin = 5, 106 .hso_end = 129, 107 .vso_even = 3, 108 .vso_odd = 260, 109 .macv_max_amp = 0xb, 110 .video_prog_mode = 0xf0, 111 .video_mode = 0x8, 112 .sch_adjust = 0x20, 113 .yc_delay = 0x333, 114 .pixel_start = 227, 115 .pixel_end = 1667, 116 .top_field_line_start = 18, 117 .top_field_line_end = 258, 118 .bottom_field_line_start = 19, 119 .bottom_field_line_end = 259, 120 .video_saturation = 18, 121 .video_contrast = 3, 122 .video_brightness = 0, 123 .video_hue = 0, 124 .analog_sync_adj = 0x9c00, 125 }; 126 127 union meson_hdmi_venc_mode { 128 struct { 129 unsigned int mode_tag; 130 unsigned int hso_begin; 131 unsigned int hso_end; 132 unsigned int vso_even; 133 unsigned int vso_odd; 134 unsigned int macv_max_amp; 135 unsigned int video_prog_mode; 136 unsigned int video_mode; 137 unsigned int sch_adjust; 138 unsigned int yc_delay; 139 unsigned int pixel_start; 140 unsigned int pixel_end; 141 unsigned int top_field_line_start; 142 unsigned int top_field_line_end; 143 unsigned int bottom_field_line_start; 144 unsigned int bottom_field_line_end; 145 } enci; 146 struct { 147 unsigned int dvi_settings; 148 unsigned int video_mode; 149 unsigned int video_mode_adv; 150 unsigned int video_prog_mode; 151 bool video_prog_mode_present; 152 unsigned int video_sync_mode; 153 bool video_sync_mode_present; 154 unsigned int video_yc_dly; 155 bool video_yc_dly_present; 156 unsigned int video_rgb_ctrl; 157 bool video_rgb_ctrl_present; 158 unsigned int video_filt_ctrl; 159 bool video_filt_ctrl_present; 160 unsigned int video_ofld_voav_ofst; 161 bool video_ofld_voav_ofst_present; 162 unsigned int yfp1_htime; 163 unsigned int yfp2_htime; 164 unsigned int max_pxcnt; 165 unsigned int hspuls_begin; 166 unsigned int hspuls_end; 167 unsigned int hspuls_switch; 168 unsigned int vspuls_begin; 169 unsigned int vspuls_end; 170 unsigned int vspuls_bline; 171 unsigned int vspuls_eline; 172 unsigned int eqpuls_begin; 173 bool eqpuls_begin_present; 174 unsigned int eqpuls_end; 175 bool eqpuls_end_present; 176 unsigned int eqpuls_bline; 177 bool eqpuls_bline_present; 178 unsigned int eqpuls_eline; 179 bool eqpuls_eline_present; 180 unsigned int havon_begin; 181 unsigned int havon_end; 182 unsigned int vavon_bline; 183 unsigned int vavon_eline; 184 unsigned int hso_begin; 185 unsigned int hso_end; 186 unsigned int vso_begin; 187 unsigned int vso_end; 188 unsigned int vso_bline; 189 unsigned int vso_eline; 190 bool vso_eline_present; 191 unsigned int sy_val; 192 bool sy_val_present; 193 unsigned int sy2_val; 194 bool sy2_val_present; 195 unsigned int max_lncnt; 196 } encp; 197 }; 198 199 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = { 200 .enci = { 201 .hso_begin = 5, 202 .hso_end = 129, 203 .vso_even = 3, 204 .vso_odd = 260, 205 .macv_max_amp = 0x810b, 206 .video_prog_mode = 0xf0, 207 .video_mode = 0x8, 208 .sch_adjust = 0x20, 209 .yc_delay = 0, 210 .pixel_start = 227, 211 .pixel_end = 1667, 212 .top_field_line_start = 18, 213 .top_field_line_end = 258, 214 .bottom_field_line_start = 19, 215 .bottom_field_line_end = 259, 216 }, 217 }; 218 219 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = { 220 .enci = { 221 .hso_begin = 3, 222 .hso_end = 129, 223 .vso_even = 3, 224 .vso_odd = 260, 225 .macv_max_amp = 8107, 226 .video_prog_mode = 0xff, 227 .video_mode = 0x13, 228 .sch_adjust = 0x28, 229 .yc_delay = 0x333, 230 .pixel_start = 251, 231 .pixel_end = 1691, 232 .top_field_line_start = 22, 233 .top_field_line_end = 310, 234 .bottom_field_line_start = 23, 235 .bottom_field_line_end = 311, 236 }, 237 }; 238 239 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = { 240 .encp = { 241 .dvi_settings = 0x21, 242 .video_mode = 0x4000, 243 .video_mode_adv = 0x9, 244 .video_prog_mode = 0, 245 .video_prog_mode_present = true, 246 .video_sync_mode = 7, 247 .video_sync_mode_present = true, 248 /* video_yc_dly */ 249 /* video_rgb_ctrl */ 250 .video_filt_ctrl = 0x2052, 251 .video_filt_ctrl_present = true, 252 /* video_ofld_voav_ofst */ 253 .yfp1_htime = 244, 254 .yfp2_htime = 1630, 255 .max_pxcnt = 1715, 256 .hspuls_begin = 0x22, 257 .hspuls_end = 0xa0, 258 .hspuls_switch = 88, 259 .vspuls_begin = 0, 260 .vspuls_end = 1589, 261 .vspuls_bline = 0, 262 .vspuls_eline = 5, 263 .havon_begin = 249, 264 .havon_end = 1689, 265 .vavon_bline = 42, 266 .vavon_eline = 521, 267 /* eqpuls_begin */ 268 /* eqpuls_end */ 269 /* eqpuls_bline */ 270 /* eqpuls_eline */ 271 .hso_begin = 3, 272 .hso_end = 5, 273 .vso_begin = 3, 274 .vso_end = 5, 275 .vso_bline = 0, 276 /* vso_eline */ 277 .sy_val = 8, 278 .sy_val_present = true, 279 .sy2_val = 0x1d8, 280 .sy2_val_present = true, 281 .max_lncnt = 524, 282 }, 283 }; 284 285 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = { 286 .encp = { 287 .dvi_settings = 0x21, 288 .video_mode = 0x4000, 289 .video_mode_adv = 0x9, 290 .video_prog_mode = 0, 291 .video_prog_mode_present = true, 292 .video_sync_mode = 7, 293 .video_sync_mode_present = true, 294 /* video_yc_dly */ 295 /* video_rgb_ctrl */ 296 .video_filt_ctrl = 0x52, 297 .video_filt_ctrl_present = true, 298 /* video_ofld_voav_ofst */ 299 .yfp1_htime = 235, 300 .yfp2_htime = 1674, 301 .max_pxcnt = 1727, 302 .hspuls_begin = 0, 303 .hspuls_end = 0x80, 304 .hspuls_switch = 88, 305 .vspuls_begin = 0, 306 .vspuls_end = 1599, 307 .vspuls_bline = 0, 308 .vspuls_eline = 4, 309 .havon_begin = 235, 310 .havon_end = 1674, 311 .vavon_bline = 44, 312 .vavon_eline = 619, 313 /* eqpuls_begin */ 314 /* eqpuls_end */ 315 /* eqpuls_bline */ 316 /* eqpuls_eline */ 317 .hso_begin = 0x80, 318 .hso_end = 0, 319 .vso_begin = 0, 320 .vso_end = 5, 321 .vso_bline = 0, 322 /* vso_eline */ 323 .sy_val = 8, 324 .sy_val_present = true, 325 .sy2_val = 0x1d8, 326 .sy2_val_present = true, 327 .max_lncnt = 624, 328 }, 329 }; 330 331 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = { 332 .encp = { 333 .dvi_settings = 0x2029, 334 .video_mode = 0x4040, 335 .video_mode_adv = 0x19, 336 /* video_prog_mode */ 337 /* video_sync_mode */ 338 /* video_yc_dly */ 339 /* video_rgb_ctrl */ 340 /* video_filt_ctrl */ 341 /* video_ofld_voav_ofst */ 342 .yfp1_htime = 648, 343 .yfp2_htime = 3207, 344 .max_pxcnt = 3299, 345 .hspuls_begin = 80, 346 .hspuls_end = 240, 347 .hspuls_switch = 80, 348 .vspuls_begin = 688, 349 .vspuls_end = 3248, 350 .vspuls_bline = 4, 351 .vspuls_eline = 8, 352 .havon_begin = 648, 353 .havon_end = 3207, 354 .vavon_bline = 29, 355 .vavon_eline = 748, 356 /* eqpuls_begin */ 357 /* eqpuls_end */ 358 /* eqpuls_bline */ 359 /* eqpuls_eline */ 360 .hso_begin = 256, 361 .hso_end = 168, 362 .vso_begin = 168, 363 .vso_end = 256, 364 .vso_bline = 0, 365 .vso_eline = 5, 366 .vso_eline_present = true, 367 /* sy_val */ 368 /* sy2_val */ 369 .max_lncnt = 749, 370 }, 371 }; 372 373 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = { 374 .encp = { 375 .dvi_settings = 0x202d, 376 .video_mode = 0x4040, 377 .video_mode_adv = 0x19, 378 .video_prog_mode = 0x100, 379 .video_prog_mode_present = true, 380 .video_sync_mode = 0x407, 381 .video_sync_mode_present = true, 382 .video_yc_dly = 0, 383 .video_yc_dly_present = true, 384 /* video_rgb_ctrl */ 385 /* video_filt_ctrl */ 386 /* video_ofld_voav_ofst */ 387 .yfp1_htime = 648, 388 .yfp2_htime = 3207, 389 .max_pxcnt = 3959, 390 .hspuls_begin = 80, 391 .hspuls_end = 240, 392 .hspuls_switch = 80, 393 .vspuls_begin = 688, 394 .vspuls_end = 3248, 395 .vspuls_bline = 4, 396 .vspuls_eline = 8, 397 .havon_begin = 648, 398 .havon_end = 3207, 399 .vavon_bline = 29, 400 .vavon_eline = 748, 401 /* eqpuls_begin */ 402 /* eqpuls_end */ 403 /* eqpuls_bline */ 404 /* eqpuls_eline */ 405 .hso_begin = 128, 406 .hso_end = 208, 407 .vso_begin = 128, 408 .vso_end = 128, 409 .vso_bline = 0, 410 .vso_eline = 5, 411 .vso_eline_present = true, 412 /* sy_val */ 413 /* sy2_val */ 414 .max_lncnt = 749, 415 }, 416 }; 417 418 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = { 419 .encp = { 420 .dvi_settings = 0x2029, 421 .video_mode = 0x5ffc, 422 .video_mode_adv = 0x19, 423 .video_prog_mode = 0x100, 424 .video_prog_mode_present = true, 425 .video_sync_mode = 0x207, 426 .video_sync_mode_present = true, 427 /* video_yc_dly */ 428 /* video_rgb_ctrl */ 429 /* video_filt_ctrl */ 430 .video_ofld_voav_ofst = 0x11, 431 .video_ofld_voav_ofst_present = true, 432 .yfp1_htime = 516, 433 .yfp2_htime = 4355, 434 .max_pxcnt = 4399, 435 .hspuls_begin = 88, 436 .hspuls_end = 264, 437 .hspuls_switch = 88, 438 .vspuls_begin = 440, 439 .vspuls_end = 2200, 440 .vspuls_bline = 0, 441 .vspuls_eline = 4, 442 .havon_begin = 516, 443 .havon_end = 4355, 444 .vavon_bline = 20, 445 .vavon_eline = 559, 446 .eqpuls_begin = 2288, 447 .eqpuls_begin_present = true, 448 .eqpuls_end = 2464, 449 .eqpuls_end_present = true, 450 .eqpuls_bline = 0, 451 .eqpuls_bline_present = true, 452 .eqpuls_eline = 4, 453 .eqpuls_eline_present = true, 454 .hso_begin = 264, 455 .hso_end = 176, 456 .vso_begin = 88, 457 .vso_end = 88, 458 .vso_bline = 0, 459 .vso_eline = 5, 460 .vso_eline_present = true, 461 /* sy_val */ 462 /* sy2_val */ 463 .max_lncnt = 1124, 464 }, 465 }; 466 467 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = { 468 .encp = { 469 .dvi_settings = 0x202d, 470 .video_mode = 0x5ffc, 471 .video_mode_adv = 0x19, 472 .video_prog_mode = 0x100, 473 .video_prog_mode_present = true, 474 .video_sync_mode = 0x7, 475 .video_sync_mode_present = true, 476 /* video_yc_dly */ 477 /* video_rgb_ctrl */ 478 /* video_filt_ctrl */ 479 .video_ofld_voav_ofst = 0x11, 480 .video_ofld_voav_ofst_present = true, 481 .yfp1_htime = 526, 482 .yfp2_htime = 4365, 483 .max_pxcnt = 5279, 484 .hspuls_begin = 88, 485 .hspuls_end = 264, 486 .hspuls_switch = 88, 487 .vspuls_begin = 440, 488 .vspuls_end = 2200, 489 .vspuls_bline = 0, 490 .vspuls_eline = 4, 491 .havon_begin = 526, 492 .havon_end = 4365, 493 .vavon_bline = 20, 494 .vavon_eline = 559, 495 .eqpuls_begin = 2288, 496 .eqpuls_begin_present = true, 497 .eqpuls_end = 2464, 498 .eqpuls_end_present = true, 499 .eqpuls_bline = 0, 500 .eqpuls_bline_present = true, 501 .eqpuls_eline = 4, 502 .eqpuls_eline_present = true, 503 .hso_begin = 142, 504 .hso_end = 230, 505 .vso_begin = 142, 506 .vso_end = 142, 507 .vso_bline = 0, 508 .vso_eline = 5, 509 .vso_eline_present = true, 510 /* sy_val */ 511 /* sy2_val */ 512 .max_lncnt = 1124, 513 }, 514 }; 515 516 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = { 517 .encp = { 518 .dvi_settings = 0xd, 519 .video_mode = 0x4040, 520 .video_mode_adv = 0x18, 521 .video_prog_mode = 0x100, 522 .video_prog_mode_present = true, 523 .video_sync_mode = 0x7, 524 .video_sync_mode_present = true, 525 .video_yc_dly = 0, 526 .video_yc_dly_present = true, 527 .video_rgb_ctrl = 2, 528 .video_rgb_ctrl_present = true, 529 .video_filt_ctrl = 0x1052, 530 .video_filt_ctrl_present = true, 531 /* video_ofld_voav_ofst */ 532 .yfp1_htime = 271, 533 .yfp2_htime = 2190, 534 .max_pxcnt = 2749, 535 .hspuls_begin = 44, 536 .hspuls_end = 132, 537 .hspuls_switch = 44, 538 .vspuls_begin = 220, 539 .vspuls_end = 2140, 540 .vspuls_bline = 0, 541 .vspuls_eline = 4, 542 .havon_begin = 271, 543 .havon_end = 2190, 544 .vavon_bline = 41, 545 .vavon_eline = 1120, 546 /* eqpuls_begin */ 547 /* eqpuls_end */ 548 .eqpuls_bline = 0, 549 .eqpuls_bline_present = true, 550 .eqpuls_eline = 4, 551 .eqpuls_eline_present = true, 552 .hso_begin = 79, 553 .hso_end = 123, 554 .vso_begin = 79, 555 .vso_end = 79, 556 .vso_bline = 0, 557 .vso_eline = 5, 558 .vso_eline_present = true, 559 /* sy_val */ 560 /* sy2_val */ 561 .max_lncnt = 1124, 562 }, 563 }; 564 565 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = { 566 .encp = { 567 .dvi_settings = 0x1, 568 .video_mode = 0x4040, 569 .video_mode_adv = 0x18, 570 .video_prog_mode = 0x100, 571 .video_prog_mode_present = true, 572 /* video_sync_mode */ 573 /* video_yc_dly */ 574 /* video_rgb_ctrl */ 575 .video_filt_ctrl = 0x1052, 576 .video_filt_ctrl_present = true, 577 /* video_ofld_voav_ofst */ 578 .yfp1_htime = 140, 579 .yfp2_htime = 2060, 580 .max_pxcnt = 2199, 581 .hspuls_begin = 2156, 582 .hspuls_end = 44, 583 .hspuls_switch = 44, 584 .vspuls_begin = 140, 585 .vspuls_end = 2059, 586 .vspuls_bline = 0, 587 .vspuls_eline = 4, 588 .havon_begin = 148, 589 .havon_end = 2067, 590 .vavon_bline = 41, 591 .vavon_eline = 1120, 592 /* eqpuls_begin */ 593 /* eqpuls_end */ 594 /* eqpuls_bline */ 595 /* eqpuls_eline */ 596 .hso_begin = 44, 597 .hso_end = 2156, 598 .vso_begin = 2100, 599 .vso_end = 2164, 600 .vso_bline = 0, 601 .vso_eline = 5, 602 .vso_eline_present = true, 603 /* sy_val */ 604 /* sy2_val */ 605 .max_lncnt = 1124, 606 }, 607 }; 608 609 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = { 610 .encp = { 611 .dvi_settings = 0xd, 612 .video_mode = 0x4040, 613 .video_mode_adv = 0x18, 614 .video_prog_mode = 0x100, 615 .video_prog_mode_present = true, 616 .video_sync_mode = 0x7, 617 .video_sync_mode_present = true, 618 .video_yc_dly = 0, 619 .video_yc_dly_present = true, 620 .video_rgb_ctrl = 2, 621 .video_rgb_ctrl_present = true, 622 /* video_filt_ctrl */ 623 /* video_ofld_voav_ofst */ 624 .yfp1_htime = 271, 625 .yfp2_htime = 2190, 626 .max_pxcnt = 2639, 627 .hspuls_begin = 44, 628 .hspuls_end = 132, 629 .hspuls_switch = 44, 630 .vspuls_begin = 220, 631 .vspuls_end = 2140, 632 .vspuls_bline = 0, 633 .vspuls_eline = 4, 634 .havon_begin = 271, 635 .havon_end = 2190, 636 .vavon_bline = 41, 637 .vavon_eline = 1120, 638 /* eqpuls_begin */ 639 /* eqpuls_end */ 640 .eqpuls_bline = 0, 641 .eqpuls_bline_present = true, 642 .eqpuls_eline = 4, 643 .eqpuls_eline_present = true, 644 .hso_begin = 79, 645 .hso_end = 123, 646 .vso_begin = 79, 647 .vso_end = 79, 648 .vso_bline = 0, 649 .vso_eline = 5, 650 .vso_eline_present = true, 651 /* sy_val */ 652 /* sy2_val */ 653 .max_lncnt = 1124, 654 }, 655 }; 656 657 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = { 658 .encp = { 659 .dvi_settings = 0x1, 660 .video_mode = 0x4040, 661 .video_mode_adv = 0x18, 662 .video_prog_mode = 0x100, 663 .video_prog_mode_present = true, 664 /* video_sync_mode */ 665 /* video_yc_dly */ 666 /* video_rgb_ctrl */ 667 .video_filt_ctrl = 0x1052, 668 .video_filt_ctrl_present = true, 669 /* video_ofld_voav_ofst */ 670 .yfp1_htime = 140, 671 .yfp2_htime = 2060, 672 .max_pxcnt = 2199, 673 .hspuls_begin = 2156, 674 .hspuls_end = 44, 675 .hspuls_switch = 44, 676 .vspuls_begin = 140, 677 .vspuls_end = 2059, 678 .vspuls_bline = 0, 679 .vspuls_eline = 4, 680 .havon_begin = 148, 681 .havon_end = 2067, 682 .vavon_bline = 41, 683 .vavon_eline = 1120, 684 /* eqpuls_begin */ 685 /* eqpuls_end */ 686 /* eqpuls_bline */ 687 /* eqpuls_eline */ 688 .hso_begin = 44, 689 .hso_end = 2156, 690 .vso_begin = 2100, 691 .vso_end = 2164, 692 .vso_bline = 0, 693 .vso_eline = 5, 694 .vso_eline_present = true, 695 /* sy_val */ 696 /* sy2_val */ 697 .max_lncnt = 1124, 698 }, 699 }; 700 701 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = { 702 .encp = { 703 .dvi_settings = 0x1, 704 .video_mode = 0x4040, 705 .video_mode_adv = 0x8, 706 /* video_sync_mode */ 707 /* video_yc_dly */ 708 /* video_rgb_ctrl */ 709 .video_filt_ctrl = 0x1000, 710 .video_filt_ctrl_present = true, 711 /* video_ofld_voav_ofst */ 712 .yfp1_htime = 140, 713 .yfp2_htime = 140+3840, 714 .max_pxcnt = 3840+1660-1, 715 .hspuls_begin = 2156+1920, 716 .hspuls_end = 44, 717 .hspuls_switch = 44, 718 .vspuls_begin = 140, 719 .vspuls_end = 2059+1920, 720 .vspuls_bline = 0, 721 .vspuls_eline = 4, 722 .havon_begin = 148, 723 .havon_end = 3987, 724 .vavon_bline = 89, 725 .vavon_eline = 2248, 726 /* eqpuls_begin */ 727 /* eqpuls_end */ 728 /* eqpuls_bline */ 729 /* eqpuls_eline */ 730 .hso_begin = 44, 731 .hso_end = 2156+1920, 732 .vso_begin = 2100+1920, 733 .vso_end = 2164+1920, 734 .vso_bline = 51, 735 .vso_eline = 53, 736 .vso_eline_present = true, 737 /* sy_val */ 738 /* sy2_val */ 739 .max_lncnt = 2249, 740 }, 741 }; 742 743 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = { 744 .encp = { 745 .dvi_settings = 0x1, 746 .video_mode = 0x4040, 747 .video_mode_adv = 0x8, 748 /* video_sync_mode */ 749 /* video_yc_dly */ 750 /* video_rgb_ctrl */ 751 .video_filt_ctrl = 0x1000, 752 .video_filt_ctrl_present = true, 753 /* video_ofld_voav_ofst */ 754 .yfp1_htime = 140, 755 .yfp2_htime = 140+3840, 756 .max_pxcnt = 3840+1440-1, 757 .hspuls_begin = 2156+1920, 758 .hspuls_end = 44, 759 .hspuls_switch = 44, 760 .vspuls_begin = 140, 761 .vspuls_end = 2059+1920, 762 .vspuls_bline = 0, 763 .vspuls_eline = 4, 764 .havon_begin = 148, 765 .havon_end = 3987, 766 .vavon_bline = 89, 767 .vavon_eline = 2248, 768 /* eqpuls_begin */ 769 /* eqpuls_end */ 770 /* eqpuls_bline */ 771 /* eqpuls_eline */ 772 .hso_begin = 44, 773 .hso_end = 2156+1920, 774 .vso_begin = 2100+1920, 775 .vso_end = 2164+1920, 776 .vso_bline = 51, 777 .vso_eline = 53, 778 .vso_eline_present = true, 779 /* sy_val */ 780 /* sy2_val */ 781 .max_lncnt = 2249, 782 }, 783 }; 784 785 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = { 786 .encp = { 787 .dvi_settings = 0x1, 788 .video_mode = 0x4040, 789 .video_mode_adv = 0x8, 790 /* video_sync_mode */ 791 /* video_yc_dly */ 792 /* video_rgb_ctrl */ 793 .video_filt_ctrl = 0x1000, 794 .video_filt_ctrl_present = true, 795 /* video_ofld_voav_ofst */ 796 .yfp1_htime = 140, 797 .yfp2_htime = 140+3840, 798 .max_pxcnt = 3840+560-1, 799 .hspuls_begin = 2156+1920, 800 .hspuls_end = 44, 801 .hspuls_switch = 44, 802 .vspuls_begin = 140, 803 .vspuls_end = 2059+1920, 804 .vspuls_bline = 0, 805 .vspuls_eline = 4, 806 .havon_begin = 148, 807 .havon_end = 3987, 808 .vavon_bline = 89, 809 .vavon_eline = 2248, 810 /* eqpuls_begin */ 811 /* eqpuls_end */ 812 /* eqpuls_bline */ 813 /* eqpuls_eline */ 814 .hso_begin = 44, 815 .hso_end = 2156+1920, 816 .vso_begin = 2100+1920, 817 .vso_end = 2164+1920, 818 .vso_bline = 51, 819 .vso_eline = 53, 820 .vso_eline_present = true, 821 /* sy_val */ 822 /* sy2_val */ 823 .max_lncnt = 2249, 824 }, 825 }; 826 827 struct meson_hdmi_venc_vic_mode { 828 unsigned int vic; 829 union meson_hdmi_venc_mode *mode; 830 } meson_hdmi_venc_vic_modes[] = { 831 { 6, &meson_hdmi_enci_mode_480i }, 832 { 7, &meson_hdmi_enci_mode_480i }, 833 { 21, &meson_hdmi_enci_mode_576i }, 834 { 22, &meson_hdmi_enci_mode_576i }, 835 { 2, &meson_hdmi_encp_mode_480p }, 836 { 3, &meson_hdmi_encp_mode_480p }, 837 { 17, &meson_hdmi_encp_mode_576p }, 838 { 18, &meson_hdmi_encp_mode_576p }, 839 { 4, &meson_hdmi_encp_mode_720p60 }, 840 { 19, &meson_hdmi_encp_mode_720p50 }, 841 { 5, &meson_hdmi_encp_mode_1080i60 }, 842 { 20, &meson_hdmi_encp_mode_1080i50 }, 843 { 32, &meson_hdmi_encp_mode_1080p24 }, 844 { 33, &meson_hdmi_encp_mode_1080p50 }, 845 { 34, &meson_hdmi_encp_mode_1080p30 }, 846 { 31, &meson_hdmi_encp_mode_1080p50 }, 847 { 16, &meson_hdmi_encp_mode_1080p60 }, 848 { 93, &meson_hdmi_encp_mode_2160p24 }, 849 { 94, &meson_hdmi_encp_mode_2160p25 }, 850 { 95, &meson_hdmi_encp_mode_2160p30 }, 851 { 96, &meson_hdmi_encp_mode_2160p25 }, 852 { 97, &meson_hdmi_encp_mode_2160p30 }, 853 { 0, NULL}, /* sentinel */ 854 }; 855 856 static signed int to_signed(unsigned int a) 857 { 858 if (a <= 7) 859 return a; 860 else 861 return a - 16; 862 } 863 864 static unsigned long modulo(unsigned long a, unsigned long b) 865 { 866 if (a >= b) 867 return a - b; 868 else 869 return a; 870 } 871 872 enum drm_mode_status 873 meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode) 874 { 875 if (mode->flags & ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | 876 DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)) 877 return MODE_BAD; 878 879 if (mode->hdisplay < 640 || mode->hdisplay > 1920) 880 return MODE_BAD_HVALUE; 881 882 if (mode->vdisplay < 480 || mode->vdisplay > 1200) 883 return MODE_BAD_VVALUE; 884 885 return MODE_OK; 886 } 887 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode); 888 889 bool meson_venc_hdmi_supported_vic(int vic) 890 { 891 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; 892 893 while (vmode->vic && vmode->mode) { 894 if (vmode->vic == vic) 895 return true; 896 vmode++; 897 } 898 899 return false; 900 } 901 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic); 902 903 void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode, 904 union meson_hdmi_venc_mode *dmt_mode) 905 { 906 memset(dmt_mode, 0, sizeof(*dmt_mode)); 907 908 dmt_mode->encp.dvi_settings = 0x21; 909 dmt_mode->encp.video_mode = 0x4040; 910 dmt_mode->encp.video_mode_adv = 0x18; 911 dmt_mode->encp.max_pxcnt = mode->htotal - 1; 912 dmt_mode->encp.havon_begin = mode->htotal - mode->hsync_start; 913 dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin + 914 mode->hdisplay - 1; 915 dmt_mode->encp.vavon_bline = mode->vtotal - mode->vsync_start; 916 dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline + 917 mode->vdisplay - 1; 918 dmt_mode->encp.hso_begin = 0; 919 dmt_mode->encp.hso_end = mode->hsync_end - mode->hsync_start; 920 dmt_mode->encp.vso_begin = 30; 921 dmt_mode->encp.vso_end = 50; 922 dmt_mode->encp.vso_bline = 0; 923 dmt_mode->encp.vso_eline = mode->vsync_end - mode->vsync_start; 924 dmt_mode->encp.vso_eline_present = true; 925 dmt_mode->encp.max_lncnt = mode->vtotal - 1; 926 } 927 928 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic) 929 { 930 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; 931 932 while (vmode->vic && vmode->mode) { 933 if (vmode->vic == vic) 934 return vmode->mode; 935 vmode++; 936 } 937 938 return NULL; 939 } 940 941 bool meson_venc_hdmi_venc_repeat(int vic) 942 { 943 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ 944 if (vic == 6 || vic == 7 || /* 480i */ 945 vic == 21 || vic == 22 || /* 576i */ 946 vic == 17 || vic == 18 || /* 576p */ 947 vic == 2 || vic == 3 || /* 480p */ 948 vic == 4 || /* 720p60 */ 949 vic == 19 || /* 720p50 */ 950 vic == 5 || /* 1080i60 */ 951 vic == 20) /* 1080i50 */ 952 return true; 953 954 return false; 955 } 956 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat); 957 958 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, 959 struct drm_display_mode *mode) 960 { 961 union meson_hdmi_venc_mode *vmode = NULL; 962 union meson_hdmi_venc_mode vmode_dmt; 963 bool use_enci = false; 964 bool venc_repeat = false; 965 bool hdmi_repeat = false; 966 unsigned int venc_hdmi_latency = 2; 967 unsigned long total_pixels_venc = 0; 968 unsigned long active_pixels_venc = 0; 969 unsigned long front_porch_venc = 0; 970 unsigned long hsync_pixels_venc = 0; 971 unsigned long de_h_begin = 0; 972 unsigned long de_h_end = 0; 973 unsigned long de_v_begin_even = 0; 974 unsigned long de_v_end_even = 0; 975 unsigned long de_v_begin_odd = 0; 976 unsigned long de_v_end_odd = 0; 977 unsigned long hs_begin = 0; 978 unsigned long hs_end = 0; 979 unsigned long vs_adjust = 0; 980 unsigned long vs_bline_evn = 0; 981 unsigned long vs_eline_evn = 0; 982 unsigned long vs_bline_odd = 0; 983 unsigned long vs_eline_odd = 0; 984 unsigned long vso_begin_evn = 0; 985 unsigned long vso_begin_odd = 0; 986 unsigned int eof_lines; 987 unsigned int sof_lines; 988 unsigned int vsync_lines; 989 990 /* Use VENCI for 480i and 576i and double HDMI pixels */ 991 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 992 hdmi_repeat = true; 993 use_enci = true; 994 venc_hdmi_latency = 1; 995 } 996 997 if (meson_venc_hdmi_supported_vic(vic)) { 998 vmode = meson_venc_hdmi_get_vic_vmode(vic); 999 if (!vmode) { 1000 dev_err(priv->dev, "%s: Fatal Error, unsupported mode " 1001 DRM_MODE_FMT "\n", __func__, 1002 DRM_MODE_ARG(mode)); 1003 return; 1004 } 1005 } else { 1006 meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt); 1007 vmode = &vmode_dmt; 1008 use_enci = false; 1009 } 1010 1011 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ 1012 if (meson_venc_hdmi_venc_repeat(vic)) 1013 venc_repeat = true; 1014 1015 eof_lines = mode->vsync_start - mode->vdisplay; 1016 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1017 eof_lines /= 2; 1018 sof_lines = mode->vtotal - mode->vsync_end; 1019 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1020 sof_lines /= 2; 1021 vsync_lines = mode->vsync_end - mode->vsync_start; 1022 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1023 vsync_lines /= 2; 1024 1025 total_pixels_venc = mode->htotal; 1026 if (hdmi_repeat) 1027 total_pixels_venc /= 2; 1028 if (venc_repeat) 1029 total_pixels_venc *= 2; 1030 1031 active_pixels_venc = mode->hdisplay; 1032 if (hdmi_repeat) 1033 active_pixels_venc /= 2; 1034 if (venc_repeat) 1035 active_pixels_venc *= 2; 1036 1037 front_porch_venc = (mode->hsync_start - mode->hdisplay); 1038 if (hdmi_repeat) 1039 front_porch_venc /= 2; 1040 if (venc_repeat) 1041 front_porch_venc *= 2; 1042 1043 hsync_pixels_venc = (mode->hsync_end - mode->hsync_start); 1044 if (hdmi_repeat) 1045 hsync_pixels_venc /= 2; 1046 if (venc_repeat) 1047 hsync_pixels_venc *= 2; 1048 1049 /* Disable VDACs */ 1050 writel_bits_relaxed(0xff, 0xff, 1051 priv->io_base + _REG(VENC_VDAC_SETTING)); 1052 1053 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 1054 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 1055 1056 if (use_enci) { 1057 unsigned int lines_f0; 1058 unsigned int lines_f1; 1059 1060 /* CVBS Filter settings */ 1061 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 1062 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1063 1064 /* Digital Video Select : Interlace, clk27 clk, external */ 1065 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); 1066 1067 /* Reset Video Mode */ 1068 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); 1069 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1070 1071 /* Horizontal sync signal output */ 1072 writel_relaxed(vmode->enci.hso_begin, 1073 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); 1074 writel_relaxed(vmode->enci.hso_end, 1075 priv->io_base + _REG(ENCI_SYNC_HSO_END)); 1076 1077 /* Vertical Sync lines */ 1078 writel_relaxed(vmode->enci.vso_even, 1079 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN)); 1080 writel_relaxed(vmode->enci.vso_odd, 1081 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 1082 1083 /* Macrovision max amplitude change */ 1084 writel_relaxed(vmode->enci.macv_max_amp, 1085 priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1086 1087 /* Video mode */ 1088 writel_relaxed(vmode->enci.video_prog_mode, 1089 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1090 writel_relaxed(vmode->enci.video_mode, 1091 priv->io_base + _REG(ENCI_VIDEO_MODE)); 1092 1093 /* Advanced Video Mode : 1094 * Demux shifting 0x2 1095 * Blank line end at line17/22 1096 * High bandwidth Luma Filter 1097 * Low bandwidth Chroma Filter 1098 * Bypass luma low pass filter 1099 * No macrovision on CSYNC 1100 */ 1101 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1102 1103 writel(vmode->enci.sch_adjust, 1104 priv->io_base + _REG(ENCI_VIDEO_SCH)); 1105 1106 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */ 1107 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE)); 1108 1109 if (vmode->enci.yc_delay) 1110 writel_relaxed(vmode->enci.yc_delay, 1111 priv->io_base + _REG(ENCI_YC_DELAY)); 1112 1113 1114 /* UNreset Interlaced TV Encoder */ 1115 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 1116 1117 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 1118 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1119 1120 /* Timings */ 1121 writel_relaxed(vmode->enci.pixel_start, 1122 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START)); 1123 writel_relaxed(vmode->enci.pixel_end, 1124 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END)); 1125 1126 writel_relaxed(vmode->enci.top_field_line_start, 1127 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1128 writel_relaxed(vmode->enci.top_field_line_end, 1129 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END)); 1130 1131 writel_relaxed(vmode->enci.bottom_field_line_start, 1132 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1133 writel_relaxed(vmode->enci.bottom_field_line_end, 1134 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END)); 1135 1136 /* Select ENCI for VIU */ 1137 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1138 1139 /* Interlace video enable */ 1140 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1141 1142 lines_f0 = mode->vtotal >> 1; 1143 lines_f1 = lines_f0 + 1; 1144 1145 de_h_begin = modulo(readl_relaxed(priv->io_base + 1146 _REG(ENCI_VFIFO2VD_PIXEL_START)) 1147 + venc_hdmi_latency, 1148 total_pixels_venc); 1149 de_h_end = modulo(de_h_begin + active_pixels_venc, 1150 total_pixels_venc); 1151 1152 writel_relaxed(de_h_begin, 1153 priv->io_base + _REG(ENCI_DE_H_BEGIN)); 1154 writel_relaxed(de_h_end, 1155 priv->io_base + _REG(ENCI_DE_H_END)); 1156 1157 de_v_begin_even = readl_relaxed(priv->io_base + 1158 _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1159 de_v_end_even = de_v_begin_even + mode->vdisplay; 1160 de_v_begin_odd = readl_relaxed(priv->io_base + 1161 _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1162 de_v_end_odd = de_v_begin_odd + mode->vdisplay; 1163 1164 writel_relaxed(de_v_begin_even, 1165 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN)); 1166 writel_relaxed(de_v_end_even, 1167 priv->io_base + _REG(ENCI_DE_V_END_EVEN)); 1168 writel_relaxed(de_v_begin_odd, 1169 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD)); 1170 writel_relaxed(de_v_end_odd, 1171 priv->io_base + _REG(ENCI_DE_V_END_ODD)); 1172 1173 /* Program Hsync timing */ 1174 hs_begin = de_h_end + front_porch_venc; 1175 if (de_h_end + front_porch_venc >= total_pixels_venc) { 1176 hs_begin -= total_pixels_venc; 1177 vs_adjust = 1; 1178 } else { 1179 hs_begin = de_h_end + front_porch_venc; 1180 vs_adjust = 0; 1181 } 1182 1183 hs_end = modulo(hs_begin + hsync_pixels_venc, 1184 total_pixels_venc); 1185 writel_relaxed(hs_begin, 1186 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN)); 1187 writel_relaxed(hs_end, 1188 priv->io_base + _REG(ENCI_DVI_HSO_END)); 1189 1190 /* Program Vsync timing for even field */ 1191 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) { 1192 vs_bline_evn = (de_v_end_odd - 1) 1193 + eof_lines 1194 + vs_adjust 1195 - lines_f1; 1196 vs_eline_evn = vs_bline_evn + vsync_lines; 1197 1198 writel_relaxed(vs_bline_evn, 1199 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN)); 1200 1201 writel_relaxed(vs_eline_evn, 1202 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1203 1204 writel_relaxed(hs_begin, 1205 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN)); 1206 writel_relaxed(hs_begin, 1207 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN)); 1208 } else { 1209 vs_bline_odd = (de_v_end_odd - 1) 1210 + eof_lines 1211 + vs_adjust; 1212 1213 writel_relaxed(vs_bline_odd, 1214 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD)); 1215 1216 writel_relaxed(hs_begin, 1217 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD)); 1218 1219 if ((vs_bline_odd + vsync_lines) >= lines_f1) { 1220 vs_eline_evn = vs_bline_odd 1221 + vsync_lines 1222 - lines_f1; 1223 1224 writel_relaxed(vs_eline_evn, priv->io_base 1225 + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1226 1227 writel_relaxed(hs_begin, priv->io_base 1228 + _REG(ENCI_DVI_VSO_END_EVN)); 1229 } else { 1230 vs_eline_odd = vs_bline_odd 1231 + vsync_lines; 1232 1233 writel_relaxed(vs_eline_odd, priv->io_base 1234 + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1235 1236 writel_relaxed(hs_begin, priv->io_base 1237 + _REG(ENCI_DVI_VSO_END_ODD)); 1238 } 1239 } 1240 1241 /* Program Vsync timing for odd field */ 1242 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) { 1243 vs_bline_odd = (de_v_end_even - 1) 1244 + (eof_lines + 1) 1245 - lines_f0; 1246 vs_eline_odd = vs_bline_odd + vsync_lines; 1247 1248 writel_relaxed(vs_bline_odd, 1249 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD)); 1250 1251 writel_relaxed(vs_eline_odd, 1252 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1253 1254 vso_begin_odd = modulo(hs_begin 1255 + (total_pixels_venc >> 1), 1256 total_pixels_venc); 1257 1258 writel_relaxed(vso_begin_odd, 1259 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD)); 1260 writel_relaxed(vso_begin_odd, 1261 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD)); 1262 } else { 1263 vs_bline_evn = (de_v_end_even - 1) 1264 + (eof_lines + 1); 1265 1266 writel_relaxed(vs_bline_evn, 1267 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN)); 1268 1269 vso_begin_evn = modulo(hs_begin 1270 + (total_pixels_venc >> 1), 1271 total_pixels_venc); 1272 1273 writel_relaxed(vso_begin_evn, priv->io_base 1274 + _REG(ENCI_DVI_VSO_BEGIN_EVN)); 1275 1276 if (vs_bline_evn + vsync_lines >= lines_f0) { 1277 vs_eline_odd = vs_bline_evn 1278 + vsync_lines 1279 - lines_f0; 1280 1281 writel_relaxed(vs_eline_odd, priv->io_base 1282 + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1283 1284 writel_relaxed(vso_begin_evn, priv->io_base 1285 + _REG(ENCI_DVI_VSO_END_ODD)); 1286 } else { 1287 vs_eline_evn = vs_bline_evn + vsync_lines; 1288 1289 writel_relaxed(vs_eline_evn, priv->io_base 1290 + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1291 1292 writel_relaxed(vso_begin_evn, priv->io_base 1293 + _REG(ENCI_DVI_VSO_END_EVN)); 1294 } 1295 } 1296 } else { 1297 writel_relaxed(vmode->encp.dvi_settings, 1298 priv->io_base + _REG(VENC_DVI_SETTING)); 1299 writel_relaxed(vmode->encp.video_mode, 1300 priv->io_base + _REG(ENCP_VIDEO_MODE)); 1301 writel_relaxed(vmode->encp.video_mode_adv, 1302 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV)); 1303 if (vmode->encp.video_prog_mode_present) 1304 writel_relaxed(vmode->encp.video_prog_mode, 1305 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1306 if (vmode->encp.video_sync_mode_present) 1307 writel_relaxed(vmode->encp.video_sync_mode, 1308 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE)); 1309 if (vmode->encp.video_yc_dly_present) 1310 writel_relaxed(vmode->encp.video_yc_dly, 1311 priv->io_base + _REG(ENCP_VIDEO_YC_DLY)); 1312 if (vmode->encp.video_rgb_ctrl_present) 1313 writel_relaxed(vmode->encp.video_rgb_ctrl, 1314 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL)); 1315 if (vmode->encp.video_filt_ctrl_present) 1316 writel_relaxed(vmode->encp.video_filt_ctrl, 1317 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL)); 1318 if (vmode->encp.video_ofld_voav_ofst_present) 1319 writel_relaxed(vmode->encp.video_ofld_voav_ofst, 1320 priv->io_base 1321 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST)); 1322 writel_relaxed(vmode->encp.yfp1_htime, 1323 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME)); 1324 writel_relaxed(vmode->encp.yfp2_htime, 1325 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME)); 1326 writel_relaxed(vmode->encp.max_pxcnt, 1327 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT)); 1328 writel_relaxed(vmode->encp.hspuls_begin, 1329 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN)); 1330 writel_relaxed(vmode->encp.hspuls_end, 1331 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END)); 1332 writel_relaxed(vmode->encp.hspuls_switch, 1333 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH)); 1334 writel_relaxed(vmode->encp.vspuls_begin, 1335 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN)); 1336 writel_relaxed(vmode->encp.vspuls_end, 1337 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END)); 1338 writel_relaxed(vmode->encp.vspuls_bline, 1339 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE)); 1340 writel_relaxed(vmode->encp.vspuls_eline, 1341 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE)); 1342 if (vmode->encp.eqpuls_begin_present) 1343 writel_relaxed(vmode->encp.eqpuls_begin, 1344 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN)); 1345 if (vmode->encp.eqpuls_end_present) 1346 writel_relaxed(vmode->encp.eqpuls_end, 1347 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END)); 1348 if (vmode->encp.eqpuls_bline_present) 1349 writel_relaxed(vmode->encp.eqpuls_bline, 1350 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE)); 1351 if (vmode->encp.eqpuls_eline_present) 1352 writel_relaxed(vmode->encp.eqpuls_eline, 1353 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE)); 1354 writel_relaxed(vmode->encp.havon_begin, 1355 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN)); 1356 writel_relaxed(vmode->encp.havon_end, 1357 priv->io_base + _REG(ENCP_VIDEO_HAVON_END)); 1358 writel_relaxed(vmode->encp.vavon_bline, 1359 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE)); 1360 writel_relaxed(vmode->encp.vavon_eline, 1361 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE)); 1362 writel_relaxed(vmode->encp.hso_begin, 1363 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN)); 1364 writel_relaxed(vmode->encp.hso_end, 1365 priv->io_base + _REG(ENCP_VIDEO_HSO_END)); 1366 writel_relaxed(vmode->encp.vso_begin, 1367 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN)); 1368 writel_relaxed(vmode->encp.vso_end, 1369 priv->io_base + _REG(ENCP_VIDEO_VSO_END)); 1370 writel_relaxed(vmode->encp.vso_bline, 1371 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE)); 1372 if (vmode->encp.vso_eline_present) 1373 writel_relaxed(vmode->encp.vso_eline, 1374 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE)); 1375 if (vmode->encp.sy_val_present) 1376 writel_relaxed(vmode->encp.sy_val, 1377 priv->io_base + _REG(ENCP_VIDEO_SY_VAL)); 1378 if (vmode->encp.sy2_val_present) 1379 writel_relaxed(vmode->encp.sy2_val, 1380 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL)); 1381 writel_relaxed(vmode->encp.max_lncnt, 1382 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT)); 1383 1384 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); 1385 1386 /* Set DE signal’s polarity is active high */ 1387 writel_bits_relaxed(BIT(14), BIT(14), 1388 priv->io_base + _REG(ENCP_VIDEO_MODE)); 1389 1390 /* Program DE timing */ 1391 de_h_begin = modulo(readl_relaxed(priv->io_base + 1392 _REG(ENCP_VIDEO_HAVON_BEGIN)) 1393 + venc_hdmi_latency, 1394 total_pixels_venc); 1395 de_h_end = modulo(de_h_begin + active_pixels_venc, 1396 total_pixels_venc); 1397 1398 writel_relaxed(de_h_begin, 1399 priv->io_base + _REG(ENCP_DE_H_BEGIN)); 1400 writel_relaxed(de_h_end, 1401 priv->io_base + _REG(ENCP_DE_H_END)); 1402 1403 /* Program DE timing for even field */ 1404 de_v_begin_even = readl_relaxed(priv->io_base 1405 + _REG(ENCP_VIDEO_VAVON_BLINE)); 1406 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1407 de_v_end_even = de_v_begin_even + 1408 (mode->vdisplay / 2); 1409 else 1410 de_v_end_even = de_v_begin_even + mode->vdisplay; 1411 1412 writel_relaxed(de_v_begin_even, 1413 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN)); 1414 writel_relaxed(de_v_end_even, 1415 priv->io_base + _REG(ENCP_DE_V_END_EVEN)); 1416 1417 /* Program DE timing for odd field if needed */ 1418 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1419 unsigned int ofld_voav_ofst = 1420 readl_relaxed(priv->io_base + 1421 _REG(ENCP_VIDEO_OFLD_VOAV_OFST)); 1422 de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4) 1423 + de_v_begin_even 1424 + ((mode->vtotal - 1) / 2); 1425 de_v_end_odd = de_v_begin_odd + (mode->vdisplay / 2); 1426 1427 writel_relaxed(de_v_begin_odd, 1428 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD)); 1429 writel_relaxed(de_v_end_odd, 1430 priv->io_base + _REG(ENCP_DE_V_END_ODD)); 1431 } 1432 1433 /* Program Hsync timing */ 1434 if ((de_h_end + front_porch_venc) >= total_pixels_venc) { 1435 hs_begin = de_h_end 1436 + front_porch_venc 1437 - total_pixels_venc; 1438 vs_adjust = 1; 1439 } else { 1440 hs_begin = de_h_end 1441 + front_porch_venc; 1442 vs_adjust = 0; 1443 } 1444 1445 hs_end = modulo(hs_begin + hsync_pixels_venc, 1446 total_pixels_venc); 1447 1448 writel_relaxed(hs_begin, 1449 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN)); 1450 writel_relaxed(hs_end, 1451 priv->io_base + _REG(ENCP_DVI_HSO_END)); 1452 1453 /* Program Vsync timing for even field */ 1454 if (de_v_begin_even >= 1455 (sof_lines + vsync_lines + (1 - vs_adjust))) 1456 vs_bline_evn = de_v_begin_even 1457 - sof_lines 1458 - vsync_lines 1459 - (1 - vs_adjust); 1460 else 1461 vs_bline_evn = mode->vtotal 1462 + de_v_begin_even 1463 - sof_lines 1464 - vsync_lines 1465 - (1 - vs_adjust); 1466 1467 vs_eline_evn = modulo(vs_bline_evn + vsync_lines, 1468 mode->vtotal); 1469 1470 writel_relaxed(vs_bline_evn, 1471 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN)); 1472 writel_relaxed(vs_eline_evn, 1473 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN)); 1474 1475 vso_begin_evn = hs_begin; 1476 writel_relaxed(vso_begin_evn, 1477 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN)); 1478 writel_relaxed(vso_begin_evn, 1479 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN)); 1480 1481 /* Program Vsync timing for odd field if needed */ 1482 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1483 vs_bline_odd = (de_v_begin_odd - 1) 1484 - sof_lines 1485 - vsync_lines; 1486 vs_eline_odd = (de_v_begin_odd - 1) 1487 - vsync_lines; 1488 vso_begin_odd = modulo(hs_begin 1489 + (total_pixels_venc >> 1), 1490 total_pixels_venc); 1491 1492 writel_relaxed(vs_bline_odd, 1493 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD)); 1494 writel_relaxed(vs_eline_odd, 1495 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD)); 1496 writel_relaxed(vso_begin_odd, 1497 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD)); 1498 writel_relaxed(vso_begin_odd, 1499 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD)); 1500 } 1501 1502 /* Select ENCP for VIU */ 1503 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP); 1504 } 1505 1506 writel_relaxed((use_enci ? 1 : 2) | 1507 (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) | 1508 (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) | 1509 4 << 5 | 1510 (venc_repeat ? 1 << 8 : 0) | 1511 (hdmi_repeat ? 1 << 12 : 0), 1512 priv->io_base + _REG(VPU_HDMI_SETTING)); 1513 1514 priv->venc.hdmi_repeat = hdmi_repeat; 1515 priv->venc.venc_repeat = venc_repeat; 1516 priv->venc.hdmi_use_enci = use_enci; 1517 1518 priv->venc.current_mode = MESON_VENC_MODE_HDMI; 1519 } 1520 EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set); 1521 1522 void meson_venci_cvbs_mode_set(struct meson_drm *priv, 1523 struct meson_cvbs_enci_mode *mode) 1524 { 1525 if (mode->mode_tag == priv->venc.current_mode) 1526 return; 1527 1528 /* CVBS Filter settings */ 1529 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 1530 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1531 1532 /* Digital Video Select : Interlace, clk27 clk, external */ 1533 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); 1534 1535 /* Reset Video Mode */ 1536 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); 1537 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1538 1539 /* Horizontal sync signal output */ 1540 writel_relaxed(mode->hso_begin, 1541 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); 1542 writel_relaxed(mode->hso_end, 1543 priv->io_base + _REG(ENCI_SYNC_HSO_END)); 1544 1545 /* Vertical Sync lines */ 1546 writel_relaxed(mode->vso_even, 1547 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN)); 1548 writel_relaxed(mode->vso_odd, 1549 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 1550 1551 /* Macrovision max amplitude change */ 1552 writel_relaxed(0x8100 + mode->macv_max_amp, 1553 priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1554 1555 /* Video mode */ 1556 writel_relaxed(mode->video_prog_mode, 1557 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1558 writel_relaxed(mode->video_mode, 1559 priv->io_base + _REG(ENCI_VIDEO_MODE)); 1560 1561 /* Advanced Video Mode : 1562 * Demux shifting 0x2 1563 * Blank line end at line17/22 1564 * High bandwidth Luma Filter 1565 * Low bandwidth Chroma Filter 1566 * Bypass luma low pass filter 1567 * No macrovision on CSYNC 1568 */ 1569 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1570 1571 writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH)); 1572 1573 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */ 1574 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE)); 1575 1576 /* 0x3 Y, C, and Component Y delay */ 1577 writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY)); 1578 1579 /* Timings */ 1580 writel_relaxed(mode->pixel_start, 1581 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START)); 1582 writel_relaxed(mode->pixel_end, 1583 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END)); 1584 1585 writel_relaxed(mode->top_field_line_start, 1586 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1587 writel_relaxed(mode->top_field_line_end, 1588 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END)); 1589 1590 writel_relaxed(mode->bottom_field_line_start, 1591 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1592 writel_relaxed(mode->bottom_field_line_end, 1593 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END)); 1594 1595 /* Internal Venc, Internal VIU Sync, Internal Vencoder */ 1596 writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE)); 1597 1598 /* UNreset Interlaced TV Encoder */ 1599 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 1600 1601 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 1602 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1603 1604 /* Power UP Dacs */ 1605 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING)); 1606 1607 /* Video Upsampling */ 1608 writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0)); 1609 writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1)); 1610 writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2)); 1611 1612 /* Select Interlace Y DACs */ 1613 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0)); 1614 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1)); 1615 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2)); 1616 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3)); 1617 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4)); 1618 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5)); 1619 1620 /* Select ENCI for VIU */ 1621 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1622 1623 /* Enable ENCI FIFO */ 1624 writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL)); 1625 1626 /* Select ENCI DACs 0, 1, 4, and 5 */ 1627 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0)); 1628 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1)); 1629 1630 /* Interlace video enable */ 1631 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1632 1633 /* Configure Video Saturation / Contrast / Brightness / Hue */ 1634 writel_relaxed(mode->video_saturation, 1635 priv->io_base + _REG(ENCI_VIDEO_SAT)); 1636 writel_relaxed(mode->video_contrast, 1637 priv->io_base + _REG(ENCI_VIDEO_CONT)); 1638 writel_relaxed(mode->video_brightness, 1639 priv->io_base + _REG(ENCI_VIDEO_BRIGHT)); 1640 writel_relaxed(mode->video_hue, 1641 priv->io_base + _REG(ENCI_VIDEO_HUE)); 1642 1643 /* Enable DAC0 Filter */ 1644 writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0)); 1645 writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1)); 1646 1647 /* 0 in Macrovision register 0 */ 1648 writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0)); 1649 1650 /* Analog Synchronization and color burst value adjust */ 1651 writel_relaxed(mode->analog_sync_adj, 1652 priv->io_base + _REG(ENCI_SYNC_ADJ)); 1653 1654 priv->venc.current_mode = mode->mode_tag; 1655 } 1656 1657 /* Returns the current ENCI field polarity */ 1658 unsigned int meson_venci_get_field(struct meson_drm *priv) 1659 { 1660 return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29); 1661 } 1662 1663 void meson_venc_enable_vsync(struct meson_drm *priv) 1664 { 1665 writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL)); 1666 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); 1667 } 1668 1669 void meson_venc_disable_vsync(struct meson_drm *priv) 1670 { 1671 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); 1672 writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL)); 1673 } 1674 1675 void meson_venc_init(struct meson_drm *priv) 1676 { 1677 /* Disable CVBS VDAC */ 1678 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); 1679 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); 1680 1681 /* Power Down Dacs */ 1682 writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); 1683 1684 /* Disable HDMI PHY */ 1685 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); 1686 1687 /* Disable HDMI */ 1688 writel_bits_relaxed(0x3, 0, 1689 priv->io_base + _REG(VPU_HDMI_SETTING)); 1690 1691 /* Disable all encoders */ 1692 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 1693 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 1694 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); 1695 1696 /* Disable VSync IRQ */ 1697 meson_venc_disable_vsync(priv); 1698 1699 priv->venc.current_mode = MESON_VENC_MODE_NONE; 1700 } 1701