1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <drm/drmP.h> 23 #include "meson_drv.h" 24 #include "meson_venc.h" 25 #include "meson_vpp.h" 26 #include "meson_vclk.h" 27 #include "meson_registers.h" 28 29 /** 30 * DOC: Video Encoder 31 * 32 * VENC Handle the pixels encoding to the output formats. 33 * We handle the following encodings : 34 * 35 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter 36 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP 37 * - Setup of more clock rates for HDMI modes 38 * 39 * What is missing : 40 * 41 * - LCD Panel encoding via ENCL 42 * - TV Panel encoding via ENCT 43 * 44 * VENC paths : 45 * 46 * .. code:: 47 * 48 * _____ _____ ____________________ 49 * vd1---| |-| | | VENC /---------|----VDAC 50 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-| 51 * osd1--| |-| | | \ | X--HDMI-TX 52 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-| 53 * | | | 54 * | \--ENCL-----------|----LVDS 55 * |____________________| 56 * 57 * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC 58 * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI. 59 * The ENCP is designed for Progressive encoding but can also generate 60 * 1080i interlaced pixels, and was initialy desined to encode pixels for 61 * VDAC to output RGB ou YUV analog outputs. 62 * It's output is only used through the ENCP_DVI encoder for HDMI. 63 * The ENCL LVDS encoder is not implemented. 64 * 65 * The ENCI and ENCP encoders needs specially defined parameters for each 66 * supported mode and thus cannot be determined from standard video timings. 67 * 68 * The ENCI end ENCP DVI encoders are more generic and can generate any timings 69 * from the pixel data generated by ENCI or ENCP, so can use the standard video 70 * timings are source for HW parameters. 71 */ 72 73 /* HHI Registers */ 74 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ 75 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ 76 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */ 77 78 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = { 79 .mode_tag = MESON_VENC_MODE_CVBS_PAL, 80 .hso_begin = 3, 81 .hso_end = 129, 82 .vso_even = 3, 83 .vso_odd = 260, 84 .macv_max_amp = 7, 85 .video_prog_mode = 0xff, 86 .video_mode = 0x13, 87 .sch_adjust = 0x28, 88 .yc_delay = 0x343, 89 .pixel_start = 251, 90 .pixel_end = 1691, 91 .top_field_line_start = 22, 92 .top_field_line_end = 310, 93 .bottom_field_line_start = 23, 94 .bottom_field_line_end = 311, 95 .video_saturation = 9, 96 .video_contrast = 0, 97 .video_brightness = 0, 98 .video_hue = 0, 99 .analog_sync_adj = 0x8080, 100 }; 101 102 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = { 103 .mode_tag = MESON_VENC_MODE_CVBS_NTSC, 104 .hso_begin = 5, 105 .hso_end = 129, 106 .vso_even = 3, 107 .vso_odd = 260, 108 .macv_max_amp = 0xb, 109 .video_prog_mode = 0xf0, 110 .video_mode = 0x8, 111 .sch_adjust = 0x20, 112 .yc_delay = 0x333, 113 .pixel_start = 227, 114 .pixel_end = 1667, 115 .top_field_line_start = 18, 116 .top_field_line_end = 258, 117 .bottom_field_line_start = 19, 118 .bottom_field_line_end = 259, 119 .video_saturation = 18, 120 .video_contrast = 3, 121 .video_brightness = 0, 122 .video_hue = 0, 123 .analog_sync_adj = 0x9c00, 124 }; 125 126 union meson_hdmi_venc_mode { 127 struct { 128 unsigned int mode_tag; 129 unsigned int hso_begin; 130 unsigned int hso_end; 131 unsigned int vso_even; 132 unsigned int vso_odd; 133 unsigned int macv_max_amp; 134 unsigned int video_prog_mode; 135 unsigned int video_mode; 136 unsigned int sch_adjust; 137 unsigned int yc_delay; 138 unsigned int pixel_start; 139 unsigned int pixel_end; 140 unsigned int top_field_line_start; 141 unsigned int top_field_line_end; 142 unsigned int bottom_field_line_start; 143 unsigned int bottom_field_line_end; 144 } enci; 145 struct { 146 unsigned int dvi_settings; 147 unsigned int video_mode; 148 unsigned int video_mode_adv; 149 unsigned int video_prog_mode; 150 bool video_prog_mode_present; 151 unsigned int video_sync_mode; 152 bool video_sync_mode_present; 153 unsigned int video_yc_dly; 154 bool video_yc_dly_present; 155 unsigned int video_rgb_ctrl; 156 bool video_rgb_ctrl_present; 157 unsigned int video_filt_ctrl; 158 bool video_filt_ctrl_present; 159 unsigned int video_ofld_voav_ofst; 160 bool video_ofld_voav_ofst_present; 161 unsigned int yfp1_htime; 162 unsigned int yfp2_htime; 163 unsigned int max_pxcnt; 164 unsigned int hspuls_begin; 165 unsigned int hspuls_end; 166 unsigned int hspuls_switch; 167 unsigned int vspuls_begin; 168 unsigned int vspuls_end; 169 unsigned int vspuls_bline; 170 unsigned int vspuls_eline; 171 unsigned int eqpuls_begin; 172 bool eqpuls_begin_present; 173 unsigned int eqpuls_end; 174 bool eqpuls_end_present; 175 unsigned int eqpuls_bline; 176 bool eqpuls_bline_present; 177 unsigned int eqpuls_eline; 178 bool eqpuls_eline_present; 179 unsigned int havon_begin; 180 unsigned int havon_end; 181 unsigned int vavon_bline; 182 unsigned int vavon_eline; 183 unsigned int hso_begin; 184 unsigned int hso_end; 185 unsigned int vso_begin; 186 unsigned int vso_end; 187 unsigned int vso_bline; 188 unsigned int vso_eline; 189 bool vso_eline_present; 190 unsigned int sy_val; 191 bool sy_val_present; 192 unsigned int sy2_val; 193 bool sy2_val_present; 194 unsigned int max_lncnt; 195 } encp; 196 }; 197 198 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = { 199 .enci = { 200 .hso_begin = 5, 201 .hso_end = 129, 202 .vso_even = 3, 203 .vso_odd = 260, 204 .macv_max_amp = 0x810b, 205 .video_prog_mode = 0xf0, 206 .video_mode = 0x8, 207 .sch_adjust = 0x20, 208 .yc_delay = 0, 209 .pixel_start = 227, 210 .pixel_end = 1667, 211 .top_field_line_start = 18, 212 .top_field_line_end = 258, 213 .bottom_field_line_start = 19, 214 .bottom_field_line_end = 259, 215 }, 216 }; 217 218 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = { 219 .enci = { 220 .hso_begin = 3, 221 .hso_end = 129, 222 .vso_even = 3, 223 .vso_odd = 260, 224 .macv_max_amp = 8107, 225 .video_prog_mode = 0xff, 226 .video_mode = 0x13, 227 .sch_adjust = 0x28, 228 .yc_delay = 0x333, 229 .pixel_start = 251, 230 .pixel_end = 1691, 231 .top_field_line_start = 22, 232 .top_field_line_end = 310, 233 .bottom_field_line_start = 23, 234 .bottom_field_line_end = 311, 235 }, 236 }; 237 238 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = { 239 .encp = { 240 .dvi_settings = 0x21, 241 .video_mode = 0x4000, 242 .video_mode_adv = 0x9, 243 .video_prog_mode = 0, 244 .video_prog_mode_present = true, 245 .video_sync_mode = 7, 246 .video_sync_mode_present = true, 247 /* video_yc_dly */ 248 /* video_rgb_ctrl */ 249 .video_filt_ctrl = 0x2052, 250 .video_filt_ctrl_present = true, 251 /* video_ofld_voav_ofst */ 252 .yfp1_htime = 244, 253 .yfp2_htime = 1630, 254 .max_pxcnt = 1715, 255 .hspuls_begin = 0x22, 256 .hspuls_end = 0xa0, 257 .hspuls_switch = 88, 258 .vspuls_begin = 0, 259 .vspuls_end = 1589, 260 .vspuls_bline = 0, 261 .vspuls_eline = 5, 262 .havon_begin = 249, 263 .havon_end = 1689, 264 .vavon_bline = 42, 265 .vavon_eline = 521, 266 /* eqpuls_begin */ 267 /* eqpuls_end */ 268 /* eqpuls_bline */ 269 /* eqpuls_eline */ 270 .hso_begin = 3, 271 .hso_end = 5, 272 .vso_begin = 3, 273 .vso_end = 5, 274 .vso_bline = 0, 275 /* vso_eline */ 276 .sy_val = 8, 277 .sy_val_present = true, 278 .sy2_val = 0x1d8, 279 .sy2_val_present = true, 280 .max_lncnt = 524, 281 }, 282 }; 283 284 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = { 285 .encp = { 286 .dvi_settings = 0x21, 287 .video_mode = 0x4000, 288 .video_mode_adv = 0x9, 289 .video_prog_mode = 0, 290 .video_prog_mode_present = true, 291 .video_sync_mode = 7, 292 .video_sync_mode_present = true, 293 /* video_yc_dly */ 294 /* video_rgb_ctrl */ 295 .video_filt_ctrl = 0x52, 296 .video_filt_ctrl_present = true, 297 /* video_ofld_voav_ofst */ 298 .yfp1_htime = 235, 299 .yfp2_htime = 1674, 300 .max_pxcnt = 1727, 301 .hspuls_begin = 0, 302 .hspuls_end = 0x80, 303 .hspuls_switch = 88, 304 .vspuls_begin = 0, 305 .vspuls_end = 1599, 306 .vspuls_bline = 0, 307 .vspuls_eline = 4, 308 .havon_begin = 235, 309 .havon_end = 1674, 310 .vavon_bline = 44, 311 .vavon_eline = 619, 312 /* eqpuls_begin */ 313 /* eqpuls_end */ 314 /* eqpuls_bline */ 315 /* eqpuls_eline */ 316 .hso_begin = 0x80, 317 .hso_end = 0, 318 .vso_begin = 0, 319 .vso_end = 5, 320 .vso_bline = 0, 321 /* vso_eline */ 322 .sy_val = 8, 323 .sy_val_present = true, 324 .sy2_val = 0x1d8, 325 .sy2_val_present = true, 326 .max_lncnt = 624, 327 }, 328 }; 329 330 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = { 331 .encp = { 332 .dvi_settings = 0x2029, 333 .video_mode = 0x4040, 334 .video_mode_adv = 0x19, 335 /* video_prog_mode */ 336 /* video_sync_mode */ 337 /* video_yc_dly */ 338 /* video_rgb_ctrl */ 339 /* video_filt_ctrl */ 340 /* video_ofld_voav_ofst */ 341 .yfp1_htime = 648, 342 .yfp2_htime = 3207, 343 .max_pxcnt = 3299, 344 .hspuls_begin = 80, 345 .hspuls_end = 240, 346 .hspuls_switch = 80, 347 .vspuls_begin = 688, 348 .vspuls_end = 3248, 349 .vspuls_bline = 4, 350 .vspuls_eline = 8, 351 .havon_begin = 648, 352 .havon_end = 3207, 353 .vavon_bline = 29, 354 .vavon_eline = 748, 355 /* eqpuls_begin */ 356 /* eqpuls_end */ 357 /* eqpuls_bline */ 358 /* eqpuls_eline */ 359 .hso_begin = 256, 360 .hso_end = 168, 361 .vso_begin = 168, 362 .vso_end = 256, 363 .vso_bline = 0, 364 .vso_eline = 5, 365 .vso_eline_present = true, 366 /* sy_val */ 367 /* sy2_val */ 368 .max_lncnt = 749, 369 }, 370 }; 371 372 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = { 373 .encp = { 374 .dvi_settings = 0x202d, 375 .video_mode = 0x4040, 376 .video_mode_adv = 0x19, 377 .video_prog_mode = 0x100, 378 .video_prog_mode_present = true, 379 .video_sync_mode = 0x407, 380 .video_sync_mode_present = true, 381 .video_yc_dly = 0, 382 .video_yc_dly_present = true, 383 /* video_rgb_ctrl */ 384 /* video_filt_ctrl */ 385 /* video_ofld_voav_ofst */ 386 .yfp1_htime = 648, 387 .yfp2_htime = 3207, 388 .max_pxcnt = 3959, 389 .hspuls_begin = 80, 390 .hspuls_end = 240, 391 .hspuls_switch = 80, 392 .vspuls_begin = 688, 393 .vspuls_end = 3248, 394 .vspuls_bline = 4, 395 .vspuls_eline = 8, 396 .havon_begin = 648, 397 .havon_end = 3207, 398 .vavon_bline = 29, 399 .vavon_eline = 748, 400 /* eqpuls_begin */ 401 /* eqpuls_end */ 402 /* eqpuls_bline */ 403 /* eqpuls_eline */ 404 .hso_begin = 128, 405 .hso_end = 208, 406 .vso_begin = 128, 407 .vso_end = 128, 408 .vso_bline = 0, 409 .vso_eline = 5, 410 .vso_eline_present = true, 411 /* sy_val */ 412 /* sy2_val */ 413 .max_lncnt = 749, 414 }, 415 }; 416 417 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = { 418 .encp = { 419 .dvi_settings = 0x2029, 420 .video_mode = 0x5ffc, 421 .video_mode_adv = 0x19, 422 .video_prog_mode = 0x100, 423 .video_prog_mode_present = true, 424 .video_sync_mode = 0x207, 425 .video_sync_mode_present = true, 426 /* video_yc_dly */ 427 /* video_rgb_ctrl */ 428 /* video_filt_ctrl */ 429 .video_ofld_voav_ofst = 0x11, 430 .video_ofld_voav_ofst_present = true, 431 .yfp1_htime = 516, 432 .yfp2_htime = 4355, 433 .max_pxcnt = 4399, 434 .hspuls_begin = 88, 435 .hspuls_end = 264, 436 .hspuls_switch = 88, 437 .vspuls_begin = 440, 438 .vspuls_end = 2200, 439 .vspuls_bline = 0, 440 .vspuls_eline = 4, 441 .havon_begin = 516, 442 .havon_end = 4355, 443 .vavon_bline = 20, 444 .vavon_eline = 559, 445 .eqpuls_begin = 2288, 446 .eqpuls_begin_present = true, 447 .eqpuls_end = 2464, 448 .eqpuls_end_present = true, 449 .eqpuls_bline = 0, 450 .eqpuls_bline_present = true, 451 .eqpuls_eline = 4, 452 .eqpuls_eline_present = true, 453 .hso_begin = 264, 454 .hso_end = 176, 455 .vso_begin = 88, 456 .vso_end = 88, 457 .vso_bline = 0, 458 .vso_eline = 5, 459 .vso_eline_present = true, 460 /* sy_val */ 461 /* sy2_val */ 462 .max_lncnt = 1124, 463 }, 464 }; 465 466 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = { 467 .encp = { 468 .dvi_settings = 0x202d, 469 .video_mode = 0x5ffc, 470 .video_mode_adv = 0x19, 471 .video_prog_mode = 0x100, 472 .video_prog_mode_present = true, 473 .video_sync_mode = 0x7, 474 .video_sync_mode_present = true, 475 /* video_yc_dly */ 476 /* video_rgb_ctrl */ 477 /* video_filt_ctrl */ 478 .video_ofld_voav_ofst = 0x11, 479 .video_ofld_voav_ofst_present = true, 480 .yfp1_htime = 526, 481 .yfp2_htime = 4365, 482 .max_pxcnt = 5279, 483 .hspuls_begin = 88, 484 .hspuls_end = 264, 485 .hspuls_switch = 88, 486 .vspuls_begin = 440, 487 .vspuls_end = 2200, 488 .vspuls_bline = 0, 489 .vspuls_eline = 4, 490 .havon_begin = 526, 491 .havon_end = 4365, 492 .vavon_bline = 20, 493 .vavon_eline = 559, 494 .eqpuls_begin = 2288, 495 .eqpuls_begin_present = true, 496 .eqpuls_end = 2464, 497 .eqpuls_end_present = true, 498 .eqpuls_bline = 0, 499 .eqpuls_bline_present = true, 500 .eqpuls_eline = 4, 501 .eqpuls_eline_present = true, 502 .hso_begin = 142, 503 .hso_end = 230, 504 .vso_begin = 142, 505 .vso_end = 142, 506 .vso_bline = 0, 507 .vso_eline = 5, 508 .vso_eline_present = true, 509 /* sy_val */ 510 /* sy2_val */ 511 .max_lncnt = 1124, 512 }, 513 }; 514 515 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = { 516 .encp = { 517 .dvi_settings = 0xd, 518 .video_mode = 0x4040, 519 .video_mode_adv = 0x18, 520 .video_prog_mode = 0x100, 521 .video_prog_mode_present = true, 522 .video_sync_mode = 0x7, 523 .video_sync_mode_present = true, 524 .video_yc_dly = 0, 525 .video_yc_dly_present = true, 526 .video_rgb_ctrl = 2, 527 .video_rgb_ctrl_present = true, 528 .video_filt_ctrl = 0x1052, 529 .video_filt_ctrl_present = true, 530 /* video_ofld_voav_ofst */ 531 .yfp1_htime = 271, 532 .yfp2_htime = 2190, 533 .max_pxcnt = 2749, 534 .hspuls_begin = 44, 535 .hspuls_end = 132, 536 .hspuls_switch = 44, 537 .vspuls_begin = 220, 538 .vspuls_end = 2140, 539 .vspuls_bline = 0, 540 .vspuls_eline = 4, 541 .havon_begin = 271, 542 .havon_end = 2190, 543 .vavon_bline = 41, 544 .vavon_eline = 1120, 545 /* eqpuls_begin */ 546 /* eqpuls_end */ 547 .eqpuls_bline = 0, 548 .eqpuls_bline_present = true, 549 .eqpuls_eline = 4, 550 .eqpuls_eline_present = true, 551 .hso_begin = 79, 552 .hso_end = 123, 553 .vso_begin = 79, 554 .vso_end = 79, 555 .vso_bline = 0, 556 .vso_eline = 5, 557 .vso_eline_present = true, 558 /* sy_val */ 559 /* sy2_val */ 560 .max_lncnt = 1124, 561 }, 562 }; 563 564 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = { 565 .encp = { 566 .dvi_settings = 0x1, 567 .video_mode = 0x4040, 568 .video_mode_adv = 0x18, 569 .video_prog_mode = 0x100, 570 .video_prog_mode_present = true, 571 /* video_sync_mode */ 572 /* video_yc_dly */ 573 /* video_rgb_ctrl */ 574 .video_filt_ctrl = 0x1052, 575 .video_filt_ctrl_present = true, 576 /* video_ofld_voav_ofst */ 577 .yfp1_htime = 140, 578 .yfp2_htime = 2060, 579 .max_pxcnt = 2199, 580 .hspuls_begin = 2156, 581 .hspuls_end = 44, 582 .hspuls_switch = 44, 583 .vspuls_begin = 140, 584 .vspuls_end = 2059, 585 .vspuls_bline = 0, 586 .vspuls_eline = 4, 587 .havon_begin = 148, 588 .havon_end = 2067, 589 .vavon_bline = 41, 590 .vavon_eline = 1120, 591 /* eqpuls_begin */ 592 /* eqpuls_end */ 593 /* eqpuls_bline */ 594 /* eqpuls_eline */ 595 .hso_begin = 44, 596 .hso_end = 2156, 597 .vso_begin = 2100, 598 .vso_end = 2164, 599 .vso_bline = 0, 600 .vso_eline = 5, 601 .vso_eline_present = true, 602 /* sy_val */ 603 /* sy2_val */ 604 .max_lncnt = 1124, 605 }, 606 }; 607 608 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = { 609 .encp = { 610 .dvi_settings = 0xd, 611 .video_mode = 0x4040, 612 .video_mode_adv = 0x18, 613 .video_prog_mode = 0x100, 614 .video_prog_mode_present = true, 615 .video_sync_mode = 0x7, 616 .video_sync_mode_present = true, 617 .video_yc_dly = 0, 618 .video_yc_dly_present = true, 619 .video_rgb_ctrl = 2, 620 .video_rgb_ctrl_present = true, 621 /* video_filt_ctrl */ 622 /* video_ofld_voav_ofst */ 623 .yfp1_htime = 271, 624 .yfp2_htime = 2190, 625 .max_pxcnt = 2639, 626 .hspuls_begin = 44, 627 .hspuls_end = 132, 628 .hspuls_switch = 44, 629 .vspuls_begin = 220, 630 .vspuls_end = 2140, 631 .vspuls_bline = 0, 632 .vspuls_eline = 4, 633 .havon_begin = 271, 634 .havon_end = 2190, 635 .vavon_bline = 41, 636 .vavon_eline = 1120, 637 /* eqpuls_begin */ 638 /* eqpuls_end */ 639 .eqpuls_bline = 0, 640 .eqpuls_bline_present = true, 641 .eqpuls_eline = 4, 642 .eqpuls_eline_present = true, 643 .hso_begin = 79, 644 .hso_end = 123, 645 .vso_begin = 79, 646 .vso_end = 79, 647 .vso_bline = 0, 648 .vso_eline = 5, 649 .vso_eline_present = true, 650 /* sy_val */ 651 /* sy2_val */ 652 .max_lncnt = 1124, 653 }, 654 }; 655 656 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = { 657 .encp = { 658 .dvi_settings = 0x1, 659 .video_mode = 0x4040, 660 .video_mode_adv = 0x18, 661 .video_prog_mode = 0x100, 662 .video_prog_mode_present = true, 663 /* video_sync_mode */ 664 /* video_yc_dly */ 665 /* video_rgb_ctrl */ 666 .video_filt_ctrl = 0x1052, 667 .video_filt_ctrl_present = true, 668 /* video_ofld_voav_ofst */ 669 .yfp1_htime = 140, 670 .yfp2_htime = 2060, 671 .max_pxcnt = 2199, 672 .hspuls_begin = 2156, 673 .hspuls_end = 44, 674 .hspuls_switch = 44, 675 .vspuls_begin = 140, 676 .vspuls_end = 2059, 677 .vspuls_bline = 0, 678 .vspuls_eline = 4, 679 .havon_begin = 148, 680 .havon_end = 2067, 681 .vavon_bline = 41, 682 .vavon_eline = 1120, 683 /* eqpuls_begin */ 684 /* eqpuls_end */ 685 /* eqpuls_bline */ 686 /* eqpuls_eline */ 687 .hso_begin = 44, 688 .hso_end = 2156, 689 .vso_begin = 2100, 690 .vso_end = 2164, 691 .vso_bline = 0, 692 .vso_eline = 5, 693 .vso_eline_present = true, 694 /* sy_val */ 695 /* sy2_val */ 696 .max_lncnt = 1124, 697 }, 698 }; 699 700 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = { 701 .encp = { 702 .dvi_settings = 0x1, 703 .video_mode = 0x4040, 704 .video_mode_adv = 0x8, 705 /* video_sync_mode */ 706 /* video_yc_dly */ 707 /* video_rgb_ctrl */ 708 .video_filt_ctrl = 0x1000, 709 .video_filt_ctrl_present = true, 710 /* video_ofld_voav_ofst */ 711 .yfp1_htime = 140, 712 .yfp2_htime = 140+3840, 713 .max_pxcnt = 3840+1660-1, 714 .hspuls_begin = 2156+1920, 715 .hspuls_end = 44, 716 .hspuls_switch = 44, 717 .vspuls_begin = 140, 718 .vspuls_end = 2059+1920, 719 .vspuls_bline = 0, 720 .vspuls_eline = 4, 721 .havon_begin = 148, 722 .havon_end = 3987, 723 .vavon_bline = 89, 724 .vavon_eline = 2248, 725 /* eqpuls_begin */ 726 /* eqpuls_end */ 727 /* eqpuls_bline */ 728 /* eqpuls_eline */ 729 .hso_begin = 44, 730 .hso_end = 2156+1920, 731 .vso_begin = 2100+1920, 732 .vso_end = 2164+1920, 733 .vso_bline = 51, 734 .vso_eline = 53, 735 .vso_eline_present = true, 736 /* sy_val */ 737 /* sy2_val */ 738 .max_lncnt = 2249, 739 }, 740 }; 741 742 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = { 743 .encp = { 744 .dvi_settings = 0x1, 745 .video_mode = 0x4040, 746 .video_mode_adv = 0x8, 747 /* video_sync_mode */ 748 /* video_yc_dly */ 749 /* video_rgb_ctrl */ 750 .video_filt_ctrl = 0x1000, 751 .video_filt_ctrl_present = true, 752 /* video_ofld_voav_ofst */ 753 .yfp1_htime = 140, 754 .yfp2_htime = 140+3840, 755 .max_pxcnt = 3840+1440-1, 756 .hspuls_begin = 2156+1920, 757 .hspuls_end = 44, 758 .hspuls_switch = 44, 759 .vspuls_begin = 140, 760 .vspuls_end = 2059+1920, 761 .vspuls_bline = 0, 762 .vspuls_eline = 4, 763 .havon_begin = 148, 764 .havon_end = 3987, 765 .vavon_bline = 89, 766 .vavon_eline = 2248, 767 /* eqpuls_begin */ 768 /* eqpuls_end */ 769 /* eqpuls_bline */ 770 /* eqpuls_eline */ 771 .hso_begin = 44, 772 .hso_end = 2156+1920, 773 .vso_begin = 2100+1920, 774 .vso_end = 2164+1920, 775 .vso_bline = 51, 776 .vso_eline = 53, 777 .vso_eline_present = true, 778 /* sy_val */ 779 /* sy2_val */ 780 .max_lncnt = 2249, 781 }, 782 }; 783 784 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = { 785 .encp = { 786 .dvi_settings = 0x1, 787 .video_mode = 0x4040, 788 .video_mode_adv = 0x8, 789 /* video_sync_mode */ 790 /* video_yc_dly */ 791 /* video_rgb_ctrl */ 792 .video_filt_ctrl = 0x1000, 793 .video_filt_ctrl_present = true, 794 /* video_ofld_voav_ofst */ 795 .yfp1_htime = 140, 796 .yfp2_htime = 140+3840, 797 .max_pxcnt = 3840+560-1, 798 .hspuls_begin = 2156+1920, 799 .hspuls_end = 44, 800 .hspuls_switch = 44, 801 .vspuls_begin = 140, 802 .vspuls_end = 2059+1920, 803 .vspuls_bline = 0, 804 .vspuls_eline = 4, 805 .havon_begin = 148, 806 .havon_end = 3987, 807 .vavon_bline = 89, 808 .vavon_eline = 2248, 809 /* eqpuls_begin */ 810 /* eqpuls_end */ 811 /* eqpuls_bline */ 812 /* eqpuls_eline */ 813 .hso_begin = 44, 814 .hso_end = 2156+1920, 815 .vso_begin = 2100+1920, 816 .vso_end = 2164+1920, 817 .vso_bline = 51, 818 .vso_eline = 53, 819 .vso_eline_present = true, 820 /* sy_val */ 821 /* sy2_val */ 822 .max_lncnt = 2249, 823 }, 824 }; 825 826 struct meson_hdmi_venc_vic_mode { 827 unsigned int vic; 828 union meson_hdmi_venc_mode *mode; 829 } meson_hdmi_venc_vic_modes[] = { 830 { 6, &meson_hdmi_enci_mode_480i }, 831 { 7, &meson_hdmi_enci_mode_480i }, 832 { 21, &meson_hdmi_enci_mode_576i }, 833 { 22, &meson_hdmi_enci_mode_576i }, 834 { 2, &meson_hdmi_encp_mode_480p }, 835 { 3, &meson_hdmi_encp_mode_480p }, 836 { 17, &meson_hdmi_encp_mode_576p }, 837 { 18, &meson_hdmi_encp_mode_576p }, 838 { 4, &meson_hdmi_encp_mode_720p60 }, 839 { 19, &meson_hdmi_encp_mode_720p50 }, 840 { 5, &meson_hdmi_encp_mode_1080i60 }, 841 { 20, &meson_hdmi_encp_mode_1080i50 }, 842 { 32, &meson_hdmi_encp_mode_1080p24 }, 843 { 34, &meson_hdmi_encp_mode_1080p30 }, 844 { 31, &meson_hdmi_encp_mode_1080p50 }, 845 { 16, &meson_hdmi_encp_mode_1080p60 }, 846 { 93, &meson_hdmi_encp_mode_2160p24 }, 847 { 94, &meson_hdmi_encp_mode_2160p25 }, 848 { 95, &meson_hdmi_encp_mode_2160p30 }, 849 { 0, NULL}, /* sentinel */ 850 }; 851 852 static signed int to_signed(unsigned int a) 853 { 854 if (a <= 7) 855 return a; 856 else 857 return a - 16; 858 } 859 860 static unsigned long modulo(unsigned long a, unsigned long b) 861 { 862 if (a >= b) 863 return a - b; 864 else 865 return a; 866 } 867 868 enum drm_mode_status 869 meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode) 870 { 871 if (mode->flags & ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | 872 DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)) 873 return MODE_BAD; 874 875 if (mode->hdisplay < 640 || mode->hdisplay > 1920) 876 return MODE_BAD_HVALUE; 877 878 if (mode->vdisplay < 480 || mode->vdisplay > 1200) 879 return MODE_BAD_VVALUE; 880 881 return MODE_OK; 882 } 883 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode); 884 885 bool meson_venc_hdmi_supported_vic(int vic) 886 { 887 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; 888 889 while (vmode->vic && vmode->mode) { 890 if (vmode->vic == vic) 891 return true; 892 vmode++; 893 } 894 895 return false; 896 } 897 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic); 898 899 void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode, 900 union meson_hdmi_venc_mode *dmt_mode) 901 { 902 memset(dmt_mode, 0, sizeof(*dmt_mode)); 903 904 dmt_mode->encp.dvi_settings = 0x21; 905 dmt_mode->encp.video_mode = 0x4040; 906 dmt_mode->encp.video_mode_adv = 0x18; 907 dmt_mode->encp.max_pxcnt = mode->htotal - 1; 908 dmt_mode->encp.havon_begin = mode->htotal - mode->hsync_start; 909 dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin + 910 mode->hdisplay - 1; 911 dmt_mode->encp.vavon_bline = mode->vtotal - mode->vsync_start; 912 dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline + 913 mode->vdisplay - 1; 914 dmt_mode->encp.hso_begin = 0; 915 dmt_mode->encp.hso_end = mode->hsync_end - mode->hsync_start; 916 dmt_mode->encp.vso_begin = 30; 917 dmt_mode->encp.vso_end = 50; 918 dmt_mode->encp.vso_bline = 0; 919 dmt_mode->encp.vso_eline = mode->vsync_end - mode->vsync_start; 920 dmt_mode->encp.vso_eline_present = true; 921 dmt_mode->encp.max_lncnt = mode->vtotal - 1; 922 } 923 924 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic) 925 { 926 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; 927 928 while (vmode->vic && vmode->mode) { 929 if (vmode->vic == vic) 930 return vmode->mode; 931 vmode++; 932 } 933 934 return NULL; 935 } 936 937 bool meson_venc_hdmi_venc_repeat(int vic) 938 { 939 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ 940 if (vic == 6 || vic == 7 || /* 480i */ 941 vic == 21 || vic == 22 || /* 576i */ 942 vic == 17 || vic == 18 || /* 576p */ 943 vic == 2 || vic == 3 || /* 480p */ 944 vic == 4 || /* 720p60 */ 945 vic == 19 || /* 720p50 */ 946 vic == 5 || /* 1080i60 */ 947 vic == 20) /* 1080i50 */ 948 return true; 949 950 return false; 951 } 952 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat); 953 954 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, 955 struct drm_display_mode *mode) 956 { 957 union meson_hdmi_venc_mode *vmode = NULL; 958 union meson_hdmi_venc_mode vmode_dmt; 959 bool use_enci = false; 960 bool venc_repeat = false; 961 bool hdmi_repeat = false; 962 unsigned int venc_hdmi_latency = 2; 963 unsigned long total_pixels_venc = 0; 964 unsigned long active_pixels_venc = 0; 965 unsigned long front_porch_venc = 0; 966 unsigned long hsync_pixels_venc = 0; 967 unsigned long de_h_begin = 0; 968 unsigned long de_h_end = 0; 969 unsigned long de_v_begin_even = 0; 970 unsigned long de_v_end_even = 0; 971 unsigned long de_v_begin_odd = 0; 972 unsigned long de_v_end_odd = 0; 973 unsigned long hs_begin = 0; 974 unsigned long hs_end = 0; 975 unsigned long vs_adjust = 0; 976 unsigned long vs_bline_evn = 0; 977 unsigned long vs_eline_evn = 0; 978 unsigned long vs_bline_odd = 0; 979 unsigned long vs_eline_odd = 0; 980 unsigned long vso_begin_evn = 0; 981 unsigned long vso_begin_odd = 0; 982 unsigned int eof_lines; 983 unsigned int sof_lines; 984 unsigned int vsync_lines; 985 986 if (meson_venc_hdmi_supported_vic(vic)) { 987 vmode = meson_venc_hdmi_get_vic_vmode(vic); 988 if (!vmode) { 989 dev_err(priv->dev, "%s: Fatal Error, unsupported mode " 990 DRM_MODE_FMT "\n", __func__, 991 DRM_MODE_ARG(mode)); 992 return; 993 } 994 } else { 995 meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt); 996 vmode = &vmode_dmt; 997 } 998 999 /* Use VENCI for 480i and 576i and double HDMI pixels */ 1000 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1001 hdmi_repeat = true; 1002 use_enci = true; 1003 venc_hdmi_latency = 1; 1004 } 1005 1006 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ 1007 if (meson_venc_hdmi_venc_repeat(vic)) 1008 venc_repeat = true; 1009 1010 eof_lines = mode->vsync_start - mode->vdisplay; 1011 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1012 eof_lines /= 2; 1013 sof_lines = mode->vtotal - mode->vsync_end; 1014 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1015 sof_lines /= 2; 1016 vsync_lines = mode->vsync_end - mode->vsync_start; 1017 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1018 vsync_lines /= 2; 1019 1020 total_pixels_venc = mode->htotal; 1021 if (hdmi_repeat) 1022 total_pixels_venc /= 2; 1023 if (venc_repeat) 1024 total_pixels_venc *= 2; 1025 1026 active_pixels_venc = mode->hdisplay; 1027 if (hdmi_repeat) 1028 active_pixels_venc /= 2; 1029 if (venc_repeat) 1030 active_pixels_venc *= 2; 1031 1032 front_porch_venc = (mode->hsync_start - mode->hdisplay); 1033 if (hdmi_repeat) 1034 front_porch_venc /= 2; 1035 if (venc_repeat) 1036 front_porch_venc *= 2; 1037 1038 hsync_pixels_venc = (mode->hsync_end - mode->hsync_start); 1039 if (hdmi_repeat) 1040 hsync_pixels_venc /= 2; 1041 if (venc_repeat) 1042 hsync_pixels_venc *= 2; 1043 1044 /* Disable VDACs */ 1045 writel_bits_relaxed(0xff, 0xff, 1046 priv->io_base + _REG(VENC_VDAC_SETTING)); 1047 1048 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 1049 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 1050 1051 if (use_enci) { 1052 unsigned int lines_f0; 1053 unsigned int lines_f1; 1054 1055 /* CVBS Filter settings */ 1056 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 1057 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1058 1059 /* Digital Video Select : Interlace, clk27 clk, external */ 1060 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); 1061 1062 /* Reset Video Mode */ 1063 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); 1064 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1065 1066 /* Horizontal sync signal output */ 1067 writel_relaxed(vmode->enci.hso_begin, 1068 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); 1069 writel_relaxed(vmode->enci.hso_end, 1070 priv->io_base + _REG(ENCI_SYNC_HSO_END)); 1071 1072 /* Vertical Sync lines */ 1073 writel_relaxed(vmode->enci.vso_even, 1074 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN)); 1075 writel_relaxed(vmode->enci.vso_odd, 1076 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 1077 1078 /* Macrovision max amplitude change */ 1079 writel_relaxed(vmode->enci.macv_max_amp, 1080 priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1081 1082 /* Video mode */ 1083 writel_relaxed(vmode->enci.video_prog_mode, 1084 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1085 writel_relaxed(vmode->enci.video_mode, 1086 priv->io_base + _REG(ENCI_VIDEO_MODE)); 1087 1088 /* Advanced Video Mode : 1089 * Demux shifting 0x2 1090 * Blank line end at line17/22 1091 * High bandwidth Luma Filter 1092 * Low bandwidth Chroma Filter 1093 * Bypass luma low pass filter 1094 * No macrovision on CSYNC 1095 */ 1096 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1097 1098 writel(vmode->enci.sch_adjust, 1099 priv->io_base + _REG(ENCI_VIDEO_SCH)); 1100 1101 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */ 1102 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE)); 1103 1104 if (vmode->enci.yc_delay) 1105 writel_relaxed(vmode->enci.yc_delay, 1106 priv->io_base + _REG(ENCI_YC_DELAY)); 1107 1108 1109 /* UNreset Interlaced TV Encoder */ 1110 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 1111 1112 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 1113 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1114 1115 /* Timings */ 1116 writel_relaxed(vmode->enci.pixel_start, 1117 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START)); 1118 writel_relaxed(vmode->enci.pixel_end, 1119 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END)); 1120 1121 writel_relaxed(vmode->enci.top_field_line_start, 1122 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1123 writel_relaxed(vmode->enci.top_field_line_end, 1124 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END)); 1125 1126 writel_relaxed(vmode->enci.bottom_field_line_start, 1127 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1128 writel_relaxed(vmode->enci.bottom_field_line_end, 1129 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END)); 1130 1131 /* Select ENCI for VIU */ 1132 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1133 1134 /* Interlace video enable */ 1135 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1136 1137 lines_f0 = mode->vtotal >> 1; 1138 lines_f1 = lines_f0 + 1; 1139 1140 de_h_begin = modulo(readl_relaxed(priv->io_base + 1141 _REG(ENCI_VFIFO2VD_PIXEL_START)) 1142 + venc_hdmi_latency, 1143 total_pixels_venc); 1144 de_h_end = modulo(de_h_begin + active_pixels_venc, 1145 total_pixels_venc); 1146 1147 writel_relaxed(de_h_begin, 1148 priv->io_base + _REG(ENCI_DE_H_BEGIN)); 1149 writel_relaxed(de_h_end, 1150 priv->io_base + _REG(ENCI_DE_H_END)); 1151 1152 de_v_begin_even = readl_relaxed(priv->io_base + 1153 _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1154 de_v_end_even = de_v_begin_even + mode->vdisplay; 1155 de_v_begin_odd = readl_relaxed(priv->io_base + 1156 _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1157 de_v_end_odd = de_v_begin_odd + mode->vdisplay; 1158 1159 writel_relaxed(de_v_begin_even, 1160 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN)); 1161 writel_relaxed(de_v_end_even, 1162 priv->io_base + _REG(ENCI_DE_V_END_EVEN)); 1163 writel_relaxed(de_v_begin_odd, 1164 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD)); 1165 writel_relaxed(de_v_end_odd, 1166 priv->io_base + _REG(ENCI_DE_V_END_ODD)); 1167 1168 /* Program Hsync timing */ 1169 hs_begin = de_h_end + front_porch_venc; 1170 if (de_h_end + front_porch_venc >= total_pixels_venc) { 1171 hs_begin -= total_pixels_venc; 1172 vs_adjust = 1; 1173 } else { 1174 hs_begin = de_h_end + front_porch_venc; 1175 vs_adjust = 0; 1176 } 1177 1178 hs_end = modulo(hs_begin + hsync_pixels_venc, 1179 total_pixels_venc); 1180 writel_relaxed(hs_begin, 1181 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN)); 1182 writel_relaxed(hs_end, 1183 priv->io_base + _REG(ENCI_DVI_HSO_END)); 1184 1185 /* Program Vsync timing for even field */ 1186 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) { 1187 vs_bline_evn = (de_v_end_odd - 1) 1188 + eof_lines 1189 + vs_adjust 1190 - lines_f1; 1191 vs_eline_evn = vs_bline_evn + vsync_lines; 1192 1193 writel_relaxed(vs_bline_evn, 1194 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN)); 1195 1196 writel_relaxed(vs_eline_evn, 1197 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1198 1199 writel_relaxed(hs_begin, 1200 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN)); 1201 writel_relaxed(hs_begin, 1202 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN)); 1203 } else { 1204 vs_bline_odd = (de_v_end_odd - 1) 1205 + eof_lines 1206 + vs_adjust; 1207 1208 writel_relaxed(vs_bline_odd, 1209 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD)); 1210 1211 writel_relaxed(hs_begin, 1212 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD)); 1213 1214 if ((vs_bline_odd + vsync_lines) >= lines_f1) { 1215 vs_eline_evn = vs_bline_odd 1216 + vsync_lines 1217 - lines_f1; 1218 1219 writel_relaxed(vs_eline_evn, priv->io_base 1220 + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1221 1222 writel_relaxed(hs_begin, priv->io_base 1223 + _REG(ENCI_DVI_VSO_END_EVN)); 1224 } else { 1225 vs_eline_odd = vs_bline_odd 1226 + vsync_lines; 1227 1228 writel_relaxed(vs_eline_odd, priv->io_base 1229 + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1230 1231 writel_relaxed(hs_begin, priv->io_base 1232 + _REG(ENCI_DVI_VSO_END_ODD)); 1233 } 1234 } 1235 1236 /* Program Vsync timing for odd field */ 1237 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) { 1238 vs_bline_odd = (de_v_end_even - 1) 1239 + (eof_lines + 1) 1240 - lines_f0; 1241 vs_eline_odd = vs_bline_odd + vsync_lines; 1242 1243 writel_relaxed(vs_bline_odd, 1244 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD)); 1245 1246 writel_relaxed(vs_eline_odd, 1247 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1248 1249 vso_begin_odd = modulo(hs_begin 1250 + (total_pixels_venc >> 1), 1251 total_pixels_venc); 1252 1253 writel_relaxed(vso_begin_odd, 1254 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD)); 1255 writel_relaxed(vso_begin_odd, 1256 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD)); 1257 } else { 1258 vs_bline_evn = (de_v_end_even - 1) 1259 + (eof_lines + 1); 1260 1261 writel_relaxed(vs_bline_evn, 1262 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN)); 1263 1264 vso_begin_evn = modulo(hs_begin 1265 + (total_pixels_venc >> 1), 1266 total_pixels_venc); 1267 1268 writel_relaxed(vso_begin_evn, priv->io_base 1269 + _REG(ENCI_DVI_VSO_BEGIN_EVN)); 1270 1271 if (vs_bline_evn + vsync_lines >= lines_f0) { 1272 vs_eline_odd = vs_bline_evn 1273 + vsync_lines 1274 - lines_f0; 1275 1276 writel_relaxed(vs_eline_odd, priv->io_base 1277 + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1278 1279 writel_relaxed(vso_begin_evn, priv->io_base 1280 + _REG(ENCI_DVI_VSO_END_ODD)); 1281 } else { 1282 vs_eline_evn = vs_bline_evn + vsync_lines; 1283 1284 writel_relaxed(vs_eline_evn, priv->io_base 1285 + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1286 1287 writel_relaxed(vso_begin_evn, priv->io_base 1288 + _REG(ENCI_DVI_VSO_END_EVN)); 1289 } 1290 } 1291 } else { 1292 writel_relaxed(vmode->encp.dvi_settings, 1293 priv->io_base + _REG(VENC_DVI_SETTING)); 1294 writel_relaxed(vmode->encp.video_mode, 1295 priv->io_base + _REG(ENCP_VIDEO_MODE)); 1296 writel_relaxed(vmode->encp.video_mode_adv, 1297 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV)); 1298 if (vmode->encp.video_prog_mode_present) 1299 writel_relaxed(vmode->encp.video_prog_mode, 1300 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1301 if (vmode->encp.video_sync_mode_present) 1302 writel_relaxed(vmode->encp.video_sync_mode, 1303 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE)); 1304 if (vmode->encp.video_yc_dly_present) 1305 writel_relaxed(vmode->encp.video_yc_dly, 1306 priv->io_base + _REG(ENCP_VIDEO_YC_DLY)); 1307 if (vmode->encp.video_rgb_ctrl_present) 1308 writel_relaxed(vmode->encp.video_rgb_ctrl, 1309 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL)); 1310 if (vmode->encp.video_filt_ctrl_present) 1311 writel_relaxed(vmode->encp.video_filt_ctrl, 1312 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL)); 1313 if (vmode->encp.video_ofld_voav_ofst_present) 1314 writel_relaxed(vmode->encp.video_ofld_voav_ofst, 1315 priv->io_base 1316 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST)); 1317 writel_relaxed(vmode->encp.yfp1_htime, 1318 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME)); 1319 writel_relaxed(vmode->encp.yfp2_htime, 1320 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME)); 1321 writel_relaxed(vmode->encp.max_pxcnt, 1322 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT)); 1323 writel_relaxed(vmode->encp.hspuls_begin, 1324 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN)); 1325 writel_relaxed(vmode->encp.hspuls_end, 1326 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END)); 1327 writel_relaxed(vmode->encp.hspuls_switch, 1328 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH)); 1329 writel_relaxed(vmode->encp.vspuls_begin, 1330 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN)); 1331 writel_relaxed(vmode->encp.vspuls_end, 1332 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END)); 1333 writel_relaxed(vmode->encp.vspuls_bline, 1334 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE)); 1335 writel_relaxed(vmode->encp.vspuls_eline, 1336 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE)); 1337 if (vmode->encp.eqpuls_begin_present) 1338 writel_relaxed(vmode->encp.eqpuls_begin, 1339 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN)); 1340 if (vmode->encp.eqpuls_end_present) 1341 writel_relaxed(vmode->encp.eqpuls_end, 1342 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END)); 1343 if (vmode->encp.eqpuls_bline_present) 1344 writel_relaxed(vmode->encp.eqpuls_bline, 1345 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE)); 1346 if (vmode->encp.eqpuls_eline_present) 1347 writel_relaxed(vmode->encp.eqpuls_eline, 1348 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE)); 1349 writel_relaxed(vmode->encp.havon_begin, 1350 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN)); 1351 writel_relaxed(vmode->encp.havon_end, 1352 priv->io_base + _REG(ENCP_VIDEO_HAVON_END)); 1353 writel_relaxed(vmode->encp.vavon_bline, 1354 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE)); 1355 writel_relaxed(vmode->encp.vavon_eline, 1356 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE)); 1357 writel_relaxed(vmode->encp.hso_begin, 1358 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN)); 1359 writel_relaxed(vmode->encp.hso_end, 1360 priv->io_base + _REG(ENCP_VIDEO_HSO_END)); 1361 writel_relaxed(vmode->encp.vso_begin, 1362 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN)); 1363 writel_relaxed(vmode->encp.vso_end, 1364 priv->io_base + _REG(ENCP_VIDEO_VSO_END)); 1365 writel_relaxed(vmode->encp.vso_bline, 1366 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE)); 1367 if (vmode->encp.vso_eline_present) 1368 writel_relaxed(vmode->encp.vso_eline, 1369 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE)); 1370 if (vmode->encp.sy_val_present) 1371 writel_relaxed(vmode->encp.sy_val, 1372 priv->io_base + _REG(ENCP_VIDEO_SY_VAL)); 1373 if (vmode->encp.sy2_val_present) 1374 writel_relaxed(vmode->encp.sy2_val, 1375 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL)); 1376 writel_relaxed(vmode->encp.max_lncnt, 1377 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT)); 1378 1379 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); 1380 1381 /* Set DE signal’s polarity is active high */ 1382 writel_bits_relaxed(BIT(14), BIT(14), 1383 priv->io_base + _REG(ENCP_VIDEO_MODE)); 1384 1385 /* Program DE timing */ 1386 de_h_begin = modulo(readl_relaxed(priv->io_base + 1387 _REG(ENCP_VIDEO_HAVON_BEGIN)) 1388 + venc_hdmi_latency, 1389 total_pixels_venc); 1390 de_h_end = modulo(de_h_begin + active_pixels_venc, 1391 total_pixels_venc); 1392 1393 writel_relaxed(de_h_begin, 1394 priv->io_base + _REG(ENCP_DE_H_BEGIN)); 1395 writel_relaxed(de_h_end, 1396 priv->io_base + _REG(ENCP_DE_H_END)); 1397 1398 /* Program DE timing for even field */ 1399 de_v_begin_even = readl_relaxed(priv->io_base 1400 + _REG(ENCP_VIDEO_VAVON_BLINE)); 1401 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1402 de_v_end_even = de_v_begin_even + 1403 (mode->vdisplay / 2); 1404 else 1405 de_v_end_even = de_v_begin_even + mode->vdisplay; 1406 1407 writel_relaxed(de_v_begin_even, 1408 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN)); 1409 writel_relaxed(de_v_end_even, 1410 priv->io_base + _REG(ENCP_DE_V_END_EVEN)); 1411 1412 /* Program DE timing for odd field if needed */ 1413 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1414 unsigned int ofld_voav_ofst = 1415 readl_relaxed(priv->io_base + 1416 _REG(ENCP_VIDEO_OFLD_VOAV_OFST)); 1417 de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4) 1418 + de_v_begin_even 1419 + ((mode->vtotal - 1) / 2); 1420 de_v_end_odd = de_v_begin_odd + (mode->vdisplay / 2); 1421 1422 writel_relaxed(de_v_begin_odd, 1423 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD)); 1424 writel_relaxed(de_v_end_odd, 1425 priv->io_base + _REG(ENCP_DE_V_END_ODD)); 1426 } 1427 1428 /* Program Hsync timing */ 1429 if ((de_h_end + front_porch_venc) >= total_pixels_venc) { 1430 hs_begin = de_h_end 1431 + front_porch_venc 1432 - total_pixels_venc; 1433 vs_adjust = 1; 1434 } else { 1435 hs_begin = de_h_end 1436 + front_porch_venc; 1437 vs_adjust = 0; 1438 } 1439 1440 hs_end = modulo(hs_begin + hsync_pixels_venc, 1441 total_pixels_venc); 1442 1443 writel_relaxed(hs_begin, 1444 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN)); 1445 writel_relaxed(hs_end, 1446 priv->io_base + _REG(ENCP_DVI_HSO_END)); 1447 1448 /* Program Vsync timing for even field */ 1449 if (de_v_begin_even >= 1450 (sof_lines + vsync_lines + (1 - vs_adjust))) 1451 vs_bline_evn = de_v_begin_even 1452 - sof_lines 1453 - vsync_lines 1454 - (1 - vs_adjust); 1455 else 1456 vs_bline_evn = mode->vtotal 1457 + de_v_begin_even 1458 - sof_lines 1459 - vsync_lines 1460 - (1 - vs_adjust); 1461 1462 vs_eline_evn = modulo(vs_bline_evn + vsync_lines, 1463 mode->vtotal); 1464 1465 writel_relaxed(vs_bline_evn, 1466 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN)); 1467 writel_relaxed(vs_eline_evn, 1468 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN)); 1469 1470 vso_begin_evn = hs_begin; 1471 writel_relaxed(vso_begin_evn, 1472 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN)); 1473 writel_relaxed(vso_begin_evn, 1474 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN)); 1475 1476 /* Program Vsync timing for odd field if needed */ 1477 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1478 vs_bline_odd = (de_v_begin_odd - 1) 1479 - sof_lines 1480 - vsync_lines; 1481 vs_eline_odd = (de_v_begin_odd - 1) 1482 - vsync_lines; 1483 vso_begin_odd = modulo(hs_begin 1484 + (total_pixels_venc >> 1), 1485 total_pixels_venc); 1486 1487 writel_relaxed(vs_bline_odd, 1488 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD)); 1489 writel_relaxed(vs_eline_odd, 1490 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD)); 1491 writel_relaxed(vso_begin_odd, 1492 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD)); 1493 writel_relaxed(vso_begin_odd, 1494 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD)); 1495 } 1496 1497 /* Select ENCP for VIU */ 1498 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP); 1499 } 1500 1501 writel_relaxed((use_enci ? 1 : 2) | 1502 (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) | 1503 (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) | 1504 4 << 5 | 1505 (venc_repeat ? 1 << 8 : 0) | 1506 (hdmi_repeat ? 1 << 12 : 0), 1507 priv->io_base + _REG(VPU_HDMI_SETTING)); 1508 1509 priv->venc.hdmi_repeat = hdmi_repeat; 1510 priv->venc.venc_repeat = venc_repeat; 1511 priv->venc.hdmi_use_enci = use_enci; 1512 1513 priv->venc.current_mode = MESON_VENC_MODE_HDMI; 1514 } 1515 EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set); 1516 1517 void meson_venci_cvbs_mode_set(struct meson_drm *priv, 1518 struct meson_cvbs_enci_mode *mode) 1519 { 1520 if (mode->mode_tag == priv->venc.current_mode) 1521 return; 1522 1523 /* CVBS Filter settings */ 1524 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 1525 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1526 1527 /* Digital Video Select : Interlace, clk27 clk, external */ 1528 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); 1529 1530 /* Reset Video Mode */ 1531 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); 1532 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1533 1534 /* Horizontal sync signal output */ 1535 writel_relaxed(mode->hso_begin, 1536 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); 1537 writel_relaxed(mode->hso_end, 1538 priv->io_base + _REG(ENCI_SYNC_HSO_END)); 1539 1540 /* Vertical Sync lines */ 1541 writel_relaxed(mode->vso_even, 1542 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN)); 1543 writel_relaxed(mode->vso_odd, 1544 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 1545 1546 /* Macrovision max amplitude change */ 1547 writel_relaxed(0x8100 + mode->macv_max_amp, 1548 priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1549 1550 /* Video mode */ 1551 writel_relaxed(mode->video_prog_mode, 1552 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1553 writel_relaxed(mode->video_mode, 1554 priv->io_base + _REG(ENCI_VIDEO_MODE)); 1555 1556 /* Advanced Video Mode : 1557 * Demux shifting 0x2 1558 * Blank line end at line17/22 1559 * High bandwidth Luma Filter 1560 * Low bandwidth Chroma Filter 1561 * Bypass luma low pass filter 1562 * No macrovision on CSYNC 1563 */ 1564 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1565 1566 writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH)); 1567 1568 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */ 1569 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE)); 1570 1571 /* 0x3 Y, C, and Component Y delay */ 1572 writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY)); 1573 1574 /* Timings */ 1575 writel_relaxed(mode->pixel_start, 1576 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START)); 1577 writel_relaxed(mode->pixel_end, 1578 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END)); 1579 1580 writel_relaxed(mode->top_field_line_start, 1581 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1582 writel_relaxed(mode->top_field_line_end, 1583 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END)); 1584 1585 writel_relaxed(mode->bottom_field_line_start, 1586 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1587 writel_relaxed(mode->bottom_field_line_end, 1588 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END)); 1589 1590 /* Internal Venc, Internal VIU Sync, Internal Vencoder */ 1591 writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE)); 1592 1593 /* UNreset Interlaced TV Encoder */ 1594 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 1595 1596 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 1597 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1598 1599 /* Power UP Dacs */ 1600 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING)); 1601 1602 /* Video Upsampling */ 1603 writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0)); 1604 writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1)); 1605 writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2)); 1606 1607 /* Select Interlace Y DACs */ 1608 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0)); 1609 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1)); 1610 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2)); 1611 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3)); 1612 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4)); 1613 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5)); 1614 1615 /* Select ENCI for VIU */ 1616 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1617 1618 /* Enable ENCI FIFO */ 1619 writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL)); 1620 1621 /* Select ENCI DACs 0, 1, 4, and 5 */ 1622 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0)); 1623 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1)); 1624 1625 /* Interlace video enable */ 1626 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1627 1628 /* Configure Video Saturation / Contrast / Brightness / Hue */ 1629 writel_relaxed(mode->video_saturation, 1630 priv->io_base + _REG(ENCI_VIDEO_SAT)); 1631 writel_relaxed(mode->video_contrast, 1632 priv->io_base + _REG(ENCI_VIDEO_CONT)); 1633 writel_relaxed(mode->video_brightness, 1634 priv->io_base + _REG(ENCI_VIDEO_BRIGHT)); 1635 writel_relaxed(mode->video_hue, 1636 priv->io_base + _REG(ENCI_VIDEO_HUE)); 1637 1638 /* Enable DAC0 Filter */ 1639 writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0)); 1640 writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1)); 1641 1642 /* 0 in Macrovision register 0 */ 1643 writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0)); 1644 1645 /* Analog Synchronization and color burst value adjust */ 1646 writel_relaxed(mode->analog_sync_adj, 1647 priv->io_base + _REG(ENCI_SYNC_ADJ)); 1648 1649 priv->venc.current_mode = mode->mode_tag; 1650 } 1651 1652 /* Returns the current ENCI field polarity */ 1653 unsigned int meson_venci_get_field(struct meson_drm *priv) 1654 { 1655 return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29); 1656 } 1657 1658 void meson_venc_enable_vsync(struct meson_drm *priv) 1659 { 1660 writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL)); 1661 } 1662 1663 void meson_venc_disable_vsync(struct meson_drm *priv) 1664 { 1665 writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL)); 1666 } 1667 1668 void meson_venc_init(struct meson_drm *priv) 1669 { 1670 /* Disable CVBS VDAC */ 1671 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); 1672 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); 1673 1674 /* Power Down Dacs */ 1675 writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); 1676 1677 /* Disable HDMI PHY */ 1678 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); 1679 1680 /* Disable HDMI */ 1681 writel_bits_relaxed(0x3, 0, 1682 priv->io_base + _REG(VPU_HDMI_SETTING)); 1683 1684 /* Disable all encoders */ 1685 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 1686 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 1687 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); 1688 1689 /* Disable VSync IRQ */ 1690 meson_venc_disable_vsync(priv); 1691 1692 priv->venc.current_mode = MESON_VENC_MODE_NONE; 1693 } 1694