1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <drm/drmP.h> 23 #include "meson_drv.h" 24 #include "meson_venc.h" 25 #include "meson_vpp.h" 26 #include "meson_vclk.h" 27 #include "meson_registers.h" 28 29 /** 30 * DOC: Video Encoder 31 * 32 * VENC Handle the pixels encoding to the output formats. 33 * We handle the following encodings : 34 * 35 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter 36 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP 37 * - Setup of more clock rates for HDMI modes 38 * 39 * What is missing : 40 * 41 * - LCD Panel encoding via ENCL 42 * - TV Panel encoding via ENCT 43 * 44 * VENC paths : 45 * 46 * .. code:: 47 * 48 * _____ _____ ____________________ 49 * vd1---| |-| | | VENC /---------|----VDAC 50 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-| 51 * osd1--| |-| | | \ | X--HDMI-TX 52 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-| 53 * | | | 54 * | \--ENCL-----------|----LVDS 55 * |____________________| 56 * 57 * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC 58 * directly for CVBS encoding or through the ENCI_DVI encoder for HDMI. 59 * The ENCP is designed for Progressive encoding but can also generate 60 * 1080i interlaced pixels, and was initialy desined to encode pixels for 61 * VDAC to output RGB ou YUV analog outputs. 62 * It's output is only used through the ENCP_DVI encoder for HDMI. 63 * The ENCL LVDS encoder is not implemented. 64 * 65 * The ENCI and ENCP encoders needs specially defined parameters for each 66 * supported mode and thus cannot be determined from standard video timings. 67 * 68 * The ENCI end ENCP DVI encoders are more generic and can generate any timings 69 * from the pixel data generated by ENCI or ENCP, so can use the standard video 70 * timings are source for HW parameters. 71 */ 72 73 /* HHI Registers */ 74 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 75 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ 76 #define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */ 77 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ 78 #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ 79 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */ 80 81 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = { 82 .mode_tag = MESON_VENC_MODE_CVBS_PAL, 83 .hso_begin = 3, 84 .hso_end = 129, 85 .vso_even = 3, 86 .vso_odd = 260, 87 .macv_max_amp = 7, 88 .video_prog_mode = 0xff, 89 .video_mode = 0x13, 90 .sch_adjust = 0x28, 91 .yc_delay = 0x343, 92 .pixel_start = 251, 93 .pixel_end = 1691, 94 .top_field_line_start = 22, 95 .top_field_line_end = 310, 96 .bottom_field_line_start = 23, 97 .bottom_field_line_end = 311, 98 .video_saturation = 9, 99 .video_contrast = 0, 100 .video_brightness = 0, 101 .video_hue = 0, 102 .analog_sync_adj = 0x8080, 103 }; 104 105 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = { 106 .mode_tag = MESON_VENC_MODE_CVBS_NTSC, 107 .hso_begin = 5, 108 .hso_end = 129, 109 .vso_even = 3, 110 .vso_odd = 260, 111 .macv_max_amp = 0xb, 112 .video_prog_mode = 0xf0, 113 .video_mode = 0x8, 114 .sch_adjust = 0x20, 115 .yc_delay = 0x333, 116 .pixel_start = 227, 117 .pixel_end = 1667, 118 .top_field_line_start = 18, 119 .top_field_line_end = 258, 120 .bottom_field_line_start = 19, 121 .bottom_field_line_end = 259, 122 .video_saturation = 18, 123 .video_contrast = 3, 124 .video_brightness = 0, 125 .video_hue = 0, 126 .analog_sync_adj = 0x9c00, 127 }; 128 129 union meson_hdmi_venc_mode { 130 struct { 131 unsigned int mode_tag; 132 unsigned int hso_begin; 133 unsigned int hso_end; 134 unsigned int vso_even; 135 unsigned int vso_odd; 136 unsigned int macv_max_amp; 137 unsigned int video_prog_mode; 138 unsigned int video_mode; 139 unsigned int sch_adjust; 140 unsigned int yc_delay; 141 unsigned int pixel_start; 142 unsigned int pixel_end; 143 unsigned int top_field_line_start; 144 unsigned int top_field_line_end; 145 unsigned int bottom_field_line_start; 146 unsigned int bottom_field_line_end; 147 } enci; 148 struct { 149 unsigned int dvi_settings; 150 unsigned int video_mode; 151 unsigned int video_mode_adv; 152 unsigned int video_prog_mode; 153 bool video_prog_mode_present; 154 unsigned int video_sync_mode; 155 bool video_sync_mode_present; 156 unsigned int video_yc_dly; 157 bool video_yc_dly_present; 158 unsigned int video_rgb_ctrl; 159 bool video_rgb_ctrl_present; 160 unsigned int video_filt_ctrl; 161 bool video_filt_ctrl_present; 162 unsigned int video_ofld_voav_ofst; 163 bool video_ofld_voav_ofst_present; 164 unsigned int yfp1_htime; 165 unsigned int yfp2_htime; 166 unsigned int max_pxcnt; 167 unsigned int hspuls_begin; 168 unsigned int hspuls_end; 169 unsigned int hspuls_switch; 170 unsigned int vspuls_begin; 171 unsigned int vspuls_end; 172 unsigned int vspuls_bline; 173 unsigned int vspuls_eline; 174 unsigned int eqpuls_begin; 175 bool eqpuls_begin_present; 176 unsigned int eqpuls_end; 177 bool eqpuls_end_present; 178 unsigned int eqpuls_bline; 179 bool eqpuls_bline_present; 180 unsigned int eqpuls_eline; 181 bool eqpuls_eline_present; 182 unsigned int havon_begin; 183 unsigned int havon_end; 184 unsigned int vavon_bline; 185 unsigned int vavon_eline; 186 unsigned int hso_begin; 187 unsigned int hso_end; 188 unsigned int vso_begin; 189 unsigned int vso_end; 190 unsigned int vso_bline; 191 unsigned int vso_eline; 192 bool vso_eline_present; 193 unsigned int sy_val; 194 bool sy_val_present; 195 unsigned int sy2_val; 196 bool sy2_val_present; 197 unsigned int max_lncnt; 198 } encp; 199 }; 200 201 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = { 202 .enci = { 203 .hso_begin = 5, 204 .hso_end = 129, 205 .vso_even = 3, 206 .vso_odd = 260, 207 .macv_max_amp = 0x810b, 208 .video_prog_mode = 0xf0, 209 .video_mode = 0x8, 210 .sch_adjust = 0x20, 211 .yc_delay = 0, 212 .pixel_start = 227, 213 .pixel_end = 1667, 214 .top_field_line_start = 18, 215 .top_field_line_end = 258, 216 .bottom_field_line_start = 19, 217 .bottom_field_line_end = 259, 218 }, 219 }; 220 221 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = { 222 .enci = { 223 .hso_begin = 3, 224 .hso_end = 129, 225 .vso_even = 3, 226 .vso_odd = 260, 227 .macv_max_amp = 8107, 228 .video_prog_mode = 0xff, 229 .video_mode = 0x13, 230 .sch_adjust = 0x28, 231 .yc_delay = 0x333, 232 .pixel_start = 251, 233 .pixel_end = 1691, 234 .top_field_line_start = 22, 235 .top_field_line_end = 310, 236 .bottom_field_line_start = 23, 237 .bottom_field_line_end = 311, 238 }, 239 }; 240 241 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = { 242 .encp = { 243 .dvi_settings = 0x21, 244 .video_mode = 0x4000, 245 .video_mode_adv = 0x9, 246 .video_prog_mode = 0, 247 .video_prog_mode_present = true, 248 .video_sync_mode = 7, 249 .video_sync_mode_present = true, 250 /* video_yc_dly */ 251 /* video_rgb_ctrl */ 252 .video_filt_ctrl = 0x2052, 253 .video_filt_ctrl_present = true, 254 /* video_ofld_voav_ofst */ 255 .yfp1_htime = 244, 256 .yfp2_htime = 1630, 257 .max_pxcnt = 1715, 258 .hspuls_begin = 0x22, 259 .hspuls_end = 0xa0, 260 .hspuls_switch = 88, 261 .vspuls_begin = 0, 262 .vspuls_end = 1589, 263 .vspuls_bline = 0, 264 .vspuls_eline = 5, 265 .havon_begin = 249, 266 .havon_end = 1689, 267 .vavon_bline = 42, 268 .vavon_eline = 521, 269 /* eqpuls_begin */ 270 /* eqpuls_end */ 271 /* eqpuls_bline */ 272 /* eqpuls_eline */ 273 .hso_begin = 3, 274 .hso_end = 5, 275 .vso_begin = 3, 276 .vso_end = 5, 277 .vso_bline = 0, 278 /* vso_eline */ 279 .sy_val = 8, 280 .sy_val_present = true, 281 .sy2_val = 0x1d8, 282 .sy2_val_present = true, 283 .max_lncnt = 524, 284 }, 285 }; 286 287 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = { 288 .encp = { 289 .dvi_settings = 0x21, 290 .video_mode = 0x4000, 291 .video_mode_adv = 0x9, 292 .video_prog_mode = 0, 293 .video_prog_mode_present = true, 294 .video_sync_mode = 7, 295 .video_sync_mode_present = true, 296 /* video_yc_dly */ 297 /* video_rgb_ctrl */ 298 .video_filt_ctrl = 0x52, 299 .video_filt_ctrl_present = true, 300 /* video_ofld_voav_ofst */ 301 .yfp1_htime = 235, 302 .yfp2_htime = 1674, 303 .max_pxcnt = 1727, 304 .hspuls_begin = 0, 305 .hspuls_end = 0x80, 306 .hspuls_switch = 88, 307 .vspuls_begin = 0, 308 .vspuls_end = 1599, 309 .vspuls_bline = 0, 310 .vspuls_eline = 4, 311 .havon_begin = 235, 312 .havon_end = 1674, 313 .vavon_bline = 44, 314 .vavon_eline = 619, 315 /* eqpuls_begin */ 316 /* eqpuls_end */ 317 /* eqpuls_bline */ 318 /* eqpuls_eline */ 319 .hso_begin = 0x80, 320 .hso_end = 0, 321 .vso_begin = 0, 322 .vso_end = 5, 323 .vso_bline = 0, 324 /* vso_eline */ 325 .sy_val = 8, 326 .sy_val_present = true, 327 .sy2_val = 0x1d8, 328 .sy2_val_present = true, 329 .max_lncnt = 624, 330 }, 331 }; 332 333 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = { 334 .encp = { 335 .dvi_settings = 0x2029, 336 .video_mode = 0x4040, 337 .video_mode_adv = 0x19, 338 /* video_prog_mode */ 339 /* video_sync_mode */ 340 /* video_yc_dly */ 341 /* video_rgb_ctrl */ 342 /* video_filt_ctrl */ 343 /* video_ofld_voav_ofst */ 344 .yfp1_htime = 648, 345 .yfp2_htime = 3207, 346 .max_pxcnt = 3299, 347 .hspuls_begin = 80, 348 .hspuls_end = 240, 349 .hspuls_switch = 80, 350 .vspuls_begin = 688, 351 .vspuls_end = 3248, 352 .vspuls_bline = 4, 353 .vspuls_eline = 8, 354 .havon_begin = 648, 355 .havon_end = 3207, 356 .vavon_bline = 29, 357 .vavon_eline = 748, 358 /* eqpuls_begin */ 359 /* eqpuls_end */ 360 /* eqpuls_bline */ 361 /* eqpuls_eline */ 362 .hso_begin = 256, 363 .hso_end = 168, 364 .vso_begin = 168, 365 .vso_end = 256, 366 .vso_bline = 0, 367 .vso_eline = 5, 368 .vso_eline_present = true, 369 /* sy_val */ 370 /* sy2_val */ 371 .max_lncnt = 749, 372 }, 373 }; 374 375 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = { 376 .encp = { 377 .dvi_settings = 0x202d, 378 .video_mode = 0x4040, 379 .video_mode_adv = 0x19, 380 .video_prog_mode = 0x100, 381 .video_prog_mode_present = true, 382 .video_sync_mode = 0x407, 383 .video_sync_mode_present = true, 384 .video_yc_dly = 0, 385 .video_yc_dly_present = true, 386 /* video_rgb_ctrl */ 387 /* video_filt_ctrl */ 388 /* video_ofld_voav_ofst */ 389 .yfp1_htime = 648, 390 .yfp2_htime = 3207, 391 .max_pxcnt = 3959, 392 .hspuls_begin = 80, 393 .hspuls_end = 240, 394 .hspuls_switch = 80, 395 .vspuls_begin = 688, 396 .vspuls_end = 3248, 397 .vspuls_bline = 4, 398 .vspuls_eline = 8, 399 .havon_begin = 648, 400 .havon_end = 3207, 401 .vavon_bline = 29, 402 .vavon_eline = 748, 403 /* eqpuls_begin */ 404 /* eqpuls_end */ 405 /* eqpuls_bline */ 406 /* eqpuls_eline */ 407 .hso_begin = 128, 408 .hso_end = 208, 409 .vso_begin = 128, 410 .vso_end = 128, 411 .vso_bline = 0, 412 .vso_eline = 5, 413 .vso_eline_present = true, 414 /* sy_val */ 415 /* sy2_val */ 416 .max_lncnt = 749, 417 }, 418 }; 419 420 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = { 421 .encp = { 422 .dvi_settings = 0x2029, 423 .video_mode = 0x5ffc, 424 .video_mode_adv = 0x19, 425 .video_prog_mode = 0x100, 426 .video_prog_mode_present = true, 427 .video_sync_mode = 0x207, 428 .video_sync_mode_present = true, 429 /* video_yc_dly */ 430 /* video_rgb_ctrl */ 431 /* video_filt_ctrl */ 432 .video_ofld_voav_ofst = 0x11, 433 .video_ofld_voav_ofst_present = true, 434 .yfp1_htime = 516, 435 .yfp2_htime = 4355, 436 .max_pxcnt = 4399, 437 .hspuls_begin = 88, 438 .hspuls_end = 264, 439 .hspuls_switch = 88, 440 .vspuls_begin = 440, 441 .vspuls_end = 2200, 442 .vspuls_bline = 0, 443 .vspuls_eline = 4, 444 .havon_begin = 516, 445 .havon_end = 4355, 446 .vavon_bline = 20, 447 .vavon_eline = 559, 448 .eqpuls_begin = 2288, 449 .eqpuls_begin_present = true, 450 .eqpuls_end = 2464, 451 .eqpuls_end_present = true, 452 .eqpuls_bline = 0, 453 .eqpuls_bline_present = true, 454 .eqpuls_eline = 4, 455 .eqpuls_eline_present = true, 456 .hso_begin = 264, 457 .hso_end = 176, 458 .vso_begin = 88, 459 .vso_end = 88, 460 .vso_bline = 0, 461 .vso_eline = 5, 462 .vso_eline_present = true, 463 /* sy_val */ 464 /* sy2_val */ 465 .max_lncnt = 1124, 466 }, 467 }; 468 469 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = { 470 .encp = { 471 .dvi_settings = 0x202d, 472 .video_mode = 0x5ffc, 473 .video_mode_adv = 0x19, 474 .video_prog_mode = 0x100, 475 .video_prog_mode_present = true, 476 .video_sync_mode = 0x7, 477 .video_sync_mode_present = true, 478 /* video_yc_dly */ 479 /* video_rgb_ctrl */ 480 /* video_filt_ctrl */ 481 .video_ofld_voav_ofst = 0x11, 482 .video_ofld_voav_ofst_present = true, 483 .yfp1_htime = 526, 484 .yfp2_htime = 4365, 485 .max_pxcnt = 5279, 486 .hspuls_begin = 88, 487 .hspuls_end = 264, 488 .hspuls_switch = 88, 489 .vspuls_begin = 440, 490 .vspuls_end = 2200, 491 .vspuls_bline = 0, 492 .vspuls_eline = 4, 493 .havon_begin = 526, 494 .havon_end = 4365, 495 .vavon_bline = 20, 496 .vavon_eline = 559, 497 .eqpuls_begin = 2288, 498 .eqpuls_begin_present = true, 499 .eqpuls_end = 2464, 500 .eqpuls_end_present = true, 501 .eqpuls_bline = 0, 502 .eqpuls_bline_present = true, 503 .eqpuls_eline = 4, 504 .eqpuls_eline_present = true, 505 .hso_begin = 142, 506 .hso_end = 230, 507 .vso_begin = 142, 508 .vso_end = 142, 509 .vso_bline = 0, 510 .vso_eline = 5, 511 .vso_eline_present = true, 512 /* sy_val */ 513 /* sy2_val */ 514 .max_lncnt = 1124, 515 }, 516 }; 517 518 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = { 519 .encp = { 520 .dvi_settings = 0xd, 521 .video_mode = 0x4040, 522 .video_mode_adv = 0x18, 523 .video_prog_mode = 0x100, 524 .video_prog_mode_present = true, 525 .video_sync_mode = 0x7, 526 .video_sync_mode_present = true, 527 .video_yc_dly = 0, 528 .video_yc_dly_present = true, 529 .video_rgb_ctrl = 2, 530 .video_rgb_ctrl_present = true, 531 .video_filt_ctrl = 0x1052, 532 .video_filt_ctrl_present = true, 533 /* video_ofld_voav_ofst */ 534 .yfp1_htime = 271, 535 .yfp2_htime = 2190, 536 .max_pxcnt = 2749, 537 .hspuls_begin = 44, 538 .hspuls_end = 132, 539 .hspuls_switch = 44, 540 .vspuls_begin = 220, 541 .vspuls_end = 2140, 542 .vspuls_bline = 0, 543 .vspuls_eline = 4, 544 .havon_begin = 271, 545 .havon_end = 2190, 546 .vavon_bline = 41, 547 .vavon_eline = 1120, 548 /* eqpuls_begin */ 549 /* eqpuls_end */ 550 .eqpuls_bline = 0, 551 .eqpuls_bline_present = true, 552 .eqpuls_eline = 4, 553 .eqpuls_eline_present = true, 554 .hso_begin = 79, 555 .hso_end = 123, 556 .vso_begin = 79, 557 .vso_end = 79, 558 .vso_bline = 0, 559 .vso_eline = 5, 560 .vso_eline_present = true, 561 /* sy_val */ 562 /* sy2_val */ 563 .max_lncnt = 1124, 564 }, 565 }; 566 567 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = { 568 .encp = { 569 .dvi_settings = 0x1, 570 .video_mode = 0x4040, 571 .video_mode_adv = 0x18, 572 .video_prog_mode = 0x100, 573 .video_prog_mode_present = true, 574 /* video_sync_mode */ 575 /* video_yc_dly */ 576 /* video_rgb_ctrl */ 577 .video_filt_ctrl = 0x1052, 578 .video_filt_ctrl_present = true, 579 /* video_ofld_voav_ofst */ 580 .yfp1_htime = 140, 581 .yfp2_htime = 2060, 582 .max_pxcnt = 2199, 583 .hspuls_begin = 2156, 584 .hspuls_end = 44, 585 .hspuls_switch = 44, 586 .vspuls_begin = 140, 587 .vspuls_end = 2059, 588 .vspuls_bline = 0, 589 .vspuls_eline = 4, 590 .havon_begin = 148, 591 .havon_end = 2067, 592 .vavon_bline = 41, 593 .vavon_eline = 1120, 594 /* eqpuls_begin */ 595 /* eqpuls_end */ 596 /* eqpuls_bline */ 597 /* eqpuls_eline */ 598 .hso_begin = 44, 599 .hso_end = 2156, 600 .vso_begin = 2100, 601 .vso_end = 2164, 602 .vso_bline = 0, 603 .vso_eline = 5, 604 .vso_eline_present = true, 605 /* sy_val */ 606 /* sy2_val */ 607 .max_lncnt = 1124, 608 }, 609 }; 610 611 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = { 612 .encp = { 613 .dvi_settings = 0xd, 614 .video_mode = 0x4040, 615 .video_mode_adv = 0x18, 616 .video_prog_mode = 0x100, 617 .video_prog_mode_present = true, 618 .video_sync_mode = 0x7, 619 .video_sync_mode_present = true, 620 .video_yc_dly = 0, 621 .video_yc_dly_present = true, 622 .video_rgb_ctrl = 2, 623 .video_rgb_ctrl_present = true, 624 /* video_filt_ctrl */ 625 /* video_ofld_voav_ofst */ 626 .yfp1_htime = 271, 627 .yfp2_htime = 2190, 628 .max_pxcnt = 2639, 629 .hspuls_begin = 44, 630 .hspuls_end = 132, 631 .hspuls_switch = 44, 632 .vspuls_begin = 220, 633 .vspuls_end = 2140, 634 .vspuls_bline = 0, 635 .vspuls_eline = 4, 636 .havon_begin = 271, 637 .havon_end = 2190, 638 .vavon_bline = 41, 639 .vavon_eline = 1120, 640 /* eqpuls_begin */ 641 /* eqpuls_end */ 642 .eqpuls_bline = 0, 643 .eqpuls_bline_present = true, 644 .eqpuls_eline = 4, 645 .eqpuls_eline_present = true, 646 .hso_begin = 79, 647 .hso_end = 123, 648 .vso_begin = 79, 649 .vso_end = 79, 650 .vso_bline = 0, 651 .vso_eline = 5, 652 .vso_eline_present = true, 653 /* sy_val */ 654 /* sy2_val */ 655 .max_lncnt = 1124, 656 }, 657 }; 658 659 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = { 660 .encp = { 661 .dvi_settings = 0x1, 662 .video_mode = 0x4040, 663 .video_mode_adv = 0x18, 664 .video_prog_mode = 0x100, 665 .video_prog_mode_present = true, 666 /* video_sync_mode */ 667 /* video_yc_dly */ 668 /* video_rgb_ctrl */ 669 .video_filt_ctrl = 0x1052, 670 .video_filt_ctrl_present = true, 671 /* video_ofld_voav_ofst */ 672 .yfp1_htime = 140, 673 .yfp2_htime = 2060, 674 .max_pxcnt = 2199, 675 .hspuls_begin = 2156, 676 .hspuls_end = 44, 677 .hspuls_switch = 44, 678 .vspuls_begin = 140, 679 .vspuls_end = 2059, 680 .vspuls_bline = 0, 681 .vspuls_eline = 4, 682 .havon_begin = 148, 683 .havon_end = 2067, 684 .vavon_bline = 41, 685 .vavon_eline = 1120, 686 /* eqpuls_begin */ 687 /* eqpuls_end */ 688 /* eqpuls_bline */ 689 /* eqpuls_eline */ 690 .hso_begin = 44, 691 .hso_end = 2156, 692 .vso_begin = 2100, 693 .vso_end = 2164, 694 .vso_bline = 0, 695 .vso_eline = 5, 696 .vso_eline_present = true, 697 /* sy_val */ 698 /* sy2_val */ 699 .max_lncnt = 1124, 700 }, 701 }; 702 703 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = { 704 .encp = { 705 .dvi_settings = 0x1, 706 .video_mode = 0x4040, 707 .video_mode_adv = 0x8, 708 /* video_sync_mode */ 709 /* video_yc_dly */ 710 /* video_rgb_ctrl */ 711 .video_filt_ctrl = 0x1000, 712 .video_filt_ctrl_present = true, 713 /* video_ofld_voav_ofst */ 714 .yfp1_htime = 140, 715 .yfp2_htime = 140+3840, 716 .max_pxcnt = 3840+1660-1, 717 .hspuls_begin = 2156+1920, 718 .hspuls_end = 44, 719 .hspuls_switch = 44, 720 .vspuls_begin = 140, 721 .vspuls_end = 2059+1920, 722 .vspuls_bline = 0, 723 .vspuls_eline = 4, 724 .havon_begin = 148, 725 .havon_end = 3987, 726 .vavon_bline = 89, 727 .vavon_eline = 2248, 728 /* eqpuls_begin */ 729 /* eqpuls_end */ 730 /* eqpuls_bline */ 731 /* eqpuls_eline */ 732 .hso_begin = 44, 733 .hso_end = 2156+1920, 734 .vso_begin = 2100+1920, 735 .vso_end = 2164+1920, 736 .vso_bline = 51, 737 .vso_eline = 53, 738 .vso_eline_present = true, 739 /* sy_val */ 740 /* sy2_val */ 741 .max_lncnt = 2249, 742 }, 743 }; 744 745 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = { 746 .encp = { 747 .dvi_settings = 0x1, 748 .video_mode = 0x4040, 749 .video_mode_adv = 0x8, 750 /* video_sync_mode */ 751 /* video_yc_dly */ 752 /* video_rgb_ctrl */ 753 .video_filt_ctrl = 0x1000, 754 .video_filt_ctrl_present = true, 755 /* video_ofld_voav_ofst */ 756 .yfp1_htime = 140, 757 .yfp2_htime = 140+3840, 758 .max_pxcnt = 3840+1440-1, 759 .hspuls_begin = 2156+1920, 760 .hspuls_end = 44, 761 .hspuls_switch = 44, 762 .vspuls_begin = 140, 763 .vspuls_end = 2059+1920, 764 .vspuls_bline = 0, 765 .vspuls_eline = 4, 766 .havon_begin = 148, 767 .havon_end = 3987, 768 .vavon_bline = 89, 769 .vavon_eline = 2248, 770 /* eqpuls_begin */ 771 /* eqpuls_end */ 772 /* eqpuls_bline */ 773 /* eqpuls_eline */ 774 .hso_begin = 44, 775 .hso_end = 2156+1920, 776 .vso_begin = 2100+1920, 777 .vso_end = 2164+1920, 778 .vso_bline = 51, 779 .vso_eline = 53, 780 .vso_eline_present = true, 781 /* sy_val */ 782 /* sy2_val */ 783 .max_lncnt = 2249, 784 }, 785 }; 786 787 union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = { 788 .encp = { 789 .dvi_settings = 0x1, 790 .video_mode = 0x4040, 791 .video_mode_adv = 0x8, 792 /* video_sync_mode */ 793 /* video_yc_dly */ 794 /* video_rgb_ctrl */ 795 .video_filt_ctrl = 0x1000, 796 .video_filt_ctrl_present = true, 797 /* video_ofld_voav_ofst */ 798 .yfp1_htime = 140, 799 .yfp2_htime = 140+3840, 800 .max_pxcnt = 3840+560-1, 801 .hspuls_begin = 2156+1920, 802 .hspuls_end = 44, 803 .hspuls_switch = 44, 804 .vspuls_begin = 140, 805 .vspuls_end = 2059+1920, 806 .vspuls_bline = 0, 807 .vspuls_eline = 4, 808 .havon_begin = 148, 809 .havon_end = 3987, 810 .vavon_bline = 89, 811 .vavon_eline = 2248, 812 /* eqpuls_begin */ 813 /* eqpuls_end */ 814 /* eqpuls_bline */ 815 /* eqpuls_eline */ 816 .hso_begin = 44, 817 .hso_end = 2156+1920, 818 .vso_begin = 2100+1920, 819 .vso_end = 2164+1920, 820 .vso_bline = 51, 821 .vso_eline = 53, 822 .vso_eline_present = true, 823 /* sy_val */ 824 /* sy2_val */ 825 .max_lncnt = 2249, 826 }, 827 }; 828 829 struct meson_hdmi_venc_vic_mode { 830 unsigned int vic; 831 union meson_hdmi_venc_mode *mode; 832 } meson_hdmi_venc_vic_modes[] = { 833 { 6, &meson_hdmi_enci_mode_480i }, 834 { 7, &meson_hdmi_enci_mode_480i }, 835 { 21, &meson_hdmi_enci_mode_576i }, 836 { 22, &meson_hdmi_enci_mode_576i }, 837 { 2, &meson_hdmi_encp_mode_480p }, 838 { 3, &meson_hdmi_encp_mode_480p }, 839 { 17, &meson_hdmi_encp_mode_576p }, 840 { 18, &meson_hdmi_encp_mode_576p }, 841 { 4, &meson_hdmi_encp_mode_720p60 }, 842 { 19, &meson_hdmi_encp_mode_720p50 }, 843 { 5, &meson_hdmi_encp_mode_1080i60 }, 844 { 20, &meson_hdmi_encp_mode_1080i50 }, 845 { 32, &meson_hdmi_encp_mode_1080p24 }, 846 { 33, &meson_hdmi_encp_mode_1080p50 }, 847 { 34, &meson_hdmi_encp_mode_1080p30 }, 848 { 31, &meson_hdmi_encp_mode_1080p50 }, 849 { 16, &meson_hdmi_encp_mode_1080p60 }, 850 { 93, &meson_hdmi_encp_mode_2160p24 }, 851 { 94, &meson_hdmi_encp_mode_2160p25 }, 852 { 95, &meson_hdmi_encp_mode_2160p30 }, 853 { 96, &meson_hdmi_encp_mode_2160p25 }, 854 { 97, &meson_hdmi_encp_mode_2160p30 }, 855 { 0, NULL}, /* sentinel */ 856 }; 857 858 static signed int to_signed(unsigned int a) 859 { 860 if (a <= 7) 861 return a; 862 else 863 return a - 16; 864 } 865 866 static unsigned long modulo(unsigned long a, unsigned long b) 867 { 868 if (a >= b) 869 return a - b; 870 else 871 return a; 872 } 873 874 enum drm_mode_status 875 meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode) 876 { 877 if (mode->flags & ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | 878 DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)) 879 return MODE_BAD; 880 881 if (mode->hdisplay < 640 || mode->hdisplay > 1920) 882 return MODE_BAD_HVALUE; 883 884 if (mode->vdisplay < 480 || mode->vdisplay > 1200) 885 return MODE_BAD_VVALUE; 886 887 return MODE_OK; 888 } 889 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode); 890 891 bool meson_venc_hdmi_supported_vic(int vic) 892 { 893 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; 894 895 while (vmode->vic && vmode->mode) { 896 if (vmode->vic == vic) 897 return true; 898 vmode++; 899 } 900 901 return false; 902 } 903 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic); 904 905 void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode, 906 union meson_hdmi_venc_mode *dmt_mode) 907 { 908 memset(dmt_mode, 0, sizeof(*dmt_mode)); 909 910 dmt_mode->encp.dvi_settings = 0x21; 911 dmt_mode->encp.video_mode = 0x4040; 912 dmt_mode->encp.video_mode_adv = 0x18; 913 dmt_mode->encp.max_pxcnt = mode->htotal - 1; 914 dmt_mode->encp.havon_begin = mode->htotal - mode->hsync_start; 915 dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin + 916 mode->hdisplay - 1; 917 dmt_mode->encp.vavon_bline = mode->vtotal - mode->vsync_start; 918 dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline + 919 mode->vdisplay - 1; 920 dmt_mode->encp.hso_begin = 0; 921 dmt_mode->encp.hso_end = mode->hsync_end - mode->hsync_start; 922 dmt_mode->encp.vso_begin = 30; 923 dmt_mode->encp.vso_end = 50; 924 dmt_mode->encp.vso_bline = 0; 925 dmt_mode->encp.vso_eline = mode->vsync_end - mode->vsync_start; 926 dmt_mode->encp.vso_eline_present = true; 927 dmt_mode->encp.max_lncnt = mode->vtotal - 1; 928 } 929 930 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic) 931 { 932 struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes; 933 934 while (vmode->vic && vmode->mode) { 935 if (vmode->vic == vic) 936 return vmode->mode; 937 vmode++; 938 } 939 940 return NULL; 941 } 942 943 bool meson_venc_hdmi_venc_repeat(int vic) 944 { 945 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ 946 if (vic == 6 || vic == 7 || /* 480i */ 947 vic == 21 || vic == 22 || /* 576i */ 948 vic == 17 || vic == 18 || /* 576p */ 949 vic == 2 || vic == 3 || /* 480p */ 950 vic == 4 || /* 720p60 */ 951 vic == 19 || /* 720p50 */ 952 vic == 5 || /* 1080i60 */ 953 vic == 20) /* 1080i50 */ 954 return true; 955 956 return false; 957 } 958 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat); 959 960 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, 961 struct drm_display_mode *mode) 962 { 963 union meson_hdmi_venc_mode *vmode = NULL; 964 union meson_hdmi_venc_mode vmode_dmt; 965 bool use_enci = false; 966 bool venc_repeat = false; 967 bool hdmi_repeat = false; 968 unsigned int venc_hdmi_latency = 2; 969 unsigned long total_pixels_venc = 0; 970 unsigned long active_pixels_venc = 0; 971 unsigned long front_porch_venc = 0; 972 unsigned long hsync_pixels_venc = 0; 973 unsigned long de_h_begin = 0; 974 unsigned long de_h_end = 0; 975 unsigned long de_v_begin_even = 0; 976 unsigned long de_v_end_even = 0; 977 unsigned long de_v_begin_odd = 0; 978 unsigned long de_v_end_odd = 0; 979 unsigned long hs_begin = 0; 980 unsigned long hs_end = 0; 981 unsigned long vs_adjust = 0; 982 unsigned long vs_bline_evn = 0; 983 unsigned long vs_eline_evn = 0; 984 unsigned long vs_bline_odd = 0; 985 unsigned long vs_eline_odd = 0; 986 unsigned long vso_begin_evn = 0; 987 unsigned long vso_begin_odd = 0; 988 unsigned int eof_lines; 989 unsigned int sof_lines; 990 unsigned int vsync_lines; 991 992 /* Use VENCI for 480i and 576i and double HDMI pixels */ 993 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 994 hdmi_repeat = true; 995 use_enci = true; 996 venc_hdmi_latency = 1; 997 } 998 999 if (meson_venc_hdmi_supported_vic(vic)) { 1000 vmode = meson_venc_hdmi_get_vic_vmode(vic); 1001 if (!vmode) { 1002 dev_err(priv->dev, "%s: Fatal Error, unsupported mode " 1003 DRM_MODE_FMT "\n", __func__, 1004 DRM_MODE_ARG(mode)); 1005 return; 1006 } 1007 } else { 1008 meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt); 1009 vmode = &vmode_dmt; 1010 use_enci = false; 1011 } 1012 1013 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ 1014 if (meson_venc_hdmi_venc_repeat(vic)) 1015 venc_repeat = true; 1016 1017 eof_lines = mode->vsync_start - mode->vdisplay; 1018 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1019 eof_lines /= 2; 1020 sof_lines = mode->vtotal - mode->vsync_end; 1021 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1022 sof_lines /= 2; 1023 vsync_lines = mode->vsync_end - mode->vsync_start; 1024 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1025 vsync_lines /= 2; 1026 1027 total_pixels_venc = mode->htotal; 1028 if (hdmi_repeat) 1029 total_pixels_venc /= 2; 1030 if (venc_repeat) 1031 total_pixels_venc *= 2; 1032 1033 active_pixels_venc = mode->hdisplay; 1034 if (hdmi_repeat) 1035 active_pixels_venc /= 2; 1036 if (venc_repeat) 1037 active_pixels_venc *= 2; 1038 1039 front_porch_venc = (mode->hsync_start - mode->hdisplay); 1040 if (hdmi_repeat) 1041 front_porch_venc /= 2; 1042 if (venc_repeat) 1043 front_porch_venc *= 2; 1044 1045 hsync_pixels_venc = (mode->hsync_end - mode->hsync_start); 1046 if (hdmi_repeat) 1047 hsync_pixels_venc /= 2; 1048 if (venc_repeat) 1049 hsync_pixels_venc *= 2; 1050 1051 /* Disable VDACs */ 1052 writel_bits_relaxed(0xff, 0xff, 1053 priv->io_base + _REG(VENC_VDAC_SETTING)); 1054 1055 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 1056 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 1057 1058 if (use_enci) { 1059 unsigned int lines_f0; 1060 unsigned int lines_f1; 1061 1062 /* CVBS Filter settings */ 1063 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 1064 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1065 1066 /* Digital Video Select : Interlace, clk27 clk, external */ 1067 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); 1068 1069 /* Reset Video Mode */ 1070 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); 1071 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1072 1073 /* Horizontal sync signal output */ 1074 writel_relaxed(vmode->enci.hso_begin, 1075 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); 1076 writel_relaxed(vmode->enci.hso_end, 1077 priv->io_base + _REG(ENCI_SYNC_HSO_END)); 1078 1079 /* Vertical Sync lines */ 1080 writel_relaxed(vmode->enci.vso_even, 1081 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN)); 1082 writel_relaxed(vmode->enci.vso_odd, 1083 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 1084 1085 /* Macrovision max amplitude change */ 1086 writel_relaxed(vmode->enci.macv_max_amp, 1087 priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1088 1089 /* Video mode */ 1090 writel_relaxed(vmode->enci.video_prog_mode, 1091 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1092 writel_relaxed(vmode->enci.video_mode, 1093 priv->io_base + _REG(ENCI_VIDEO_MODE)); 1094 1095 /* Advanced Video Mode : 1096 * Demux shifting 0x2 1097 * Blank line end at line17/22 1098 * High bandwidth Luma Filter 1099 * Low bandwidth Chroma Filter 1100 * Bypass luma low pass filter 1101 * No macrovision on CSYNC 1102 */ 1103 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1104 1105 writel(vmode->enci.sch_adjust, 1106 priv->io_base + _REG(ENCI_VIDEO_SCH)); 1107 1108 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */ 1109 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE)); 1110 1111 if (vmode->enci.yc_delay) 1112 writel_relaxed(vmode->enci.yc_delay, 1113 priv->io_base + _REG(ENCI_YC_DELAY)); 1114 1115 1116 /* UNreset Interlaced TV Encoder */ 1117 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 1118 1119 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 1120 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1121 1122 /* Timings */ 1123 writel_relaxed(vmode->enci.pixel_start, 1124 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START)); 1125 writel_relaxed(vmode->enci.pixel_end, 1126 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END)); 1127 1128 writel_relaxed(vmode->enci.top_field_line_start, 1129 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1130 writel_relaxed(vmode->enci.top_field_line_end, 1131 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END)); 1132 1133 writel_relaxed(vmode->enci.bottom_field_line_start, 1134 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1135 writel_relaxed(vmode->enci.bottom_field_line_end, 1136 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END)); 1137 1138 /* Select ENCI for VIU */ 1139 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1140 1141 /* Interlace video enable */ 1142 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1143 1144 lines_f0 = mode->vtotal >> 1; 1145 lines_f1 = lines_f0 + 1; 1146 1147 de_h_begin = modulo(readl_relaxed(priv->io_base + 1148 _REG(ENCI_VFIFO2VD_PIXEL_START)) 1149 + venc_hdmi_latency, 1150 total_pixels_venc); 1151 de_h_end = modulo(de_h_begin + active_pixels_venc, 1152 total_pixels_venc); 1153 1154 writel_relaxed(de_h_begin, 1155 priv->io_base + _REG(ENCI_DE_H_BEGIN)); 1156 writel_relaxed(de_h_end, 1157 priv->io_base + _REG(ENCI_DE_H_END)); 1158 1159 de_v_begin_even = readl_relaxed(priv->io_base + 1160 _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1161 de_v_end_even = de_v_begin_even + mode->vdisplay; 1162 de_v_begin_odd = readl_relaxed(priv->io_base + 1163 _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1164 de_v_end_odd = de_v_begin_odd + mode->vdisplay; 1165 1166 writel_relaxed(de_v_begin_even, 1167 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN)); 1168 writel_relaxed(de_v_end_even, 1169 priv->io_base + _REG(ENCI_DE_V_END_EVEN)); 1170 writel_relaxed(de_v_begin_odd, 1171 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD)); 1172 writel_relaxed(de_v_end_odd, 1173 priv->io_base + _REG(ENCI_DE_V_END_ODD)); 1174 1175 /* Program Hsync timing */ 1176 hs_begin = de_h_end + front_porch_venc; 1177 if (de_h_end + front_porch_venc >= total_pixels_venc) { 1178 hs_begin -= total_pixels_venc; 1179 vs_adjust = 1; 1180 } else { 1181 hs_begin = de_h_end + front_porch_venc; 1182 vs_adjust = 0; 1183 } 1184 1185 hs_end = modulo(hs_begin + hsync_pixels_venc, 1186 total_pixels_venc); 1187 writel_relaxed(hs_begin, 1188 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN)); 1189 writel_relaxed(hs_end, 1190 priv->io_base + _REG(ENCI_DVI_HSO_END)); 1191 1192 /* Program Vsync timing for even field */ 1193 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) { 1194 vs_bline_evn = (de_v_end_odd - 1) 1195 + eof_lines 1196 + vs_adjust 1197 - lines_f1; 1198 vs_eline_evn = vs_bline_evn + vsync_lines; 1199 1200 writel_relaxed(vs_bline_evn, 1201 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN)); 1202 1203 writel_relaxed(vs_eline_evn, 1204 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1205 1206 writel_relaxed(hs_begin, 1207 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN)); 1208 writel_relaxed(hs_begin, 1209 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN)); 1210 } else { 1211 vs_bline_odd = (de_v_end_odd - 1) 1212 + eof_lines 1213 + vs_adjust; 1214 1215 writel_relaxed(vs_bline_odd, 1216 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD)); 1217 1218 writel_relaxed(hs_begin, 1219 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD)); 1220 1221 if ((vs_bline_odd + vsync_lines) >= lines_f1) { 1222 vs_eline_evn = vs_bline_odd 1223 + vsync_lines 1224 - lines_f1; 1225 1226 writel_relaxed(vs_eline_evn, priv->io_base 1227 + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1228 1229 writel_relaxed(hs_begin, priv->io_base 1230 + _REG(ENCI_DVI_VSO_END_EVN)); 1231 } else { 1232 vs_eline_odd = vs_bline_odd 1233 + vsync_lines; 1234 1235 writel_relaxed(vs_eline_odd, priv->io_base 1236 + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1237 1238 writel_relaxed(hs_begin, priv->io_base 1239 + _REG(ENCI_DVI_VSO_END_ODD)); 1240 } 1241 } 1242 1243 /* Program Vsync timing for odd field */ 1244 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) { 1245 vs_bline_odd = (de_v_end_even - 1) 1246 + (eof_lines + 1) 1247 - lines_f0; 1248 vs_eline_odd = vs_bline_odd + vsync_lines; 1249 1250 writel_relaxed(vs_bline_odd, 1251 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD)); 1252 1253 writel_relaxed(vs_eline_odd, 1254 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1255 1256 vso_begin_odd = modulo(hs_begin 1257 + (total_pixels_venc >> 1), 1258 total_pixels_venc); 1259 1260 writel_relaxed(vso_begin_odd, 1261 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD)); 1262 writel_relaxed(vso_begin_odd, 1263 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD)); 1264 } else { 1265 vs_bline_evn = (de_v_end_even - 1) 1266 + (eof_lines + 1); 1267 1268 writel_relaxed(vs_bline_evn, 1269 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN)); 1270 1271 vso_begin_evn = modulo(hs_begin 1272 + (total_pixels_venc >> 1), 1273 total_pixels_venc); 1274 1275 writel_relaxed(vso_begin_evn, priv->io_base 1276 + _REG(ENCI_DVI_VSO_BEGIN_EVN)); 1277 1278 if (vs_bline_evn + vsync_lines >= lines_f0) { 1279 vs_eline_odd = vs_bline_evn 1280 + vsync_lines 1281 - lines_f0; 1282 1283 writel_relaxed(vs_eline_odd, priv->io_base 1284 + _REG(ENCI_DVI_VSO_ELINE_ODD)); 1285 1286 writel_relaxed(vso_begin_evn, priv->io_base 1287 + _REG(ENCI_DVI_VSO_END_ODD)); 1288 } else { 1289 vs_eline_evn = vs_bline_evn + vsync_lines; 1290 1291 writel_relaxed(vs_eline_evn, priv->io_base 1292 + _REG(ENCI_DVI_VSO_ELINE_EVN)); 1293 1294 writel_relaxed(vso_begin_evn, priv->io_base 1295 + _REG(ENCI_DVI_VSO_END_EVN)); 1296 } 1297 } 1298 } else { 1299 writel_relaxed(vmode->encp.dvi_settings, 1300 priv->io_base + _REG(VENC_DVI_SETTING)); 1301 writel_relaxed(vmode->encp.video_mode, 1302 priv->io_base + _REG(ENCP_VIDEO_MODE)); 1303 writel_relaxed(vmode->encp.video_mode_adv, 1304 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV)); 1305 if (vmode->encp.video_prog_mode_present) 1306 writel_relaxed(vmode->encp.video_prog_mode, 1307 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1308 if (vmode->encp.video_sync_mode_present) 1309 writel_relaxed(vmode->encp.video_sync_mode, 1310 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE)); 1311 if (vmode->encp.video_yc_dly_present) 1312 writel_relaxed(vmode->encp.video_yc_dly, 1313 priv->io_base + _REG(ENCP_VIDEO_YC_DLY)); 1314 if (vmode->encp.video_rgb_ctrl_present) 1315 writel_relaxed(vmode->encp.video_rgb_ctrl, 1316 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL)); 1317 if (vmode->encp.video_filt_ctrl_present) 1318 writel_relaxed(vmode->encp.video_filt_ctrl, 1319 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL)); 1320 if (vmode->encp.video_ofld_voav_ofst_present) 1321 writel_relaxed(vmode->encp.video_ofld_voav_ofst, 1322 priv->io_base 1323 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST)); 1324 writel_relaxed(vmode->encp.yfp1_htime, 1325 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME)); 1326 writel_relaxed(vmode->encp.yfp2_htime, 1327 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME)); 1328 writel_relaxed(vmode->encp.max_pxcnt, 1329 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT)); 1330 writel_relaxed(vmode->encp.hspuls_begin, 1331 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN)); 1332 writel_relaxed(vmode->encp.hspuls_end, 1333 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END)); 1334 writel_relaxed(vmode->encp.hspuls_switch, 1335 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH)); 1336 writel_relaxed(vmode->encp.vspuls_begin, 1337 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN)); 1338 writel_relaxed(vmode->encp.vspuls_end, 1339 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END)); 1340 writel_relaxed(vmode->encp.vspuls_bline, 1341 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE)); 1342 writel_relaxed(vmode->encp.vspuls_eline, 1343 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE)); 1344 if (vmode->encp.eqpuls_begin_present) 1345 writel_relaxed(vmode->encp.eqpuls_begin, 1346 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN)); 1347 if (vmode->encp.eqpuls_end_present) 1348 writel_relaxed(vmode->encp.eqpuls_end, 1349 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END)); 1350 if (vmode->encp.eqpuls_bline_present) 1351 writel_relaxed(vmode->encp.eqpuls_bline, 1352 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE)); 1353 if (vmode->encp.eqpuls_eline_present) 1354 writel_relaxed(vmode->encp.eqpuls_eline, 1355 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE)); 1356 writel_relaxed(vmode->encp.havon_begin, 1357 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN)); 1358 writel_relaxed(vmode->encp.havon_end, 1359 priv->io_base + _REG(ENCP_VIDEO_HAVON_END)); 1360 writel_relaxed(vmode->encp.vavon_bline, 1361 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE)); 1362 writel_relaxed(vmode->encp.vavon_eline, 1363 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE)); 1364 writel_relaxed(vmode->encp.hso_begin, 1365 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN)); 1366 writel_relaxed(vmode->encp.hso_end, 1367 priv->io_base + _REG(ENCP_VIDEO_HSO_END)); 1368 writel_relaxed(vmode->encp.vso_begin, 1369 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN)); 1370 writel_relaxed(vmode->encp.vso_end, 1371 priv->io_base + _REG(ENCP_VIDEO_VSO_END)); 1372 writel_relaxed(vmode->encp.vso_bline, 1373 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE)); 1374 if (vmode->encp.vso_eline_present) 1375 writel_relaxed(vmode->encp.vso_eline, 1376 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE)); 1377 if (vmode->encp.sy_val_present) 1378 writel_relaxed(vmode->encp.sy_val, 1379 priv->io_base + _REG(ENCP_VIDEO_SY_VAL)); 1380 if (vmode->encp.sy2_val_present) 1381 writel_relaxed(vmode->encp.sy2_val, 1382 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL)); 1383 writel_relaxed(vmode->encp.max_lncnt, 1384 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT)); 1385 1386 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); 1387 1388 /* Set DE signal’s polarity is active high */ 1389 writel_bits_relaxed(BIT(14), BIT(14), 1390 priv->io_base + _REG(ENCP_VIDEO_MODE)); 1391 1392 /* Program DE timing */ 1393 de_h_begin = modulo(readl_relaxed(priv->io_base + 1394 _REG(ENCP_VIDEO_HAVON_BEGIN)) 1395 + venc_hdmi_latency, 1396 total_pixels_venc); 1397 de_h_end = modulo(de_h_begin + active_pixels_venc, 1398 total_pixels_venc); 1399 1400 writel_relaxed(de_h_begin, 1401 priv->io_base + _REG(ENCP_DE_H_BEGIN)); 1402 writel_relaxed(de_h_end, 1403 priv->io_base + _REG(ENCP_DE_H_END)); 1404 1405 /* Program DE timing for even field */ 1406 de_v_begin_even = readl_relaxed(priv->io_base 1407 + _REG(ENCP_VIDEO_VAVON_BLINE)); 1408 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1409 de_v_end_even = de_v_begin_even + 1410 (mode->vdisplay / 2); 1411 else 1412 de_v_end_even = de_v_begin_even + mode->vdisplay; 1413 1414 writel_relaxed(de_v_begin_even, 1415 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN)); 1416 writel_relaxed(de_v_end_even, 1417 priv->io_base + _REG(ENCP_DE_V_END_EVEN)); 1418 1419 /* Program DE timing for odd field if needed */ 1420 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1421 unsigned int ofld_voav_ofst = 1422 readl_relaxed(priv->io_base + 1423 _REG(ENCP_VIDEO_OFLD_VOAV_OFST)); 1424 de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4) 1425 + de_v_begin_even 1426 + ((mode->vtotal - 1) / 2); 1427 de_v_end_odd = de_v_begin_odd + (mode->vdisplay / 2); 1428 1429 writel_relaxed(de_v_begin_odd, 1430 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD)); 1431 writel_relaxed(de_v_end_odd, 1432 priv->io_base + _REG(ENCP_DE_V_END_ODD)); 1433 } 1434 1435 /* Program Hsync timing */ 1436 if ((de_h_end + front_porch_venc) >= total_pixels_venc) { 1437 hs_begin = de_h_end 1438 + front_porch_venc 1439 - total_pixels_venc; 1440 vs_adjust = 1; 1441 } else { 1442 hs_begin = de_h_end 1443 + front_porch_venc; 1444 vs_adjust = 0; 1445 } 1446 1447 hs_end = modulo(hs_begin + hsync_pixels_venc, 1448 total_pixels_venc); 1449 1450 writel_relaxed(hs_begin, 1451 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN)); 1452 writel_relaxed(hs_end, 1453 priv->io_base + _REG(ENCP_DVI_HSO_END)); 1454 1455 /* Program Vsync timing for even field */ 1456 if (de_v_begin_even >= 1457 (sof_lines + vsync_lines + (1 - vs_adjust))) 1458 vs_bline_evn = de_v_begin_even 1459 - sof_lines 1460 - vsync_lines 1461 - (1 - vs_adjust); 1462 else 1463 vs_bline_evn = mode->vtotal 1464 + de_v_begin_even 1465 - sof_lines 1466 - vsync_lines 1467 - (1 - vs_adjust); 1468 1469 vs_eline_evn = modulo(vs_bline_evn + vsync_lines, 1470 mode->vtotal); 1471 1472 writel_relaxed(vs_bline_evn, 1473 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN)); 1474 writel_relaxed(vs_eline_evn, 1475 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN)); 1476 1477 vso_begin_evn = hs_begin; 1478 writel_relaxed(vso_begin_evn, 1479 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN)); 1480 writel_relaxed(vso_begin_evn, 1481 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN)); 1482 1483 /* Program Vsync timing for odd field if needed */ 1484 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1485 vs_bline_odd = (de_v_begin_odd - 1) 1486 - sof_lines 1487 - vsync_lines; 1488 vs_eline_odd = (de_v_begin_odd - 1) 1489 - vsync_lines; 1490 vso_begin_odd = modulo(hs_begin 1491 + (total_pixels_venc >> 1), 1492 total_pixels_venc); 1493 1494 writel_relaxed(vs_bline_odd, 1495 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD)); 1496 writel_relaxed(vs_eline_odd, 1497 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD)); 1498 writel_relaxed(vso_begin_odd, 1499 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD)); 1500 writel_relaxed(vso_begin_odd, 1501 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD)); 1502 } 1503 1504 /* Select ENCP for VIU */ 1505 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP); 1506 } 1507 1508 writel_relaxed((use_enci ? 1 : 2) | 1509 (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) | 1510 (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) | 1511 4 << 5 | 1512 (venc_repeat ? 1 << 8 : 0) | 1513 (hdmi_repeat ? 1 << 12 : 0), 1514 priv->io_base + _REG(VPU_HDMI_SETTING)); 1515 1516 priv->venc.hdmi_repeat = hdmi_repeat; 1517 priv->venc.venc_repeat = venc_repeat; 1518 priv->venc.hdmi_use_enci = use_enci; 1519 1520 priv->venc.current_mode = MESON_VENC_MODE_HDMI; 1521 } 1522 EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set); 1523 1524 void meson_venci_cvbs_mode_set(struct meson_drm *priv, 1525 struct meson_cvbs_enci_mode *mode) 1526 { 1527 if (mode->mode_tag == priv->venc.current_mode) 1528 return; 1529 1530 /* CVBS Filter settings */ 1531 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 1532 writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1533 1534 /* Digital Video Select : Interlace, clk27 clk, external */ 1535 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); 1536 1537 /* Reset Video Mode */ 1538 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); 1539 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1540 1541 /* Horizontal sync signal output */ 1542 writel_relaxed(mode->hso_begin, 1543 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); 1544 writel_relaxed(mode->hso_end, 1545 priv->io_base + _REG(ENCI_SYNC_HSO_END)); 1546 1547 /* Vertical Sync lines */ 1548 writel_relaxed(mode->vso_even, 1549 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN)); 1550 writel_relaxed(mode->vso_odd, 1551 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 1552 1553 /* Macrovision max amplitude change */ 1554 writel_relaxed(0x8100 + mode->macv_max_amp, 1555 priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1556 1557 /* Video mode */ 1558 writel_relaxed(mode->video_prog_mode, 1559 priv->io_base + _REG(VENC_VIDEO_PROG_MODE)); 1560 writel_relaxed(mode->video_mode, 1561 priv->io_base + _REG(ENCI_VIDEO_MODE)); 1562 1563 /* Advanced Video Mode : 1564 * Demux shifting 0x2 1565 * Blank line end at line17/22 1566 * High bandwidth Luma Filter 1567 * Low bandwidth Chroma Filter 1568 * Bypass luma low pass filter 1569 * No macrovision on CSYNC 1570 */ 1571 writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1572 1573 writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH)); 1574 1575 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */ 1576 writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE)); 1577 1578 /* 0x3 Y, C, and Component Y delay */ 1579 writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY)); 1580 1581 /* Timings */ 1582 writel_relaxed(mode->pixel_start, 1583 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START)); 1584 writel_relaxed(mode->pixel_end, 1585 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END)); 1586 1587 writel_relaxed(mode->top_field_line_start, 1588 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START)); 1589 writel_relaxed(mode->top_field_line_end, 1590 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END)); 1591 1592 writel_relaxed(mode->bottom_field_line_start, 1593 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START)); 1594 writel_relaxed(mode->bottom_field_line_end, 1595 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END)); 1596 1597 /* Internal Venc, Internal VIU Sync, Internal Vencoder */ 1598 writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE)); 1599 1600 /* UNreset Interlaced TV Encoder */ 1601 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 1602 1603 /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 1604 writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1605 1606 /* Power UP Dacs */ 1607 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING)); 1608 1609 /* Video Upsampling */ 1610 writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0)); 1611 writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1)); 1612 writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2)); 1613 1614 /* Select Interlace Y DACs */ 1615 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0)); 1616 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1)); 1617 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2)); 1618 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3)); 1619 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4)); 1620 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5)); 1621 1622 /* Select ENCI for VIU */ 1623 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1624 1625 /* Enable ENCI FIFO */ 1626 writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL)); 1627 1628 /* Select ENCI DACs 0, 1, 4, and 5 */ 1629 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0)); 1630 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1)); 1631 1632 /* Interlace video enable */ 1633 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1634 1635 /* Configure Video Saturation / Contrast / Brightness / Hue */ 1636 writel_relaxed(mode->video_saturation, 1637 priv->io_base + _REG(ENCI_VIDEO_SAT)); 1638 writel_relaxed(mode->video_contrast, 1639 priv->io_base + _REG(ENCI_VIDEO_CONT)); 1640 writel_relaxed(mode->video_brightness, 1641 priv->io_base + _REG(ENCI_VIDEO_BRIGHT)); 1642 writel_relaxed(mode->video_hue, 1643 priv->io_base + _REG(ENCI_VIDEO_HUE)); 1644 1645 /* Enable DAC0 Filter */ 1646 writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0)); 1647 writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1)); 1648 1649 /* 0 in Macrovision register 0 */ 1650 writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0)); 1651 1652 /* Analog Synchronization and color burst value adjust */ 1653 writel_relaxed(mode->analog_sync_adj, 1654 priv->io_base + _REG(ENCI_SYNC_ADJ)); 1655 1656 priv->venc.current_mode = mode->mode_tag; 1657 } 1658 1659 /* Returns the current ENCI field polarity */ 1660 unsigned int meson_venci_get_field(struct meson_drm *priv) 1661 { 1662 return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29); 1663 } 1664 1665 void meson_venc_enable_vsync(struct meson_drm *priv) 1666 { 1667 writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL)); 1668 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); 1669 } 1670 1671 void meson_venc_disable_vsync(struct meson_drm *priv) 1672 { 1673 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); 1674 writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL)); 1675 } 1676 1677 void meson_venc_init(struct meson_drm *priv) 1678 { 1679 /* Disable CVBS VDAC */ 1680 if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 1681 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); 1682 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8); 1683 } else { 1684 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); 1685 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); 1686 } 1687 1688 /* Power Down Dacs */ 1689 writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); 1690 1691 /* Disable HDMI PHY */ 1692 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); 1693 1694 /* Disable HDMI */ 1695 writel_bits_relaxed(0x3, 0, 1696 priv->io_base + _REG(VPU_HDMI_SETTING)); 1697 1698 /* Disable all encoders */ 1699 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 1700 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 1701 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); 1702 1703 /* Disable VSync IRQ */ 1704 meson_venc_disable_vsync(priv); 1705 1706 priv->venc.current_mode = MESON_VENC_MODE_NONE; 1707 } 1708