1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * Copyright (C) 2014 Endless Mobile 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of the 10 * License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Written by: 21 * Jasper St. Pierre <jstpierre@mecheye.net> 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/platform_device.h> 28 #include <drm/drmP.h> 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_plane_helper.h> 32 #include <drm/drm_gem_cma_helper.h> 33 #include <drm/drm_fb_cma_helper.h> 34 #include <drm/drm_rect.h> 35 36 #include "meson_plane.h" 37 #include "meson_vpp.h" 38 #include "meson_viu.h" 39 #include "meson_canvas.h" 40 #include "meson_registers.h" 41 42 struct meson_plane { 43 struct drm_plane base; 44 struct meson_drm *priv; 45 }; 46 #define to_meson_plane(x) container_of(x, struct meson_plane, base) 47 48 static int meson_plane_atomic_check(struct drm_plane *plane, 49 struct drm_plane_state *state) 50 { 51 struct drm_crtc_state *crtc_state; 52 53 if (!state->crtc) 54 return 0; 55 56 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 57 if (IS_ERR(crtc_state)) 58 return PTR_ERR(crtc_state); 59 60 return drm_atomic_helper_check_plane_state(state, crtc_state, 61 DRM_PLANE_HELPER_NO_SCALING, 62 DRM_PLANE_HELPER_NO_SCALING, 63 true, true); 64 } 65 66 /* Takes a fixed 16.16 number and converts it to integer. */ 67 static inline int64_t fixed16_to_int(int64_t value) 68 { 69 return value >> 16; 70 } 71 72 static void meson_plane_atomic_update(struct drm_plane *plane, 73 struct drm_plane_state *old_state) 74 { 75 struct meson_plane *meson_plane = to_meson_plane(plane); 76 struct drm_plane_state *state = plane->state; 77 struct drm_framebuffer *fb = state->fb; 78 struct meson_drm *priv = meson_plane->priv; 79 struct drm_gem_cma_object *gem; 80 struct drm_rect src = { 81 .x1 = (state->src_x), 82 .y1 = (state->src_y), 83 .x2 = (state->src_x + state->src_w), 84 .y2 = (state->src_y + state->src_h), 85 }; 86 struct drm_rect dest = { 87 .x1 = state->crtc_x, 88 .y1 = state->crtc_y, 89 .x2 = state->crtc_x + state->crtc_w, 90 .y2 = state->crtc_y + state->crtc_h, 91 }; 92 unsigned long flags; 93 94 /* 95 * Update Coordinates 96 * Update Formats 97 * Update Buffer 98 * Enable Plane 99 */ 100 spin_lock_irqsave(&priv->drm->event_lock, flags); 101 102 /* Enable OSD and BLK0, set max global alpha */ 103 priv->viu.osd1_ctrl_stat = OSD_ENABLE | 104 (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | 105 OSD_BLK0_ENABLE; 106 107 /* Set up BLK0 to point to the right canvas */ 108 priv->viu.osd1_blk0_cfg[0] = ((MESON_CANVAS_ID_OSD1 << OSD_CANVAS_SEL) | 109 OSD_ENDIANNESS_LE); 110 111 /* On GXBB, Use the old non-HDR RGB2YUV converter */ 112 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) 113 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; 114 115 switch (fb->format->format) { 116 case DRM_FORMAT_XRGB8888: 117 /* For XRGB, replace the pixel's alpha by 0xFF */ 118 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, 119 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); 120 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | 121 OSD_COLOR_MATRIX_32_ARGB; 122 break; 123 case DRM_FORMAT_ARGB8888: 124 /* For ARGB, use the pixel's alpha */ 125 writel_bits_relaxed(OSD_REPLACE_EN, 0, 126 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); 127 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | 128 OSD_COLOR_MATRIX_32_ARGB; 129 break; 130 case DRM_FORMAT_RGB888: 131 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 | 132 OSD_COLOR_MATRIX_24_RGB; 133 break; 134 case DRM_FORMAT_RGB565: 135 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 | 136 OSD_COLOR_MATRIX_16_RGB565; 137 break; 138 }; 139 140 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) { 141 priv->viu.osd1_interlace = true; 142 143 dest.y1 /= 2; 144 dest.y2 /= 2; 145 } else 146 priv->viu.osd1_interlace = false; 147 148 /* 149 * The format of these registers is (x2 << 16 | x1), 150 * where x2 is exclusive. 151 * e.g. +30x1920 would be (1919 << 16) | 30 152 */ 153 priv->viu.osd1_blk0_cfg[1] = ((fixed16_to_int(src.x2) - 1) << 16) | 154 fixed16_to_int(src.x1); 155 priv->viu.osd1_blk0_cfg[2] = ((fixed16_to_int(src.y2) - 1) << 16) | 156 fixed16_to_int(src.y1); 157 priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1; 158 priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1; 159 160 /* Update Canvas with buffer address */ 161 gem = drm_fb_cma_get_gem_obj(fb, 0); 162 163 priv->viu.osd1_addr = gem->paddr; 164 priv->viu.osd1_stride = fb->pitches[0]; 165 priv->viu.osd1_height = fb->height; 166 167 spin_unlock_irqrestore(&priv->drm->event_lock, flags); 168 } 169 170 static void meson_plane_atomic_disable(struct drm_plane *plane, 171 struct drm_plane_state *old_state) 172 { 173 struct meson_plane *meson_plane = to_meson_plane(plane); 174 struct meson_drm *priv = meson_plane->priv; 175 176 /* Disable OSD1 */ 177 writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, 178 priv->io_base + _REG(VPP_MISC)); 179 180 } 181 182 static const struct drm_plane_helper_funcs meson_plane_helper_funcs = { 183 .atomic_check = meson_plane_atomic_check, 184 .atomic_disable = meson_plane_atomic_disable, 185 .atomic_update = meson_plane_atomic_update, 186 }; 187 188 static const struct drm_plane_funcs meson_plane_funcs = { 189 .update_plane = drm_atomic_helper_update_plane, 190 .disable_plane = drm_atomic_helper_disable_plane, 191 .destroy = drm_plane_cleanup, 192 .reset = drm_atomic_helper_plane_reset, 193 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 194 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 195 }; 196 197 static const uint32_t supported_drm_formats[] = { 198 DRM_FORMAT_ARGB8888, 199 DRM_FORMAT_XRGB8888, 200 DRM_FORMAT_RGB888, 201 DRM_FORMAT_RGB565, 202 }; 203 204 int meson_plane_create(struct meson_drm *priv) 205 { 206 struct meson_plane *meson_plane; 207 struct drm_plane *plane; 208 209 meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), 210 GFP_KERNEL); 211 if (!meson_plane) 212 return -ENOMEM; 213 214 meson_plane->priv = priv; 215 plane = &meson_plane->base; 216 217 drm_universal_plane_init(priv->drm, plane, 0xFF, 218 &meson_plane_funcs, 219 supported_drm_formats, 220 ARRAY_SIZE(supported_drm_formats), 221 NULL, 222 DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); 223 224 drm_plane_helper_add(plane, &meson_plane_helper_funcs); 225 226 priv->primary_plane = plane; 227 228 return 0; 229 } 230