1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * Copyright (C) 2014 Endless Mobile 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of the 10 * License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Written by: 21 * Jasper St. Pierre <jstpierre@mecheye.net> 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/bitfield.h> 28 #include <linux/platform_device.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_plane_helper.h> 33 #include <drm/drm_gem_cma_helper.h> 34 #include <drm/drm_fb_cma_helper.h> 35 #include <drm/drm_gem_framebuffer_helper.h> 36 #include <drm/drm_rect.h> 37 38 #include "meson_plane.h" 39 #include "meson_vpp.h" 40 #include "meson_viu.h" 41 #include "meson_registers.h" 42 43 /* OSD_SCI_WH_M1 */ 44 #define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w) 45 #define SCI_WH_M1_H(h) FIELD_PREP(GENMASK(12, 0), h) 46 47 /* OSD_SCO_H_START_END */ 48 /* OSD_SCO_V_START_END */ 49 #define SCO_HV_START(start) FIELD_PREP(GENMASK(27, 16), start) 50 #define SCO_HV_END(end) FIELD_PREP(GENMASK(11, 0), end) 51 52 /* OSD_SC_CTRL0 */ 53 #define SC_CTRL0_PATH_EN BIT(3) 54 #define SC_CTRL0_SEL_OSD1 BIT(2) 55 56 /* OSD_VSC_CTRL0 */ 57 #define VSC_BANK_LEN(value) FIELD_PREP(GENMASK(2, 0), value) 58 #define VSC_TOP_INI_RCV_NUM(value) FIELD_PREP(GENMASK(6, 3), value) 59 #define VSC_TOP_RPT_L0_NUM(value) FIELD_PREP(GENMASK(9, 8), value) 60 #define VSC_BOT_INI_RCV_NUM(value) FIELD_PREP(GENMASK(14, 11), value) 61 #define VSC_BOT_RPT_L0_NUM(value) FIELD_PREP(GENMASK(17, 16), value) 62 #define VSC_PROG_INTERLACE BIT(23) 63 #define VSC_VERTICAL_SCALER_EN BIT(24) 64 65 /* OSD_VSC_INI_PHASE */ 66 #define VSC_INI_PHASE_BOT(bottom) FIELD_PREP(GENMASK(31, 16), bottom) 67 #define VSC_INI_PHASE_TOP(top) FIELD_PREP(GENMASK(15, 0), top) 68 69 /* OSD_HSC_CTRL0 */ 70 #define HSC_BANK_LENGTH(value) FIELD_PREP(GENMASK(2, 0), value) 71 #define HSC_INI_RCV_NUM0(value) FIELD_PREP(GENMASK(6, 3), value) 72 #define HSC_RPT_P0_NUM0(value) FIELD_PREP(GENMASK(9, 8), value) 73 #define HSC_HORIZ_SCALER_EN BIT(22) 74 75 /* VPP_OSD_VSC_PHASE_STEP */ 76 /* VPP_OSD_HSC_PHASE_STEP */ 77 #define SC_PHASE_STEP(value) FIELD_PREP(GENMASK(27, 0), value) 78 79 struct meson_plane { 80 struct drm_plane base; 81 struct meson_drm *priv; 82 bool enabled; 83 }; 84 #define to_meson_plane(x) container_of(x, struct meson_plane, base) 85 86 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 87 88 static int meson_plane_atomic_check(struct drm_plane *plane, 89 struct drm_plane_state *state) 90 { 91 struct drm_crtc_state *crtc_state; 92 93 if (!state->crtc) 94 return 0; 95 96 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 97 if (IS_ERR(crtc_state)) 98 return PTR_ERR(crtc_state); 99 100 /* 101 * Only allow : 102 * - Upscaling up to 5x, vertical and horizontal 103 * - Final coordinates must match crtc size 104 */ 105 return drm_atomic_helper_check_plane_state(state, crtc_state, 106 FRAC_16_16(1, 5), 107 DRM_PLANE_HELPER_NO_SCALING, 108 false, true); 109 } 110 111 /* Takes a fixed 16.16 number and converts it to integer. */ 112 static inline int64_t fixed16_to_int(int64_t value) 113 { 114 return value >> 16; 115 } 116 117 static void meson_plane_atomic_update(struct drm_plane *plane, 118 struct drm_plane_state *old_state) 119 { 120 struct meson_plane *meson_plane = to_meson_plane(plane); 121 struct drm_plane_state *state = plane->state; 122 struct drm_rect dest = drm_plane_state_dest(state); 123 struct meson_drm *priv = meson_plane->priv; 124 struct drm_framebuffer *fb = state->fb; 125 struct drm_gem_cma_object *gem; 126 unsigned long flags; 127 int vsc_ini_rcv_num, vsc_ini_rpt_p0_num; 128 int vsc_bot_rcv_num, vsc_bot_rpt_p0_num; 129 int hsc_ini_rcv_num, hsc_ini_rpt_p0_num; 130 int hf_phase_step, vf_phase_step; 131 int src_w, src_h, dst_w, dst_h; 132 int bot_ini_phase; 133 int hf_bank_len; 134 int vf_bank_len; 135 u8 canvas_id_osd1; 136 137 /* 138 * Update Coordinates 139 * Update Formats 140 * Update Buffer 141 * Enable Plane 142 */ 143 spin_lock_irqsave(&priv->drm->event_lock, flags); 144 145 /* Enable OSD and BLK0, set max global alpha */ 146 priv->viu.osd1_ctrl_stat = OSD_ENABLE | 147 (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | 148 OSD_BLK0_ENABLE; 149 150 canvas_id_osd1 = priv->canvas_id_osd1; 151 152 /* Set up BLK0 to point to the right canvas */ 153 priv->viu.osd1_blk0_cfg[0] = ((canvas_id_osd1 << OSD_CANVAS_SEL) | 154 OSD_ENDIANNESS_LE); 155 156 /* On GXBB, Use the old non-HDR RGB2YUV converter */ 157 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) 158 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; 159 160 switch (fb->format->format) { 161 case DRM_FORMAT_XRGB8888: 162 /* For XRGB, replace the pixel's alpha by 0xFF */ 163 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, 164 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); 165 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | 166 OSD_COLOR_MATRIX_32_ARGB; 167 break; 168 case DRM_FORMAT_ARGB8888: 169 /* For ARGB, use the pixel's alpha */ 170 writel_bits_relaxed(OSD_REPLACE_EN, 0, 171 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); 172 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | 173 OSD_COLOR_MATRIX_32_ARGB; 174 break; 175 case DRM_FORMAT_RGB888: 176 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 | 177 OSD_COLOR_MATRIX_24_RGB; 178 break; 179 case DRM_FORMAT_RGB565: 180 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 | 181 OSD_COLOR_MATRIX_16_RGB565; 182 break; 183 }; 184 185 /* Default scaler parameters */ 186 vsc_bot_rcv_num = 0; 187 vsc_bot_rpt_p0_num = 0; 188 hf_bank_len = 4; 189 vf_bank_len = 4; 190 191 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) { 192 vsc_bot_rcv_num = 6; 193 vsc_bot_rpt_p0_num = 2; 194 } 195 196 hsc_ini_rcv_num = hf_bank_len; 197 vsc_ini_rcv_num = vf_bank_len; 198 hsc_ini_rpt_p0_num = (hf_bank_len / 2) - 1; 199 vsc_ini_rpt_p0_num = (vf_bank_len / 2) - 1; 200 201 src_w = fixed16_to_int(state->src_w); 202 src_h = fixed16_to_int(state->src_h); 203 dst_w = state->crtc_w; 204 dst_h = state->crtc_h; 205 206 /* 207 * When the output is interlaced, the OSD must switch between 208 * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0 209 * at each vsync. 210 * But the vertical scaler can provide such funtionnality if 211 * is configured for 2:1 scaling with interlace options enabled. 212 */ 213 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) { 214 dest.y1 /= 2; 215 dest.y2 /= 2; 216 dst_h /= 2; 217 } 218 219 hf_phase_step = ((src_w << 18) / dst_w) << 6; 220 vf_phase_step = (src_h << 20) / dst_h; 221 222 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 223 bot_ini_phase = ((vf_phase_step / 2) >> 4); 224 else 225 bot_ini_phase = 0; 226 227 vf_phase_step = (vf_phase_step << 4); 228 229 /* In interlaced mode, scaler is always active */ 230 if (src_h != dst_h || src_w != dst_w) { 231 priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) | 232 SCI_WH_M1_H(src_h - 1); 233 priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) | 234 SCO_HV_END(dest.x2 - 1); 235 priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) | 236 SCO_HV_END(dest.y2 - 1); 237 /* Enable OSD Scaler */ 238 priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1; 239 } else { 240 priv->viu.osd_sc_i_wh_m1 = 0; 241 priv->viu.osd_sc_o_h_start_end = 0; 242 priv->viu.osd_sc_o_v_start_end = 0; 243 priv->viu.osd_sc_ctrl0 = 0; 244 } 245 246 /* In interlaced mode, vertical scaler is always active */ 247 if (src_h != dst_h) { 248 priv->viu.osd_sc_v_ctrl0 = 249 VSC_BANK_LEN(vf_bank_len) | 250 VSC_TOP_INI_RCV_NUM(vsc_ini_rcv_num) | 251 VSC_TOP_RPT_L0_NUM(vsc_ini_rpt_p0_num) | 252 VSC_VERTICAL_SCALER_EN; 253 254 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 255 priv->viu.osd_sc_v_ctrl0 |= 256 VSC_BOT_INI_RCV_NUM(vsc_bot_rcv_num) | 257 VSC_BOT_RPT_L0_NUM(vsc_bot_rpt_p0_num) | 258 VSC_PROG_INTERLACE; 259 260 priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step); 261 priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase); 262 } else { 263 priv->viu.osd_sc_v_ctrl0 = 0; 264 priv->viu.osd_sc_v_phase_step = 0; 265 priv->viu.osd_sc_v_ini_phase = 0; 266 } 267 268 /* Horizontal scaler is only used if width does not match */ 269 if (src_w != dst_w) { 270 priv->viu.osd_sc_h_ctrl0 = 271 HSC_BANK_LENGTH(hf_bank_len) | 272 HSC_INI_RCV_NUM0(hsc_ini_rcv_num) | 273 HSC_RPT_P0_NUM0(hsc_ini_rpt_p0_num) | 274 HSC_HORIZ_SCALER_EN; 275 priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step); 276 priv->viu.osd_sc_h_ini_phase = 0; 277 } else { 278 priv->viu.osd_sc_h_ctrl0 = 0; 279 priv->viu.osd_sc_h_phase_step = 0; 280 priv->viu.osd_sc_h_ini_phase = 0; 281 } 282 283 /* 284 * The format of these registers is (x2 << 16 | x1), 285 * where x2 is exclusive. 286 * e.g. +30x1920 would be (1919 << 16) | 30 287 */ 288 priv->viu.osd1_blk0_cfg[1] = 289 ((fixed16_to_int(state->src.x2) - 1) << 16) | 290 fixed16_to_int(state->src.x1); 291 priv->viu.osd1_blk0_cfg[2] = 292 ((fixed16_to_int(state->src.y2) - 1) << 16) | 293 fixed16_to_int(state->src.y1); 294 priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1; 295 priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1; 296 297 if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 298 priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1; 299 priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1; 300 priv->viu.osb_blend0_size = dst_h << 16 | dst_w; 301 priv->viu.osb_blend1_size = dst_h << 16 | dst_w; 302 } 303 304 /* Update Canvas with buffer address */ 305 gem = drm_fb_cma_get_gem_obj(fb, 0); 306 307 priv->viu.osd1_addr = gem->paddr; 308 priv->viu.osd1_stride = fb->pitches[0]; 309 priv->viu.osd1_height = fb->height; 310 311 if (!meson_plane->enabled) { 312 /* Reset OSD1 before enabling it on GXL+ SoCs */ 313 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 314 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) 315 meson_viu_osd1_reset(priv); 316 317 meson_plane->enabled = true; 318 } 319 320 spin_unlock_irqrestore(&priv->drm->event_lock, flags); 321 } 322 323 static void meson_plane_atomic_disable(struct drm_plane *plane, 324 struct drm_plane_state *old_state) 325 { 326 struct meson_plane *meson_plane = to_meson_plane(plane); 327 struct meson_drm *priv = meson_plane->priv; 328 329 /* Disable OSD1 */ 330 if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 331 writel_bits_relaxed(BIT(0) | BIT(21), 0, 332 priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); 333 else 334 writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, 335 priv->io_base + _REG(VPP_MISC)); 336 337 meson_plane->enabled = false; 338 339 } 340 341 static const struct drm_plane_helper_funcs meson_plane_helper_funcs = { 342 .atomic_check = meson_plane_atomic_check, 343 .atomic_disable = meson_plane_atomic_disable, 344 .atomic_update = meson_plane_atomic_update, 345 .prepare_fb = drm_gem_fb_prepare_fb, 346 }; 347 348 static const struct drm_plane_funcs meson_plane_funcs = { 349 .update_plane = drm_atomic_helper_update_plane, 350 .disable_plane = drm_atomic_helper_disable_plane, 351 .destroy = drm_plane_cleanup, 352 .reset = drm_atomic_helper_plane_reset, 353 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 354 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 355 }; 356 357 static const uint32_t supported_drm_formats[] = { 358 DRM_FORMAT_ARGB8888, 359 DRM_FORMAT_XRGB8888, 360 DRM_FORMAT_RGB888, 361 DRM_FORMAT_RGB565, 362 }; 363 364 int meson_plane_create(struct meson_drm *priv) 365 { 366 struct meson_plane *meson_plane; 367 struct drm_plane *plane; 368 369 meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), 370 GFP_KERNEL); 371 if (!meson_plane) 372 return -ENOMEM; 373 374 meson_plane->priv = priv; 375 plane = &meson_plane->base; 376 377 drm_universal_plane_init(priv->drm, plane, 0xFF, 378 &meson_plane_funcs, 379 supported_drm_formats, 380 ARRAY_SIZE(supported_drm_formats), 381 NULL, 382 DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); 383 384 drm_plane_helper_add(plane, &meson_plane_helper_funcs); 385 386 priv->primary_plane = plane; 387 388 return 0; 389 } 390