1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 6 */ 7 8 #include <linux/bitfield.h> 9 10 #include <drm/drm_atomic.h> 11 #include <drm/drm_atomic_helper.h> 12 #include <drm/drm_device.h> 13 #include <drm/drm_fourcc.h> 14 #include <drm/drm_plane_helper.h> 15 #include <drm/drm_gem_cma_helper.h> 16 #include <drm/drm_fb_cma_helper.h> 17 #include <drm/drm_gem_framebuffer_helper.h> 18 19 #include "meson_overlay.h" 20 #include "meson_registers.h" 21 #include "meson_viu.h" 22 #include "meson_vpp.h" 23 24 /* VD1_IF0_GEN_REG */ 25 #define VD_URGENT_CHROMA BIT(28) 26 #define VD_URGENT_LUMA BIT(27) 27 #define VD_HOLD_LINES(lines) FIELD_PREP(GENMASK(24, 19), lines) 28 #define VD_DEMUX_MODE_RGB BIT(16) 29 #define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val) 30 #define VD_CHRO_RPT_LASTL_CTRL BIT(6) 31 #define VD_LITTLE_ENDIAN BIT(4) 32 #define VD_SEPARATE_EN BIT(1) 33 #define VD_ENABLE BIT(0) 34 35 /* VD1_IF0_CANVAS0 */ 36 #define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr) 37 #define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr) 38 #define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr) 39 40 /* VD1_IF0_LUMA_X0 VD1_IF0_CHROMA_X0 */ 41 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value) 42 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value) 43 44 /* VD1_IF0_LUMA_Y0 VD1_IF0_CHROMA_Y0 */ 45 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value) 46 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value) 47 48 /* VD1_IF0_GEN_REG2 */ 49 #define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value) 50 51 /* VIU_VD1_FMT_CTRL */ 52 #define VD_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value) 53 #define VD_HORZ_FMT_EN BIT(20) 54 #define VD_VERT_RPT_LINE0 BIT(16) 55 #define VD_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value) 56 #define VD_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value) 57 #define VD_VERT_FMT_EN BIT(0) 58 59 /* VPP_POSTBLEND_VD1_H_START_END */ 60 #define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value) 61 #define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), \ 62 ((value) & GENMASK(13, 0))) 63 64 /* VPP_POSTBLEND_VD1_V_START_END */ 65 #define VD_V_END(value) FIELD_PREP(GENMASK(11, 0), value) 66 #define VD_V_START(value) FIELD_PREP(GENMASK(27, 16), value) 67 68 /* VPP_BLEND_VD2_V_START_END */ 69 #define VD2_V_END(value) FIELD_PREP(GENMASK(11, 0), value) 70 #define VD2_V_START(value) FIELD_PREP(GENMASK(27, 16), value) 71 72 /* VIU_VD1_FMT_W */ 73 #define VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value) 74 #define VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value) 75 76 /* VPP_HSC_REGION12_STARTP VPP_HSC_REGION34_STARTP */ 77 #define VD_REGION24_START(value) FIELD_PREP(GENMASK(11, 0), value) 78 #define VD_REGION13_END(value) FIELD_PREP(GENMASK(27, 16), value) 79 80 /* AFBC_ENABLE */ 81 #define AFBC_DEC_ENABLE BIT(8) 82 #define AFBC_FRM_START BIT(0) 83 84 /* AFBC_MODE */ 85 #define AFBC_HORZ_SKIP_UV(value) FIELD_PREP(GENMASK(1, 0), value) 86 #define AFBC_VERT_SKIP_UV(value) FIELD_PREP(GENMASK(3, 2), value) 87 #define AFBC_HORZ_SKIP_Y(value) FIELD_PREP(GENMASK(5, 4), value) 88 #define AFBC_VERT_SKIP_Y(value) FIELD_PREP(GENMASK(7, 6), value) 89 #define AFBC_COMPBITS_YUV(value) FIELD_PREP(GENMASK(13, 8), value) 90 #define AFBC_COMPBITS_8BIT 0 91 #define AFBC_COMPBITS_10BIT (2 | (2 << 2) | (2 << 4)) 92 #define AFBC_BURST_LEN(value) FIELD_PREP(GENMASK(15, 14), value) 93 #define AFBC_HOLD_LINE_NUM(value) FIELD_PREP(GENMASK(22, 16), value) 94 #define AFBC_MIF_URGENT(value) FIELD_PREP(GENMASK(25, 24), value) 95 #define AFBC_REV_MODE(value) FIELD_PREP(GENMASK(27, 26), value) 96 #define AFBC_BLK_MEM_MODE BIT(28) 97 #define AFBC_SCATTER_MODE BIT(29) 98 #define AFBC_SOFT_RESET BIT(31) 99 100 /* AFBC_SIZE_IN */ 101 #define AFBC_HSIZE_IN(value) FIELD_PREP(GENMASK(28, 16), value) 102 #define AFBC_VSIZE_IN(value) FIELD_PREP(GENMASK(12, 0), value) 103 104 /* AFBC_DEC_DEF_COLOR */ 105 #define AFBC_DEF_COLOR_Y(value) FIELD_PREP(GENMASK(29, 20), value) 106 #define AFBC_DEF_COLOR_U(value) FIELD_PREP(GENMASK(19, 10), value) 107 #define AFBC_DEF_COLOR_V(value) FIELD_PREP(GENMASK(9, 0), value) 108 109 /* AFBC_CONV_CTRL */ 110 #define AFBC_CONV_LBUF_LEN(value) FIELD_PREP(GENMASK(11, 0), value) 111 112 /* AFBC_LBUF_DEPTH */ 113 #define AFBC_DEC_LBUF_DEPTH(value) FIELD_PREP(GENMASK(27, 16), value) 114 #define AFBC_MIF_LBUF_DEPTH(value) FIELD_PREP(GENMASK(11, 0), value) 115 116 /* AFBC_OUT_XSCOPE/AFBC_SIZE_OUT */ 117 #define AFBC_HSIZE_OUT(value) FIELD_PREP(GENMASK(28, 16), value) 118 #define AFBC_VSIZE_OUT(value) FIELD_PREP(GENMASK(12, 0), value) 119 #define AFBC_OUT_HORZ_BGN(value) FIELD_PREP(GENMASK(28, 16), value) 120 #define AFBC_OUT_HORZ_END(value) FIELD_PREP(GENMASK(12, 0), value) 121 122 /* AFBC_OUT_YSCOPE */ 123 #define AFBC_OUT_VERT_BGN(value) FIELD_PREP(GENMASK(28, 16), value) 124 #define AFBC_OUT_VERT_END(value) FIELD_PREP(GENMASK(12, 0), value) 125 126 /* AFBC_VD_CFMT_CTRL */ 127 #define AFBC_HORZ_RPT_PIXEL0 BIT(23) 128 #define AFBC_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value) 129 #define AFBC_HORZ_FMT_EN BIT(20) 130 #define AFBC_VERT_RPT_LINE0 BIT(16) 131 #define AFBC_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value) 132 #define AFBC_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value) 133 #define AFBC_VERT_FMT_EN BIT(0) 134 135 /* AFBC_VD_CFMT_W */ 136 #define AFBC_VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value) 137 #define AFBC_VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value) 138 139 /* AFBC_MIF_HOR_SCOPE */ 140 #define AFBC_MIF_BLK_BGN_H(value) FIELD_PREP(GENMASK(25, 16), value) 141 #define AFBC_MIF_BLK_END_H(value) FIELD_PREP(GENMASK(9, 0), value) 142 143 /* AFBC_MIF_VER_SCOPE */ 144 #define AFBC_MIF_BLK_BGN_V(value) FIELD_PREP(GENMASK(27, 16), value) 145 #define AFBC_MIF_BLK_END_V(value) FIELD_PREP(GENMASK(11, 0), value) 146 147 /* AFBC_PIXEL_HOR_SCOPE */ 148 #define AFBC_DEC_PIXEL_BGN_H(value) FIELD_PREP(GENMASK(28, 16), \ 149 ((value) & GENMASK(12, 0))) 150 #define AFBC_DEC_PIXEL_END_H(value) FIELD_PREP(GENMASK(12, 0), value) 151 152 /* AFBC_PIXEL_VER_SCOPE */ 153 #define AFBC_DEC_PIXEL_BGN_V(value) FIELD_PREP(GENMASK(28, 16), value) 154 #define AFBC_DEC_PIXEL_END_V(value) FIELD_PREP(GENMASK(12, 0), value) 155 156 /* AFBC_VD_CFMT_H */ 157 #define AFBC_VD_HEIGHT(value) FIELD_PREP(GENMASK(12, 0), value) 158 159 struct meson_overlay { 160 struct drm_plane base; 161 struct meson_drm *priv; 162 }; 163 #define to_meson_overlay(x) container_of(x, struct meson_overlay, base) 164 165 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 166 167 static int meson_overlay_atomic_check(struct drm_plane *plane, 168 struct drm_plane_state *state) 169 { 170 struct drm_crtc_state *crtc_state; 171 172 if (!state->crtc) 173 return 0; 174 175 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 176 if (IS_ERR(crtc_state)) 177 return PTR_ERR(crtc_state); 178 179 return drm_atomic_helper_check_plane_state(state, crtc_state, 180 FRAC_16_16(1, 5), 181 FRAC_16_16(5, 1), 182 true, true); 183 } 184 185 /* Takes a fixed 16.16 number and converts it to integer. */ 186 static inline int64_t fixed16_to_int(int64_t value) 187 { 188 return value >> 16; 189 } 190 191 static const uint8_t skip_tab[6] = { 192 0x24, 0x04, 0x68, 0x48, 0x28, 0x08, 193 }; 194 195 static void meson_overlay_get_vertical_phase(unsigned int ratio_y, int *phase, 196 int *repeat, bool interlace) 197 { 198 int offset_in = 0; 199 int offset_out = 0; 200 int repeat_skip = 0; 201 202 if (!interlace && ratio_y > (1 << 18)) 203 offset_out = (1 * ratio_y) >> 10; 204 205 while ((offset_in + (4 << 8)) <= offset_out) { 206 repeat_skip++; 207 offset_in += 4 << 8; 208 } 209 210 *phase = (offset_out - offset_in) >> 2; 211 212 if (*phase > 0x100) 213 repeat_skip++; 214 215 *phase = *phase & 0xff; 216 217 if (repeat_skip > 5) 218 repeat_skip = 5; 219 220 *repeat = skip_tab[repeat_skip]; 221 } 222 223 static void meson_overlay_setup_scaler_params(struct meson_drm *priv, 224 struct drm_plane *plane, 225 bool interlace_mode) 226 { 227 struct drm_crtc_state *crtc_state = priv->crtc->state; 228 int video_top, video_left, video_width, video_height; 229 struct drm_plane_state *state = plane->state; 230 unsigned int vd_start_lines, vd_end_lines; 231 unsigned int hd_start_lines, hd_end_lines; 232 unsigned int crtc_height, crtc_width; 233 unsigned int vsc_startp, vsc_endp; 234 unsigned int hsc_startp, hsc_endp; 235 unsigned int crop_top, crop_left; 236 int vphase, vphase_repeat_skip; 237 unsigned int ratio_x, ratio_y; 238 int temp_height, temp_width; 239 unsigned int w_in, h_in; 240 int afbc_left, afbc_right; 241 int afbc_top_src, afbc_bottom_src; 242 int afbc_top, afbc_bottom; 243 int temp, start, end; 244 245 if (!crtc_state) { 246 DRM_ERROR("Invalid crtc_state\n"); 247 return; 248 } 249 250 crtc_height = crtc_state->mode.vdisplay; 251 crtc_width = crtc_state->mode.hdisplay; 252 253 w_in = fixed16_to_int(state->src_w); 254 h_in = fixed16_to_int(state->src_h); 255 crop_top = fixed16_to_int(state->src_y); 256 crop_left = fixed16_to_int(state->src_x); 257 258 video_top = state->crtc_y; 259 video_left = state->crtc_x; 260 video_width = state->crtc_w; 261 video_height = state->crtc_h; 262 263 DRM_DEBUG("crtc_width %d crtc_height %d interlace %d\n", 264 crtc_width, crtc_height, interlace_mode); 265 DRM_DEBUG("w_in %d h_in %d crop_top %d crop_left %d\n", 266 w_in, h_in, crop_top, crop_left); 267 DRM_DEBUG("video top %d left %d width %d height %d\n", 268 video_top, video_left, video_width, video_height); 269 270 ratio_x = (w_in << 18) / video_width; 271 ratio_y = (h_in << 18) / video_height; 272 273 if (ratio_x * video_width < (w_in << 18)) 274 ratio_x++; 275 276 DRM_DEBUG("ratio x 0x%x y 0x%x\n", ratio_x, ratio_y); 277 278 meson_overlay_get_vertical_phase(ratio_y, &vphase, &vphase_repeat_skip, 279 interlace_mode); 280 281 DRM_DEBUG("vphase 0x%x skip %d\n", vphase, vphase_repeat_skip); 282 283 /* Vertical */ 284 285 start = video_top + video_height / 2 - ((h_in << 17) / ratio_y); 286 end = (h_in << 18) / ratio_y + start - 1; 287 288 if (video_top < 0 && start < 0) 289 vd_start_lines = (-(start) * ratio_y) >> 18; 290 else if (start < video_top) 291 vd_start_lines = ((video_top - start) * ratio_y) >> 18; 292 else 293 vd_start_lines = 0; 294 295 if (video_top < 0) 296 temp_height = min_t(unsigned int, 297 video_top + video_height - 1, 298 crtc_height - 1); 299 else 300 temp_height = min_t(unsigned int, 301 video_top + video_height - 1, 302 crtc_height - 1) - video_top + 1; 303 304 temp = vd_start_lines + (temp_height * ratio_y >> 18); 305 vd_end_lines = (temp <= (h_in - 1)) ? temp : (h_in - 1); 306 307 vd_start_lines += crop_left; 308 vd_end_lines += crop_left; 309 310 /* 311 * TOFIX: Input frames are handled and scaled like progressive frames, 312 * proper handling of interlaced field input frames need to be figured 313 * out using the proper framebuffer flags set by userspace. 314 */ 315 if (interlace_mode) { 316 start >>= 1; 317 end >>= 1; 318 } 319 320 vsc_startp = max_t(int, start, 321 max_t(int, 0, video_top)); 322 vsc_endp = min_t(int, end, 323 min_t(int, crtc_height - 1, 324 video_top + video_height - 1)); 325 326 DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n", 327 vsc_startp, vsc_endp, vd_start_lines, vd_end_lines); 328 329 afbc_top = round_down(vd_start_lines, 4); 330 afbc_bottom = round_up(vd_end_lines + 1, 4); 331 afbc_top_src = 0; 332 afbc_bottom_src = round_up(h_in + 1, 4); 333 334 DRM_DEBUG("afbc top %d (src %d) bottom %d (src %d)\n", 335 afbc_top, afbc_top_src, afbc_bottom, afbc_bottom_src); 336 337 /* Horizontal */ 338 339 start = video_left + video_width / 2 - ((w_in << 17) / ratio_x); 340 end = (w_in << 18) / ratio_x + start - 1; 341 342 if (video_left < 0 && start < 0) 343 hd_start_lines = (-(start) * ratio_x) >> 18; 344 else if (start < video_left) 345 hd_start_lines = ((video_left - start) * ratio_x) >> 18; 346 else 347 hd_start_lines = 0; 348 349 if (video_left < 0) 350 temp_width = min_t(unsigned int, 351 video_left + video_width - 1, 352 crtc_width - 1); 353 else 354 temp_width = min_t(unsigned int, 355 video_left + video_width - 1, 356 crtc_width - 1) - video_left + 1; 357 358 temp = hd_start_lines + (temp_width * ratio_x >> 18); 359 hd_end_lines = (temp <= (w_in - 1)) ? temp : (w_in - 1); 360 361 priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1; 362 hsc_startp = max_t(int, start, max_t(int, 0, video_left)); 363 hsc_endp = min_t(int, end, min_t(int, crtc_width - 1, 364 video_left + video_width - 1)); 365 366 hd_start_lines += crop_top; 367 hd_end_lines += crop_top; 368 369 DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n", 370 hsc_startp, hsc_endp, hd_start_lines, hd_end_lines); 371 372 if (hd_start_lines > 0 || (hd_end_lines < w_in)) { 373 afbc_left = 0; 374 afbc_right = round_up(w_in, 32); 375 } else { 376 afbc_left = round_down(hd_start_lines, 32); 377 afbc_right = round_up(hd_end_lines + 1, 32); 378 } 379 380 DRM_DEBUG("afbc left %d right %d\n", afbc_left, afbc_right); 381 382 priv->viu.vpp_vsc_start_phase_step = ratio_y << 6; 383 384 priv->viu.vpp_vsc_ini_phase = vphase << 8; 385 priv->viu.vpp_vsc_phase_ctrl = (1 << 13) | (4 << 8) | 386 vphase_repeat_skip; 387 388 priv->viu.vd1_if0_luma_x0 = VD_X_START(hd_start_lines) | 389 VD_X_END(hd_end_lines); 390 priv->viu.vd1_if0_chroma_x0 = VD_X_START(hd_start_lines >> 1) | 391 VD_X_END(hd_end_lines >> 1); 392 393 priv->viu.viu_vd1_fmt_w = 394 VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) | 395 VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1); 396 397 priv->viu.vd1_afbc_vd_cfmt_w = 398 AFBC_VD_H_WIDTH(afbc_right - afbc_left) | 399 AFBC_VD_V_WIDTH(afbc_right / 2 - afbc_left / 2); 400 401 priv->viu.vd1_afbc_vd_cfmt_h = 402 AFBC_VD_HEIGHT((afbc_bottom - afbc_top) / 2); 403 404 priv->viu.vd1_afbc_mif_hor_scope = AFBC_MIF_BLK_BGN_H(afbc_left / 32) | 405 AFBC_MIF_BLK_END_H((afbc_right / 32) - 1); 406 407 priv->viu.vd1_afbc_mif_ver_scope = AFBC_MIF_BLK_BGN_V(afbc_top / 4) | 408 AFBC_MIF_BLK_END_H((afbc_bottom / 4) - 1); 409 410 priv->viu.vd1_afbc_size_out = 411 AFBC_HSIZE_OUT(afbc_right - afbc_left) | 412 AFBC_VSIZE_OUT(afbc_bottom - afbc_top); 413 414 priv->viu.vd1_afbc_pixel_hor_scope = 415 AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) | 416 AFBC_DEC_PIXEL_END_H(hd_end_lines - afbc_left); 417 418 priv->viu.vd1_afbc_pixel_ver_scope = 419 AFBC_DEC_PIXEL_BGN_V(vd_start_lines - afbc_top) | 420 AFBC_DEC_PIXEL_END_V(vd_end_lines - afbc_top); 421 422 priv->viu.vd1_afbc_size_in = 423 AFBC_HSIZE_IN(afbc_right - afbc_left) | 424 AFBC_VSIZE_IN(afbc_bottom_src - afbc_top_src); 425 426 priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) | 427 VD_Y_END(vd_end_lines); 428 429 priv->viu.vd1_if0_chroma_y0 = VD_Y_START(vd_start_lines >> 1) | 430 VD_Y_END(vd_end_lines >> 1); 431 432 priv->viu.vpp_pic_in_height = h_in; 433 434 priv->viu.vpp_postblend_vd1_h_start_end = VD_H_START(hsc_startp) | 435 VD_H_END(hsc_endp); 436 priv->viu.vpp_blend_vd2_h_start_end = VD_H_START(hd_start_lines) | 437 VD_H_END(hd_end_lines); 438 priv->viu.vpp_hsc_region12_startp = VD_REGION13_END(0) | 439 VD_REGION24_START(hsc_startp); 440 priv->viu.vpp_hsc_region34_startp = 441 VD_REGION13_END(hsc_startp) | 442 VD_REGION24_START(hsc_endp - hsc_startp); 443 priv->viu.vpp_hsc_region4_endp = hsc_endp - hsc_startp; 444 priv->viu.vpp_hsc_start_phase_step = ratio_x << 6; 445 priv->viu.vpp_hsc_region1_phase_slope = 0; 446 priv->viu.vpp_hsc_region3_phase_slope = 0; 447 priv->viu.vpp_hsc_phase_ctrl = (1 << 21) | (4 << 16); 448 449 priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1; 450 priv->viu.vpp_preblend_h_size = hd_end_lines - hd_start_lines + 1; 451 452 priv->viu.vpp_postblend_vd1_v_start_end = VD_V_START(vsc_startp) | 453 VD_V_END(vsc_endp); 454 priv->viu.vpp_blend_vd2_v_start_end = 455 VD2_V_START((vd_end_lines + 1) >> 1) | 456 VD2_V_END(vd_end_lines); 457 458 priv->viu.vpp_vsc_region12_startp = 0; 459 priv->viu.vpp_vsc_region34_startp = 460 VD_REGION13_END(vsc_endp - vsc_startp) | 461 VD_REGION24_START(vsc_endp - vsc_startp); 462 priv->viu.vpp_vsc_region4_endp = vsc_endp - vsc_startp; 463 priv->viu.vpp_vsc_start_phase_step = ratio_y << 6; 464 } 465 466 static void meson_overlay_atomic_update(struct drm_plane *plane, 467 struct drm_plane_state *old_state) 468 { 469 struct meson_overlay *meson_overlay = to_meson_overlay(plane); 470 struct drm_plane_state *state = plane->state; 471 struct drm_framebuffer *fb = state->fb; 472 struct meson_drm *priv = meson_overlay->priv; 473 struct drm_gem_cma_object *gem; 474 unsigned long flags; 475 bool interlace_mode; 476 477 DRM_DEBUG_DRIVER("\n"); 478 479 interlace_mode = state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE; 480 481 spin_lock_irqsave(&priv->drm->event_lock, flags); 482 483 if ((fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) == 484 DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) { 485 priv->viu.vd1_afbc = true; 486 487 priv->viu.vd1_afbc_mode = AFBC_MIF_URGENT(3) | 488 AFBC_HOLD_LINE_NUM(8) | 489 AFBC_BURST_LEN(2); 490 491 if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 492 AMLOGIC_FBC_OPTION_MEM_SAVING)) 493 priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE; 494 495 if ((fb->modifier & __fourcc_mod_amlogic_layout_mask) == 496 AMLOGIC_FBC_LAYOUT_SCATTER) 497 priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE; 498 499 priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE; 500 501 priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256); 502 503 priv->viu.vd1_afbc_dec_def_color = AFBC_DEF_COLOR_Y(1023); 504 505 /* 420: horizontal / 2, vertical / 4 */ 506 priv->viu.vd1_afbc_vd_cfmt_ctrl = AFBC_HORZ_RPT_PIXEL0 | 507 AFBC_HORZ_Y_C_RATIO(1) | 508 AFBC_HORZ_FMT_EN | 509 AFBC_VERT_RPT_LINE0 | 510 AFBC_VERT_INITIAL_PHASE(12) | 511 AFBC_VERT_PHASE_STEP(8) | 512 AFBC_VERT_FMT_EN; 513 514 switch (fb->format->format) { 515 /* AFBC Only formats */ 516 case DRM_FORMAT_YUV420_10BIT: 517 priv->viu.vd1_afbc_mode |= 518 AFBC_COMPBITS_YUV(AFBC_COMPBITS_10BIT); 519 priv->viu.vd1_afbc_dec_def_color |= 520 AFBC_DEF_COLOR_U(512) | 521 AFBC_DEF_COLOR_V(512); 522 break; 523 case DRM_FORMAT_YUV420_8BIT: 524 priv->viu.vd1_afbc_dec_def_color |= 525 AFBC_DEF_COLOR_U(128) | 526 AFBC_DEF_COLOR_V(128); 527 break; 528 } 529 530 priv->viu.vd1_if0_gen_reg = 0; 531 priv->viu.vd1_if0_canvas0 = 0; 532 priv->viu.viu_vd1_fmt_ctrl = 0; 533 } else { 534 priv->viu.vd1_afbc = false; 535 536 priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA | 537 VD_URGENT_LUMA | 538 VD_HOLD_LINES(9) | 539 VD_CHRO_RPT_LASTL_CTRL | 540 VD_ENABLE; 541 } 542 543 /* Setup scaler params */ 544 meson_overlay_setup_scaler_params(priv, plane, interlace_mode); 545 546 priv->viu.vd1_if0_repeat_loop = 0; 547 priv->viu.vd1_if0_luma0_rpt_pat = interlace_mode ? 8 : 0; 548 priv->viu.vd1_if0_chroma0_rpt_pat = interlace_mode ? 8 : 0; 549 priv->viu.vd1_range_map_y = 0; 550 priv->viu.vd1_range_map_cb = 0; 551 priv->viu.vd1_range_map_cr = 0; 552 553 /* Default values for RGB888/YUV444 */ 554 priv->viu.vd1_if0_gen_reg2 = 0; 555 priv->viu.viu_vd1_fmt_ctrl = 0; 556 557 /* None will match for AFBC Only formats */ 558 switch (fb->format->format) { 559 /* TOFIX DRM_FORMAT_RGB888 should be supported */ 560 case DRM_FORMAT_YUYV: 561 priv->viu.vd1_if0_gen_reg |= VD_BYTES_PER_PIXEL(1); 562 priv->viu.vd1_if0_canvas0 = 563 CANVAS_ADDR2(priv->canvas_id_vd1_0) | 564 CANVAS_ADDR1(priv->canvas_id_vd1_0) | 565 CANVAS_ADDR0(priv->canvas_id_vd1_0); 566 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */ 567 VD_HORZ_FMT_EN | 568 VD_VERT_RPT_LINE0 | 569 VD_VERT_INITIAL_PHASE(12) | 570 VD_VERT_PHASE_STEP(16) | /* /2 */ 571 VD_VERT_FMT_EN; 572 break; 573 case DRM_FORMAT_NV12: 574 case DRM_FORMAT_NV21: 575 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN; 576 priv->viu.vd1_if0_canvas0 = 577 CANVAS_ADDR2(priv->canvas_id_vd1_1) | 578 CANVAS_ADDR1(priv->canvas_id_vd1_1) | 579 CANVAS_ADDR0(priv->canvas_id_vd1_0); 580 if (fb->format->format == DRM_FORMAT_NV12) 581 priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(1); 582 else 583 priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(2); 584 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */ 585 VD_HORZ_FMT_EN | 586 VD_VERT_RPT_LINE0 | 587 VD_VERT_INITIAL_PHASE(12) | 588 VD_VERT_PHASE_STEP(8) | /* /4 */ 589 VD_VERT_FMT_EN; 590 break; 591 case DRM_FORMAT_YUV444: 592 case DRM_FORMAT_YUV422: 593 case DRM_FORMAT_YUV420: 594 case DRM_FORMAT_YUV411: 595 case DRM_FORMAT_YUV410: 596 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN; 597 priv->viu.vd1_if0_canvas0 = 598 CANVAS_ADDR2(priv->canvas_id_vd1_2) | 599 CANVAS_ADDR1(priv->canvas_id_vd1_1) | 600 CANVAS_ADDR0(priv->canvas_id_vd1_0); 601 switch (fb->format->format) { 602 case DRM_FORMAT_YUV422: 603 priv->viu.viu_vd1_fmt_ctrl = 604 VD_HORZ_Y_C_RATIO(1) | /* /2 */ 605 VD_HORZ_FMT_EN | 606 VD_VERT_RPT_LINE0 | 607 VD_VERT_INITIAL_PHASE(12) | 608 VD_VERT_PHASE_STEP(16) | /* /2 */ 609 VD_VERT_FMT_EN; 610 break; 611 case DRM_FORMAT_YUV420: 612 priv->viu.viu_vd1_fmt_ctrl = 613 VD_HORZ_Y_C_RATIO(1) | /* /2 */ 614 VD_HORZ_FMT_EN | 615 VD_VERT_RPT_LINE0 | 616 VD_VERT_INITIAL_PHASE(12) | 617 VD_VERT_PHASE_STEP(8) | /* /4 */ 618 VD_VERT_FMT_EN; 619 break; 620 case DRM_FORMAT_YUV411: 621 priv->viu.viu_vd1_fmt_ctrl = 622 VD_HORZ_Y_C_RATIO(2) | /* /4 */ 623 VD_HORZ_FMT_EN | 624 VD_VERT_RPT_LINE0 | 625 VD_VERT_INITIAL_PHASE(12) | 626 VD_VERT_PHASE_STEP(16) | /* /2 */ 627 VD_VERT_FMT_EN; 628 break; 629 case DRM_FORMAT_YUV410: 630 priv->viu.viu_vd1_fmt_ctrl = 631 VD_HORZ_Y_C_RATIO(2) | /* /4 */ 632 VD_HORZ_FMT_EN | 633 VD_VERT_RPT_LINE0 | 634 VD_VERT_INITIAL_PHASE(12) | 635 VD_VERT_PHASE_STEP(8) | /* /4 */ 636 VD_VERT_FMT_EN; 637 break; 638 } 639 break; 640 } 641 642 /* Update Canvas with buffer address */ 643 priv->viu.vd1_planes = fb->format->num_planes; 644 645 switch (priv->viu.vd1_planes) { 646 case 3: 647 gem = drm_fb_cma_get_gem_obj(fb, 2); 648 priv->viu.vd1_addr2 = gem->paddr + fb->offsets[2]; 649 priv->viu.vd1_stride2 = fb->pitches[2]; 650 priv->viu.vd1_height2 = 651 drm_format_info_plane_height(fb->format, 652 fb->height, 2); 653 DRM_DEBUG("plane 2 addr 0x%x stride %d height %d\n", 654 priv->viu.vd1_addr2, 655 priv->viu.vd1_stride2, 656 priv->viu.vd1_height2); 657 /* fallthrough */ 658 case 2: 659 gem = drm_fb_cma_get_gem_obj(fb, 1); 660 priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1]; 661 priv->viu.vd1_stride1 = fb->pitches[1]; 662 priv->viu.vd1_height1 = 663 drm_format_info_plane_height(fb->format, 664 fb->height, 1); 665 DRM_DEBUG("plane 1 addr 0x%x stride %d height %d\n", 666 priv->viu.vd1_addr1, 667 priv->viu.vd1_stride1, 668 priv->viu.vd1_height1); 669 /* fallthrough */ 670 case 1: 671 gem = drm_fb_cma_get_gem_obj(fb, 0); 672 priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0]; 673 priv->viu.vd1_stride0 = fb->pitches[0]; 674 priv->viu.vd1_height0 = 675 drm_format_info_plane_height(fb->format, 676 fb->height, 0); 677 DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n", 678 priv->viu.vd1_addr0, 679 priv->viu.vd1_stride0, 680 priv->viu.vd1_height0); 681 } 682 683 if (priv->viu.vd1_afbc) { 684 if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) { 685 /* 686 * In Scatter mode, the header contains the physical 687 * body content layout, thus the body content 688 * size isn't needed. 689 */ 690 priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4; 691 priv->viu.vd1_afbc_body_addr = 0; 692 } else { 693 /* Default mode is 4k per superblock */ 694 unsigned long block_size = 4096; 695 unsigned long body_size; 696 697 /* 8bit mem saving mode is 3072bytes per superblock */ 698 if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE) 699 block_size = 3072; 700 701 body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) * 702 (ALIGN(priv->viu.vd1_height0, 32) / 32) * 703 block_size; 704 705 priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4; 706 /* Header is after body content */ 707 priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 + 708 body_size) >> 4; 709 } 710 } 711 712 priv->viu.vd1_enabled = true; 713 714 spin_unlock_irqrestore(&priv->drm->event_lock, flags); 715 716 DRM_DEBUG_DRIVER("\n"); 717 } 718 719 static void meson_overlay_atomic_disable(struct drm_plane *plane, 720 struct drm_plane_state *old_state) 721 { 722 struct meson_overlay *meson_overlay = to_meson_overlay(plane); 723 struct meson_drm *priv = meson_overlay->priv; 724 725 DRM_DEBUG_DRIVER("\n"); 726 727 priv->viu.vd1_enabled = false; 728 729 /* Disable VD1 */ 730 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 731 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); 732 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); 733 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0)); 734 writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0)); 735 } else 736 writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, 737 priv->io_base + _REG(VPP_MISC)); 738 739 } 740 741 static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = { 742 .atomic_check = meson_overlay_atomic_check, 743 .atomic_disable = meson_overlay_atomic_disable, 744 .atomic_update = meson_overlay_atomic_update, 745 .prepare_fb = drm_gem_fb_prepare_fb, 746 }; 747 748 static bool meson_overlay_format_mod_supported(struct drm_plane *plane, 749 u32 format, u64 modifier) 750 { 751 if (modifier == DRM_FORMAT_MOD_LINEAR && 752 format != DRM_FORMAT_YUV420_8BIT && 753 format != DRM_FORMAT_YUV420_10BIT) 754 return true; 755 756 if ((modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) == 757 DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) { 758 unsigned int layout = modifier & 759 DRM_FORMAT_MOD_AMLOGIC_FBC( 760 __fourcc_mod_amlogic_layout_mask, 0); 761 unsigned int options = 762 (modifier >> __fourcc_mod_amlogic_options_shift) & 763 __fourcc_mod_amlogic_options_mask; 764 765 if (format != DRM_FORMAT_YUV420_8BIT && 766 format != DRM_FORMAT_YUV420_10BIT) { 767 DRM_DEBUG_KMS("%llx invalid format 0x%08x\n", 768 modifier, format); 769 return false; 770 } 771 772 if (layout != AMLOGIC_FBC_LAYOUT_BASIC && 773 layout != AMLOGIC_FBC_LAYOUT_SCATTER) { 774 DRM_DEBUG_KMS("%llx invalid layout %x\n", 775 modifier, layout); 776 return false; 777 } 778 779 if (options && 780 options != AMLOGIC_FBC_OPTION_MEM_SAVING) { 781 DRM_DEBUG_KMS("%llx invalid layout %x\n", 782 modifier, layout); 783 return false; 784 } 785 786 return true; 787 } 788 789 DRM_DEBUG_KMS("invalid modifier %llx for format 0x%08x\n", 790 modifier, format); 791 792 return false; 793 } 794 795 static const struct drm_plane_funcs meson_overlay_funcs = { 796 .update_plane = drm_atomic_helper_update_plane, 797 .disable_plane = drm_atomic_helper_disable_plane, 798 .destroy = drm_plane_cleanup, 799 .reset = drm_atomic_helper_plane_reset, 800 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 801 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 802 .format_mod_supported = meson_overlay_format_mod_supported, 803 }; 804 805 static const uint32_t supported_drm_formats[] = { 806 DRM_FORMAT_YUYV, 807 DRM_FORMAT_NV12, 808 DRM_FORMAT_NV21, 809 DRM_FORMAT_YUV444, 810 DRM_FORMAT_YUV422, 811 DRM_FORMAT_YUV420, 812 DRM_FORMAT_YUV411, 813 DRM_FORMAT_YUV410, 814 DRM_FORMAT_YUV420_8BIT, /* Amlogic FBC Only */ 815 DRM_FORMAT_YUV420_10BIT, /* Amlogic FBC Only */ 816 }; 817 818 static const uint64_t format_modifiers[] = { 819 DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, 820 AMLOGIC_FBC_OPTION_MEM_SAVING), 821 DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 822 AMLOGIC_FBC_OPTION_MEM_SAVING), 823 DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, 0), 824 DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0), 825 DRM_FORMAT_MOD_LINEAR, 826 DRM_FORMAT_MOD_INVALID, 827 }; 828 829 int meson_overlay_create(struct meson_drm *priv) 830 { 831 struct meson_overlay *meson_overlay; 832 struct drm_plane *plane; 833 834 DRM_DEBUG_DRIVER("\n"); 835 836 meson_overlay = devm_kzalloc(priv->drm->dev, sizeof(*meson_overlay), 837 GFP_KERNEL); 838 if (!meson_overlay) 839 return -ENOMEM; 840 841 meson_overlay->priv = priv; 842 plane = &meson_overlay->base; 843 844 drm_universal_plane_init(priv->drm, plane, 0xFF, 845 &meson_overlay_funcs, 846 supported_drm_formats, 847 ARRAY_SIZE(supported_drm_formats), 848 format_modifiers, 849 DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane"); 850 851 drm_plane_helper_add(plane, &meson_overlay_helper_funcs); 852 853 /* For now, VD Overlay plane is always on the back */ 854 drm_plane_create_zpos_immutable_property(plane, 0); 855 856 priv->overlay_plane = plane; 857 858 DRM_DEBUG_DRIVER("\n"); 859 860 return 0; 861 } 862