1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2020 BayLibre, SAS
4  * Author: Neil Armstrong <narmstrong@baylibre.com>
5  * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
6  */
7 
8 #ifndef __MESON_DW_MIPI_DSI_H
9 #define __MESON_DW_MIPI_DSI_H
10 
11 /* Top-level registers */
12 /* [31: 4]    Reserved.     Default 0.
13  *     [3] RW timing_rst_n: Default 1.
14  *		1=Assert SW reset of timing feature.   0=Release reset.
15  *     [2] RW dpi_rst_n: Default 1.
16  *		1=Assert SW reset on mipi_dsi_host_dpi block.   0=Release reset.
17  *     [1] RW intr_rst_n: Default 1.
18  *		1=Assert SW reset on mipi_dsi_host_intr block.  0=Release reset.
19  *     [0] RW dwc_rst_n:  Default 1.
20  *		1=Assert SW reset on IP core.   0=Release reset.
21  */
22 #define MIPI_DSI_TOP_SW_RESET                      0x3c0
23 
24 #define MIPI_DSI_TOP_SW_RESET_DWC	BIT(0)
25 #define MIPI_DSI_TOP_SW_RESET_INTR	BIT(1)
26 #define MIPI_DSI_TOP_SW_RESET_DPI	BIT(2)
27 #define MIPI_DSI_TOP_SW_RESET_TIMING	BIT(3)
28 
29 /* [31: 5] Reserved.   Default 0.
30  *     [4] RW manual_edpihalt: Default 0.
31  *		1=Manual suspend VencL; 0=do not suspend VencL.
32  *     [3] RW auto_edpihalt_en: Default 0.
33  *		1=Enable IP's edpihalt signal to suspend VencL;
34  *		0=IP's edpihalt signal does not affect VencL.
35  *     [2] RW clock_freerun: Apply to auto-clock gate only. Default 0.
36  *		0=Default, use auto-clock gating to save power;
37  *		1=use free-run clock, disable auto-clock gating, for debug mode.
38  *     [1] RW enable_pixclk: A manual clock gate option, due to DWC IP does not
39  *		have auto-clock gating. 1=Enable pixclk.      Default 0.
40  *     [0] RW enable_sysclk: A manual clock gate option, due to DWC IP does not
41  *		have auto-clock gating. 1=Enable sysclk.      Default 0.
42  */
43 #define MIPI_DSI_TOP_CLK_CNTL                      0x3c4
44 
45 #define MIPI_DSI_TOP_CLK_SYSCLK_EN	BIT(0)
46 #define MIPI_DSI_TOP_CLK_PIXCLK_EN	BIT(1)
47 
48 /* [31:24]    Reserved. Default 0.
49  * [23:20] RW dpi_color_mode: Define DPI pixel format. Default 0.
50  *		0=16-bit RGB565 config 1;
51  *		1=16-bit RGB565 config 2;
52  *		2=16-bit RGB565 config 3;
53  *		3=18-bit RGB666 config 1;
54  *		4=18-bit RGB666 config 2;
55  *		5=24-bit RGB888;
56  *		6=20-bit YCbCr 4:2:2;
57  *		7=24-bit YCbCr 4:2:2;
58  *		8=16-bit YCbCr 4:2:2;
59  *		9=30-bit RGB;
60  *		10=36-bit RGB;
61  *		11=12-bit YCbCr 4:2:0.
62  *    [19] Reserved. Default 0.
63  * [18:16] RW in_color_mode:  Define VENC data width. Default 0.
64  *		0=30-bit pixel;
65  *		1=24-bit pixel;
66  *		2=18-bit pixel, RGB666;
67  *		3=16-bit pixel, RGB565.
68  * [15:14] RW chroma_subsample: Define method of chroma subsampling. Default 0.
69  *		Applicable to YUV422 or YUV420 only.
70  *		0=Use even pixel's chroma;
71  *		1=Use odd pixel's chroma;
72  *		2=Use averaged value between even and odd pair.
73  * [13:12] RW comp2_sel:  Select which component to be Cr or B: Default 2.
74  *		0=comp0; 1=comp1; 2=comp2.
75  * [11:10] RW comp1_sel:  Select which component to be Cb or G: Default 1.
76  *		0=comp0; 1=comp1; 2=comp2.
77  *  [9: 8] RW comp0_sel:  Select which component to be Y  or R: Default 0.
78  *		0=comp0; 1=comp1; 2=comp2.
79  *     [7]    Reserved. Default 0.
80  *     [6] RW de_pol:  Default 0.
81  *		If DE input is active low, set to 1 to invert to active high.
82  *     [5] RW hsync_pol: Default 0.
83  *		If HS input is active low, set to 1 to invert to active high.
84  *     [4] RW vsync_pol: Default 0.
85  *		If VS input is active low, set to 1 to invert to active high.
86  *     [3] RW dpicolorm: Signal to IP.   Default 0.
87  *     [2] RW dpishutdn: Signal to IP.   Default 0.
88  *     [1]    Reserved.  Default 0.
89  *     [0]    Reserved.  Default 0.
90  */
91 #define MIPI_DSI_TOP_CNTL                          0x3c8
92 
93 /* VENC data width */
94 #define VENC_IN_COLOR_30B   0x0
95 #define VENC_IN_COLOR_24B   0x1
96 #define VENC_IN_COLOR_18B   0x2
97 #define VENC_IN_COLOR_16B   0x3
98 
99 /* DPI pixel format */
100 #define DPI_COLOR_16BIT_CFG_1		0
101 #define DPI_COLOR_16BIT_CFG_2		1
102 #define DPI_COLOR_16BIT_CFG_3		2
103 #define DPI_COLOR_18BIT_CFG_1		3
104 #define DPI_COLOR_18BIT_CFG_2		4
105 #define DPI_COLOR_24BIT			5
106 #define DPI_COLOR_20BIT_YCBCR_422	6
107 #define DPI_COLOR_24BIT_YCBCR_422	7
108 #define DPI_COLOR_16BIT_YCBCR_422	8
109 #define DPI_COLOR_30BIT			9
110 #define DPI_COLOR_36BIT			10
111 #define DPI_COLOR_12BIT_YCBCR_420	11
112 
113 #define MIPI_DSI_TOP_DPI_COLOR_MODE	GENMASK(23, 20)
114 #define MIPI_DSI_TOP_IN_COLOR_MODE	GENMASK(18, 16)
115 #define MIPI_DSI_TOP_CHROMA_SUBSAMPLE	GENMASK(15, 14)
116 #define MIPI_DSI_TOP_COMP2_SEL		GENMASK(13, 12)
117 #define MIPI_DSI_TOP_COMP1_SEL		GENMASK(11, 10)
118 #define MIPI_DSI_TOP_COMP0_SEL		GENMASK(9, 8)
119 #define MIPI_DSI_TOP_DE_INVERT		BIT(6)
120 #define MIPI_DSI_TOP_HSYNC_INVERT	BIT(5)
121 #define MIPI_DSI_TOP_VSYNC_INVERT	BIT(4)
122 #define MIPI_DSI_TOP_DPICOLORM		BIT(3)
123 #define MIPI_DSI_TOP_DPISHUTDN		BIT(2)
124 
125 #define MIPI_DSI_TOP_SUSPEND_CNTL                  0x3cc
126 #define MIPI_DSI_TOP_SUSPEND_LINE                  0x3d0
127 #define MIPI_DSI_TOP_SUSPEND_PIX                   0x3d4
128 #define MIPI_DSI_TOP_MEAS_CNTL                     0x3d8
129 /* [0] R  stat_edpihalt:  edpihalt signal from IP.    Default 0. */
130 #define MIPI_DSI_TOP_STAT                          0x3dc
131 #define MIPI_DSI_TOP_MEAS_STAT_TE0                 0x3e0
132 #define MIPI_DSI_TOP_MEAS_STAT_TE1                 0x3e4
133 #define MIPI_DSI_TOP_MEAS_STAT_VS0                 0x3e8
134 #define MIPI_DSI_TOP_MEAS_STAT_VS1                 0x3ec
135 /* [31:16] RW intr_stat/clr. Default 0.
136  *		For each bit, read as this interrupt level status,
137  *		write 1 to clear.
138  * [31:22] Reserved
139  * [   21] stat/clr of eof interrupt
140  * [   21] vde_fall interrupt
141  * [   19] stat/clr of de_rise interrupt
142  * [   18] stat/clr of vs_fall interrupt
143  * [   17] stat/clr of vs_rise interrupt
144  * [   16] stat/clr of dwc_edpite interrupt
145  * [15: 0] RW intr_enable. Default 0.
146  *		For each bit, 1=enable this interrupt, 0=disable.
147  *	[15: 6] Reserved
148  *	[    5] eof interrupt
149  *	[    4] de_fall interrupt
150  *	[    3] de_rise interrupt
151  *	[    2] vs_fall interrupt
152  *	[    1] vs_rise interrupt
153  *	[    0] dwc_edpite interrupt
154  */
155 #define MIPI_DSI_TOP_INTR_CNTL_STAT                0x3f0
156 // 31: 2    Reserved.   Default 0.
157 //  1: 0 RW mem_pd.     Default 3.
158 #define MIPI_DSI_TOP_MEM_PD                        0x3f4
159 
160 #endif /* __MESON_DW_MIPI_DSI_H */
161