1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __MESON_DW_HDMI_H 21 #define __MESON_DW_HDMI_H 22 23 /* 24 * Bit 15-10: RW Reserved. Default 1 starting from G12A 25 * Bit 9 RW sw_reset_i2c starting from G12A 26 * Bit 8 RW sw_reset_axiarb starting from G12A 27 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A 28 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A 29 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A 30 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. 31 * Default 1. 32 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; 33 * 0=Release from reset. 34 * Default 1. 35 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset. 36 * Default 1. 37 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset; 38 * 0=Release from reset. Default 1. 39 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset; 40 * 0=Release from reset. Default 1. 41 */ 42 #define HDMITX_TOP_SW_RESET (0x000) 43 44 /* 45 * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable 46 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. 47 * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. 48 * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. 49 * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. 50 * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. 51 * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable 52 * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable 53 * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable 54 * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A 55 * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. 56 * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. 57 * Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. 58 * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. 59 */ 60 #define HDMITX_TOP_CLK_CNTL (0x001) 61 62 /* 63 * Bit 31:28 RW rxsense_glitch_width: starting from G12A 64 * Bit 27:16 RW rxsense_valid_width: starting from G12A 65 * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. 66 * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. 67 */ 68 #define HDMITX_TOP_HPD_FILTER (0x002) 69 70 /* 71 * intr_maskn: MASK_N, one bit per interrupt source. 72 * 1=Enable interrupt source; 0=Disable interrupt source. Default 0. 73 * [ 7] rxsense_fall starting from G12A 74 * [ 6] rxsense_rise starting from G12A 75 * [ 5] err_i2c_timeout starting from G12A 76 * [ 4] hdcp22_rndnum_err 77 * [ 3] nonce_rfrsh_rise 78 * [ 2] hpd_fall_intr 79 * [ 1] hpd_rise_intr 80 * [ 0] core_intr 81 */ 82 #define HDMITX_TOP_INTR_MASKN (0x003) 83 84 /* 85 * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt 86 * bit, read back the interrupt status. 87 * Bit 31 R IP interrupt status 88 * Bit 7 RW rxsense_fall starting from G12A 89 * Bit 6 RW rxsense_rise starting from G12A 90 * Bit 5 RW err_i2c_timeout starting from G12A 91 * Bit 2 RW hpd_fall 92 * Bit 1 RW hpd_rise 93 * Bit 0 RW IP interrupt 94 */ 95 #define HDMITX_TOP_INTR_STAT (0x004) 96 97 /* 98 * [7] rxsense_fall starting from G12A 99 * [6] rxsense_rise starting from G12A 100 * [5] err_i2c_timeout starting from G12A 101 * [4] hdcp22_rndnum_err 102 * [3] nonce_rfrsh_rise 103 * [2] hpd_fall 104 * [1] hpd_rise 105 * [0] core_intr_rise 106 */ 107 #define HDMITX_TOP_INTR_STAT_CLR (0x005) 108 109 #define HDMITX_TOP_INTR_CORE BIT(0) 110 #define HDMITX_TOP_INTR_HPD_RISE BIT(1) 111 #define HDMITX_TOP_INTR_HPD_FALL BIT(2) 112 #define HDMITX_TOP_INTR_RXSENSE_RISE BIT(6) 113 #define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7) 114 115 /* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; 116 * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. 117 * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern 118 * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0. 119 * Bit 8 RW shift_pttn_en: 1= Enable shift pattern generator; 0=Disable. 120 * Default 0. 121 * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0. 122 * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern; 123 * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0. 124 * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0. 125 */ 126 #define HDMITX_TOP_BIST_CNTL (0x006) 127 128 /* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */ 129 /* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */ 130 /* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */ 131 #define HDMITX_TOP_SHIFT_PTTN_012 (0x007) 132 133 /* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */ 134 /* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */ 135 /* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */ 136 #define HDMITX_TOP_SHIFT_PTTN_345 (0x008) 137 138 /* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */ 139 /* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */ 140 #define HDMITX_TOP_SHIFT_PTTN_67 (0x009) 141 142 /* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */ 143 /* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */ 144 #define HDMITX_TOP_TMDS_CLK_PTTN_01 (0x00A) 145 146 /* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */ 147 /* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ 148 #define HDMITX_TOP_TMDS_CLK_PTTN_23 (0x00B) 149 150 /* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, 151 * used when TMDS CLK rate = TMDS character rate /4. Default 0. 152 * Bit 0 R Reserved. Default 0. 153 * [ 1] shift_tmds_clk_pttn 154 * [ 0] load_tmds_clk_pttn 155 */ 156 #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (0x00C) 157 158 /* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM 159 * failure, write 1 to clear the failure flag. Default 0. 160 */ 161 #define HDMITX_TOP_REVOCMEM_STAT (0x00D) 162 163 /* Bit 1 R filtered RxSense status 164 * Bit 0 R filtered HPD status. 165 */ 166 #define HDMITX_TOP_STAT0 (0x00E) 167 168 #endif /* __MESON_DW_HDMI_H */ 169