1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/of_graph.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/reset.h> 16 17 #include <drm/bridge/dw_hdmi.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_device.h> 20 #include <drm/drm_edid.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_print.h> 23 24 #include <linux/media-bus-format.h> 25 #include <linux/videodev2.h> 26 27 #include "meson_drv.h" 28 #include "meson_dw_hdmi.h" 29 #include "meson_registers.h" 30 #include "meson_vclk.h" 31 #include "meson_venc.h" 32 33 #define DRIVER_NAME "meson-dw-hdmi" 34 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver" 35 36 /** 37 * DOC: HDMI Output 38 * 39 * HDMI Output is composed of : 40 * 41 * - A Synopsys DesignWare HDMI Controller IP 42 * - A TOP control block controlling the Clocks and PHY 43 * - A custom HDMI PHY in order convert video to TMDS signal 44 * 45 * .. code:: 46 * 47 * ___________________________________ 48 * | HDMI TOP |<= HPD 49 * |___________________________________| 50 * | | | 51 * | Synopsys HDMI | HDMI PHY |=> TMDS 52 * | Controller |________________| 53 * |___________________________________|<=> DDC 54 * 55 * 56 * The HDMI TOP block only supports HPD sensing. 57 * The Synopsys HDMI Controller interrupt is routed 58 * through the TOP Block interrupt. 59 * Communication to the TOP Block and the Synopsys 60 * HDMI Controller is done a pair of addr+read/write 61 * registers. 62 * The HDMI PHY is configured by registers in the 63 * HHI register block. 64 * 65 * Pixel data arrives in 4:4:4 format from the VENC 66 * block and the VPU HDMI mux selects either the ENCI 67 * encoder for the 576i or 480i formats or the ENCP 68 * encoder for all the other formats including 69 * interlaced HD formats. 70 * The VENC uses a DVI encoder on top of the ENCI 71 * or ENCP encoders to generate DVI timings for the 72 * HDMI controller. 73 * 74 * GXBB, GXL and GXM embeds the Synopsys DesignWare 75 * HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF 76 * audio source interfaces. 77 * 78 * We handle the following features : 79 * 80 * - HPD Rise & Fall interrupt 81 * - HDMI Controller Interrupt 82 * - HDMI PHY Init for 480i to 1080p60 83 * - VENC & HDMI Clock setup for 480i to 1080p60 84 * - VENC Mode setup for 480i to 1080p60 85 * 86 * What is missing : 87 * 88 * - PHY, Clock and Mode setup for 2k && 4k modes 89 * - SDDC Scrambling mode for HDMI 2.0a 90 * - HDCP Setup 91 * - CEC Management 92 */ 93 94 /* TOP Block Communication Channel */ 95 #define HDMITX_TOP_ADDR_REG 0x0 96 #define HDMITX_TOP_DATA_REG 0x4 97 #define HDMITX_TOP_CTRL_REG 0x8 98 #define HDMITX_TOP_G12A_OFFSET 0x8000 99 100 /* Controller Communication Channel */ 101 #define HDMITX_DWC_ADDR_REG 0x10 102 #define HDMITX_DWC_DATA_REG 0x14 103 #define HDMITX_DWC_CTRL_REG 0x18 104 105 /* HHI Registers */ 106 #define HHI_MEM_PD_REG0 0x100 /* 0x40 */ 107 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ 108 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */ 109 #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */ 110 #define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */ 111 #define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */ 112 #define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */ 113 #define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */ 114 115 static DEFINE_SPINLOCK(reg_lock); 116 117 enum meson_venc_source { 118 MESON_VENC_SOURCE_NONE = 0, 119 MESON_VENC_SOURCE_ENCI = 1, 120 MESON_VENC_SOURCE_ENCP = 2, 121 }; 122 123 struct meson_dw_hdmi; 124 125 struct meson_dw_hdmi_data { 126 unsigned int (*top_read)(struct meson_dw_hdmi *dw_hdmi, 127 unsigned int addr); 128 void (*top_write)(struct meson_dw_hdmi *dw_hdmi, 129 unsigned int addr, unsigned int data); 130 unsigned int (*dwc_read)(struct meson_dw_hdmi *dw_hdmi, 131 unsigned int addr); 132 void (*dwc_write)(struct meson_dw_hdmi *dw_hdmi, 133 unsigned int addr, unsigned int data); 134 }; 135 136 struct meson_dw_hdmi { 137 struct drm_encoder encoder; 138 struct dw_hdmi_plat_data dw_plat_data; 139 struct meson_drm *priv; 140 struct device *dev; 141 void __iomem *hdmitx; 142 const struct meson_dw_hdmi_data *data; 143 struct reset_control *hdmitx_apb; 144 struct reset_control *hdmitx_ctrl; 145 struct reset_control *hdmitx_phy; 146 struct clk *hdmi_pclk; 147 struct clk *venci_clk; 148 struct regulator *hdmi_supply; 149 u32 irq_stat; 150 struct dw_hdmi *hdmi; 151 }; 152 #define encoder_to_meson_dw_hdmi(x) \ 153 container_of(x, struct meson_dw_hdmi, encoder) 154 155 static inline int dw_hdmi_is_compatible(struct meson_dw_hdmi *dw_hdmi, 156 const char *compat) 157 { 158 return of_device_is_compatible(dw_hdmi->dev->of_node, compat); 159 } 160 161 /* PHY (via TOP bridge) and Controller dedicated register interface */ 162 163 static unsigned int dw_hdmi_top_read(struct meson_dw_hdmi *dw_hdmi, 164 unsigned int addr) 165 { 166 unsigned long flags; 167 unsigned int data; 168 169 spin_lock_irqsave(®_lock, flags); 170 171 /* ADDR must be written twice */ 172 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); 173 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); 174 175 /* Read needs a second DATA read */ 176 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); 177 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); 178 179 spin_unlock_irqrestore(®_lock, flags); 180 181 return data; 182 } 183 184 static unsigned int dw_hdmi_g12a_top_read(struct meson_dw_hdmi *dw_hdmi, 185 unsigned int addr) 186 { 187 return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); 188 } 189 190 static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi, 191 unsigned int addr, unsigned int data) 192 { 193 unsigned long flags; 194 195 spin_lock_irqsave(®_lock, flags); 196 197 /* ADDR must be written twice */ 198 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); 199 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); 200 201 /* Write needs single DATA write */ 202 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); 203 204 spin_unlock_irqrestore(®_lock, flags); 205 } 206 207 static inline void dw_hdmi_g12a_top_write(struct meson_dw_hdmi *dw_hdmi, 208 unsigned int addr, unsigned int data) 209 { 210 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); 211 } 212 213 /* Helper to change specific bits in PHY registers */ 214 static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi *dw_hdmi, 215 unsigned int addr, 216 unsigned int mask, 217 unsigned int val) 218 { 219 unsigned int data = dw_hdmi->data->top_read(dw_hdmi, addr); 220 221 data &= ~mask; 222 data |= val; 223 224 dw_hdmi->data->top_write(dw_hdmi, addr, data); 225 } 226 227 static unsigned int dw_hdmi_dwc_read(struct meson_dw_hdmi *dw_hdmi, 228 unsigned int addr) 229 { 230 unsigned long flags; 231 unsigned int data; 232 233 spin_lock_irqsave(®_lock, flags); 234 235 /* ADDR must be written twice */ 236 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); 237 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); 238 239 /* Read needs a second DATA read */ 240 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); 241 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); 242 243 spin_unlock_irqrestore(®_lock, flags); 244 245 return data; 246 } 247 248 static unsigned int dw_hdmi_g12a_dwc_read(struct meson_dw_hdmi *dw_hdmi, 249 unsigned int addr) 250 { 251 return readb(dw_hdmi->hdmitx + addr); 252 } 253 254 static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi, 255 unsigned int addr, unsigned int data) 256 { 257 unsigned long flags; 258 259 spin_lock_irqsave(®_lock, flags); 260 261 /* ADDR must be written twice */ 262 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); 263 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); 264 265 /* Write needs single DATA write */ 266 writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); 267 268 spin_unlock_irqrestore(®_lock, flags); 269 } 270 271 static inline void dw_hdmi_g12a_dwc_write(struct meson_dw_hdmi *dw_hdmi, 272 unsigned int addr, unsigned int data) 273 { 274 writeb(data, dw_hdmi->hdmitx + addr); 275 } 276 277 /* Helper to change specific bits in controller registers */ 278 static inline void dw_hdmi_dwc_write_bits(struct meson_dw_hdmi *dw_hdmi, 279 unsigned int addr, 280 unsigned int mask, 281 unsigned int val) 282 { 283 unsigned int data = dw_hdmi->data->dwc_read(dw_hdmi, addr); 284 285 data &= ~mask; 286 data |= val; 287 288 dw_hdmi->data->dwc_write(dw_hdmi, addr, data); 289 } 290 291 /* Bridge */ 292 293 /* Setup PHY bandwidth modes */ 294 static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi, 295 struct drm_display_mode *mode) 296 { 297 struct meson_drm *priv = dw_hdmi->priv; 298 unsigned int pixel_clock = mode->clock; 299 300 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || 301 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) { 302 if (pixel_clock >= 371250) { 303 /* 5.94Gbps, 3.7125Gbps */ 304 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x333d3282); 305 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b); 306 } else if (pixel_clock >= 297000) { 307 /* 2.97Gbps */ 308 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382); 309 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b); 310 } else if (pixel_clock >= 148500) { 311 /* 1.485Gbps */ 312 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303362); 313 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2016315b); 314 } else { 315 /* 742.5Mbps, and below */ 316 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33604142); 317 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x0016315b); 318 } 319 } else if (dw_hdmi_is_compatible(dw_hdmi, 320 "amlogic,meson-gxbb-dw-hdmi")) { 321 if (pixel_clock >= 371250) { 322 /* 5.94Gbps, 3.7125Gbps */ 323 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33353245); 324 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2100115b); 325 } else if (pixel_clock >= 297000) { 326 /* 2.97Gbps */ 327 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33634283); 328 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0xb000115b); 329 } else { 330 /* 1.485Gbps, and below */ 331 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33632122); 332 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2000115b); 333 } 334 } else if (dw_hdmi_is_compatible(dw_hdmi, 335 "amlogic,meson-g12a-dw-hdmi")) { 336 if (pixel_clock >= 371250) { 337 /* 5.94Gbps, 3.7125Gbps */ 338 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x37eb65c4); 339 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); 340 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x0000080b); 341 } else if (pixel_clock >= 297000) { 342 /* 2.97Gbps */ 343 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb6262); 344 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); 345 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003); 346 } else { 347 /* 1.485Gbps, and below */ 348 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb4242); 349 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); 350 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003); 351 } 352 } 353 } 354 355 static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi) 356 { 357 struct meson_drm *priv = dw_hdmi->priv; 358 359 /* Enable and software reset */ 360 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); 361 362 mdelay(2); 363 364 /* Enable and unreset */ 365 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); 366 367 mdelay(2); 368 } 369 370 static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, 371 struct drm_display_mode *mode) 372 { 373 struct meson_drm *priv = dw_hdmi->priv; 374 int vic = drm_match_cea_mode(mode); 375 unsigned int vclk_freq; 376 unsigned int venc_freq; 377 unsigned int hdmi_freq; 378 379 vclk_freq = mode->clock; 380 381 if (!vic) { 382 meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, vclk_freq, 383 vclk_freq, vclk_freq, false); 384 return; 385 } 386 387 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 388 vclk_freq *= 2; 389 390 venc_freq = vclk_freq; 391 hdmi_freq = vclk_freq; 392 393 if (meson_venc_hdmi_venc_repeat(vic)) 394 venc_freq *= 2; 395 396 vclk_freq = max(venc_freq, hdmi_freq); 397 398 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 399 venc_freq /= 2; 400 401 DRM_DEBUG_DRIVER("vclk:%d venc=%d hdmi=%d enci=%d\n", 402 vclk_freq, venc_freq, hdmi_freq, 403 priv->venc.hdmi_use_enci); 404 405 meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, vclk_freq, 406 venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); 407 } 408 409 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 410 struct drm_display_mode *mode) 411 { 412 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; 413 struct meson_drm *priv = dw_hdmi->priv; 414 unsigned int wr_clk = 415 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); 416 417 DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name, 418 mode->clock > 340000 ? 40 : 10); 419 420 /* Enable clocks */ 421 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); 422 423 /* Bring HDMITX MEM output of power down */ 424 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); 425 426 /* Bring out of reset */ 427 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0); 428 429 /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */ 430 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL, 431 0x3, 0x3); 432 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL, 433 0x3 << 4, 0x3 << 4); 434 435 /* Enable normal output to PHY */ 436 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); 437 438 /* TMDS pattern setup (TOFIX Handle the YUV420 case) */ 439 if (mode->clock > 340000) { 440 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 441 0); 442 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 443 0x03ff03ff); 444 } else { 445 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 446 0x001f001f); 447 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 448 0x001f001f); 449 } 450 451 /* Load TMDS pattern */ 452 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); 453 msleep(20); 454 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); 455 456 /* Setup PHY parameters */ 457 meson_hdmi_phy_setup_mode(dw_hdmi, mode); 458 459 /* Setup PHY */ 460 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 461 0xffff << 16, 0x0390 << 16); 462 463 /* BIT_INVERT */ 464 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || 465 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") || 466 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi")) 467 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 468 BIT(17), 0); 469 else 470 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 471 BIT(17), BIT(17)); 472 473 /* Disable clock, fifo, fifo_wr */ 474 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); 475 476 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 477 478 msleep(100); 479 480 /* Reset PHY 3 times in a row */ 481 meson_dw_hdmi_phy_reset(dw_hdmi); 482 meson_dw_hdmi_phy_reset(dw_hdmi); 483 meson_dw_hdmi_phy_reset(dw_hdmi); 484 485 /* Temporary Disable VENC video stream */ 486 if (priv->venc.hdmi_use_enci) 487 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 488 else 489 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 490 491 /* Temporary Disable HDMI video stream to HDMI-TX */ 492 writel_bits_relaxed(0x3, 0, 493 priv->io_base + _REG(VPU_HDMI_SETTING)); 494 writel_bits_relaxed(0xf << 8, 0, 495 priv->io_base + _REG(VPU_HDMI_SETTING)); 496 497 /* Re-Enable VENC video stream */ 498 if (priv->venc.hdmi_use_enci) 499 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 500 else 501 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); 502 503 /* Push back HDMI clock settings */ 504 writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), 505 priv->io_base + _REG(VPU_HDMI_SETTING)); 506 507 /* Enable and Select HDMI video source for HDMI-TX */ 508 if (priv->venc.hdmi_use_enci) 509 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, 510 priv->io_base + _REG(VPU_HDMI_SETTING)); 511 else 512 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, 513 priv->io_base + _REG(VPU_HDMI_SETTING)); 514 515 return 0; 516 } 517 518 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, 519 void *data) 520 { 521 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; 522 struct meson_drm *priv = dw_hdmi->priv; 523 524 DRM_DEBUG_DRIVER("\n"); 525 526 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); 527 } 528 529 static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi, 530 void *data) 531 { 532 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; 533 534 return !!dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_STAT0) ? 535 connector_status_connected : connector_status_disconnected; 536 } 537 538 static void dw_hdmi_setup_hpd(struct dw_hdmi *hdmi, 539 void *data) 540 { 541 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; 542 543 /* Setup HPD Filter */ 544 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER, 545 (0xa << 12) | 0xa0); 546 547 /* Clear interrupts */ 548 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, 549 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL); 550 551 /* Unmask interrupts */ 552 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_INTR_MASKN, 553 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL, 554 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL); 555 } 556 557 static const struct dw_hdmi_phy_ops meson_dw_hdmi_phy_ops = { 558 .init = dw_hdmi_phy_init, 559 .disable = dw_hdmi_phy_disable, 560 .read_hpd = dw_hdmi_read_hpd, 561 .setup_hpd = dw_hdmi_setup_hpd, 562 }; 563 564 static irqreturn_t dw_hdmi_top_irq(int irq, void *dev_id) 565 { 566 struct meson_dw_hdmi *dw_hdmi = dev_id; 567 u32 stat; 568 569 stat = dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_INTR_STAT); 570 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat); 571 572 /* HPD Events, handle in the threaded interrupt handler */ 573 if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) { 574 dw_hdmi->irq_stat = stat; 575 return IRQ_WAKE_THREAD; 576 } 577 578 /* HDMI Controller Interrupt */ 579 if (stat & 1) 580 return IRQ_NONE; 581 582 /* TOFIX Handle HDCP Interrupts */ 583 584 return IRQ_HANDLED; 585 } 586 587 /* Threaded interrupt handler to manage HPD events */ 588 static irqreturn_t dw_hdmi_top_thread_irq(int irq, void *dev_id) 589 { 590 struct meson_dw_hdmi *dw_hdmi = dev_id; 591 u32 stat = dw_hdmi->irq_stat; 592 593 /* HPD Events */ 594 if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) { 595 bool hpd_connected = false; 596 597 if (stat & HDMITX_TOP_INTR_HPD_RISE) 598 hpd_connected = true; 599 600 dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected, 601 hpd_connected); 602 603 drm_helper_hpd_irq_event(dw_hdmi->encoder.dev); 604 } 605 606 return IRQ_HANDLED; 607 } 608 609 static enum drm_mode_status 610 dw_hdmi_mode_valid(struct drm_connector *connector, 611 const struct drm_display_mode *mode) 612 { 613 struct meson_drm *priv = connector->dev->dev_private; 614 unsigned int vclk_freq; 615 unsigned int venc_freq; 616 unsigned int hdmi_freq; 617 int vic = drm_match_cea_mode(mode); 618 enum drm_mode_status status; 619 620 DRM_DEBUG_DRIVER("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); 621 622 /* If sink max TMDS clock, we reject the mode */ 623 if (connector->display_info.max_tmds_clock && 624 mode->clock > connector->display_info.max_tmds_clock) 625 return MODE_BAD; 626 627 /* Check against non-VIC supported modes */ 628 if (!vic) { 629 status = meson_venc_hdmi_supported_mode(mode); 630 if (status != MODE_OK) 631 return status; 632 633 return meson_vclk_dmt_supported_freq(priv, mode->clock); 634 /* Check against supported VIC modes */ 635 } else if (!meson_venc_hdmi_supported_vic(vic)) 636 return MODE_BAD; 637 638 vclk_freq = mode->clock; 639 640 /* 480i/576i needs global pixel doubling */ 641 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 642 vclk_freq *= 2; 643 644 venc_freq = vclk_freq; 645 hdmi_freq = vclk_freq; 646 647 /* VENC double pixels for 1080i and 720p modes */ 648 if (meson_venc_hdmi_venc_repeat(vic)) 649 venc_freq *= 2; 650 651 vclk_freq = max(venc_freq, hdmi_freq); 652 653 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 654 venc_freq /= 2; 655 656 dev_dbg(connector->dev->dev, "%s: vclk:%d venc=%d hdmi=%d\n", __func__, 657 vclk_freq, venc_freq, hdmi_freq); 658 659 return meson_vclk_vic_supported_freq(vclk_freq); 660 } 661 662 /* Encoder */ 663 664 static void meson_venc_hdmi_encoder_destroy(struct drm_encoder *encoder) 665 { 666 drm_encoder_cleanup(encoder); 667 } 668 669 static const struct drm_encoder_funcs meson_venc_hdmi_encoder_funcs = { 670 .destroy = meson_venc_hdmi_encoder_destroy, 671 }; 672 673 static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 674 struct drm_crtc_state *crtc_state, 675 struct drm_connector_state *conn_state) 676 { 677 return 0; 678 } 679 680 static void meson_venc_hdmi_encoder_disable(struct drm_encoder *encoder) 681 { 682 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); 683 struct meson_drm *priv = dw_hdmi->priv; 684 685 DRM_DEBUG_DRIVER("\n"); 686 687 writel_bits_relaxed(0x3, 0, 688 priv->io_base + _REG(VPU_HDMI_SETTING)); 689 690 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 691 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 692 } 693 694 static void meson_venc_hdmi_encoder_enable(struct drm_encoder *encoder) 695 { 696 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); 697 struct meson_drm *priv = dw_hdmi->priv; 698 699 DRM_DEBUG_DRIVER("%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP"); 700 701 if (priv->venc.hdmi_use_enci) 702 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 703 else 704 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); 705 } 706 707 static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder, 708 struct drm_display_mode *mode, 709 struct drm_display_mode *adjusted_mode) 710 { 711 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); 712 struct meson_drm *priv = dw_hdmi->priv; 713 int vic = drm_match_cea_mode(mode); 714 715 DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode->name, vic); 716 717 /* VENC + VENC-DVI Mode setup */ 718 meson_venc_hdmi_mode_set(priv, vic, mode); 719 720 /* VCLK Set clock */ 721 dw_hdmi_set_vclk(dw_hdmi, mode); 722 723 /* Setup YUV444 to HDMI-TX, no 10bit diphering */ 724 writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); 725 } 726 727 static const struct drm_encoder_helper_funcs 728 meson_venc_hdmi_encoder_helper_funcs = { 729 .atomic_check = meson_venc_hdmi_encoder_atomic_check, 730 .disable = meson_venc_hdmi_encoder_disable, 731 .enable = meson_venc_hdmi_encoder_enable, 732 .mode_set = meson_venc_hdmi_encoder_mode_set, 733 }; 734 735 /* DW HDMI Regmap */ 736 737 static int meson_dw_hdmi_reg_read(void *context, unsigned int reg, 738 unsigned int *result) 739 { 740 struct meson_dw_hdmi *dw_hdmi = context; 741 742 *result = dw_hdmi->data->dwc_read(dw_hdmi, reg); 743 744 return 0; 745 746 } 747 748 static int meson_dw_hdmi_reg_write(void *context, unsigned int reg, 749 unsigned int val) 750 { 751 struct meson_dw_hdmi *dw_hdmi = context; 752 753 dw_hdmi->data->dwc_write(dw_hdmi, reg, val); 754 755 return 0; 756 } 757 758 static const struct regmap_config meson_dw_hdmi_regmap_config = { 759 .reg_bits = 32, 760 .val_bits = 8, 761 .reg_read = meson_dw_hdmi_reg_read, 762 .reg_write = meson_dw_hdmi_reg_write, 763 .max_register = 0x10000, 764 .fast_io = true, 765 }; 766 767 static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = { 768 .top_read = dw_hdmi_top_read, 769 .top_write = dw_hdmi_top_write, 770 .dwc_read = dw_hdmi_dwc_read, 771 .dwc_write = dw_hdmi_dwc_write, 772 }; 773 774 static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = { 775 .top_read = dw_hdmi_g12a_top_read, 776 .top_write = dw_hdmi_g12a_top_write, 777 .dwc_read = dw_hdmi_g12a_dwc_read, 778 .dwc_write = dw_hdmi_g12a_dwc_write, 779 }; 780 781 static bool meson_hdmi_connector_is_available(struct device *dev) 782 { 783 struct device_node *ep, *remote; 784 785 /* HDMI Connector is on the second port, first endpoint */ 786 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, 0); 787 if (!ep) 788 return false; 789 790 /* If the endpoint node exists, consider it enabled */ 791 remote = of_graph_get_remote_port(ep); 792 if (remote) { 793 of_node_put(ep); 794 return true; 795 } 796 797 of_node_put(ep); 798 of_node_put(remote); 799 800 return false; 801 } 802 803 static int meson_dw_hdmi_bind(struct device *dev, struct device *master, 804 void *data) 805 { 806 struct platform_device *pdev = to_platform_device(dev); 807 const struct meson_dw_hdmi_data *match; 808 struct meson_dw_hdmi *meson_dw_hdmi; 809 struct drm_device *drm = data; 810 struct meson_drm *priv = drm->dev_private; 811 struct dw_hdmi_plat_data *dw_plat_data; 812 struct drm_encoder *encoder; 813 struct resource *res; 814 int irq; 815 int ret; 816 817 DRM_DEBUG_DRIVER("\n"); 818 819 if (!meson_hdmi_connector_is_available(dev)) { 820 dev_info(drm->dev, "HDMI Output connector not available\n"); 821 return -ENODEV; 822 } 823 824 match = of_device_get_match_data(&pdev->dev); 825 if (!match) { 826 dev_err(&pdev->dev, "failed to get match data\n"); 827 return -ENODEV; 828 } 829 830 meson_dw_hdmi = devm_kzalloc(dev, sizeof(*meson_dw_hdmi), 831 GFP_KERNEL); 832 if (!meson_dw_hdmi) 833 return -ENOMEM; 834 835 meson_dw_hdmi->priv = priv; 836 meson_dw_hdmi->dev = dev; 837 meson_dw_hdmi->data = match; 838 dw_plat_data = &meson_dw_hdmi->dw_plat_data; 839 encoder = &meson_dw_hdmi->encoder; 840 841 meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi"); 842 if (IS_ERR(meson_dw_hdmi->hdmi_supply)) { 843 if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER) 844 return -EPROBE_DEFER; 845 meson_dw_hdmi->hdmi_supply = NULL; 846 } else { 847 ret = regulator_enable(meson_dw_hdmi->hdmi_supply); 848 if (ret) 849 return ret; 850 } 851 852 meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev, 853 "hdmitx_apb"); 854 if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) { 855 dev_err(dev, "Failed to get hdmitx_apb reset\n"); 856 return PTR_ERR(meson_dw_hdmi->hdmitx_apb); 857 } 858 859 meson_dw_hdmi->hdmitx_ctrl = devm_reset_control_get_exclusive(dev, 860 "hdmitx"); 861 if (IS_ERR(meson_dw_hdmi->hdmitx_ctrl)) { 862 dev_err(dev, "Failed to get hdmitx reset\n"); 863 return PTR_ERR(meson_dw_hdmi->hdmitx_ctrl); 864 } 865 866 meson_dw_hdmi->hdmitx_phy = devm_reset_control_get_exclusive(dev, 867 "hdmitx_phy"); 868 if (IS_ERR(meson_dw_hdmi->hdmitx_phy)) { 869 dev_err(dev, "Failed to get hdmitx_phy reset\n"); 870 return PTR_ERR(meson_dw_hdmi->hdmitx_phy); 871 } 872 873 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 874 meson_dw_hdmi->hdmitx = devm_ioremap_resource(dev, res); 875 if (IS_ERR(meson_dw_hdmi->hdmitx)) 876 return PTR_ERR(meson_dw_hdmi->hdmitx); 877 878 meson_dw_hdmi->hdmi_pclk = devm_clk_get(dev, "isfr"); 879 if (IS_ERR(meson_dw_hdmi->hdmi_pclk)) { 880 dev_err(dev, "Unable to get HDMI pclk\n"); 881 return PTR_ERR(meson_dw_hdmi->hdmi_pclk); 882 } 883 clk_prepare_enable(meson_dw_hdmi->hdmi_pclk); 884 885 meson_dw_hdmi->venci_clk = devm_clk_get(dev, "venci"); 886 if (IS_ERR(meson_dw_hdmi->venci_clk)) { 887 dev_err(dev, "Unable to get venci clk\n"); 888 return PTR_ERR(meson_dw_hdmi->venci_clk); 889 } 890 clk_prepare_enable(meson_dw_hdmi->venci_clk); 891 892 dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi, 893 &meson_dw_hdmi_regmap_config); 894 if (IS_ERR(dw_plat_data->regm)) 895 return PTR_ERR(dw_plat_data->regm); 896 897 irq = platform_get_irq(pdev, 0); 898 if (irq < 0) { 899 dev_err(dev, "Failed to get hdmi top irq\n"); 900 return irq; 901 } 902 903 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_top_irq, 904 dw_hdmi_top_thread_irq, IRQF_SHARED, 905 "dw_hdmi_top_irq", meson_dw_hdmi); 906 if (ret) { 907 dev_err(dev, "Failed to request hdmi top irq\n"); 908 return ret; 909 } 910 911 /* Encoder */ 912 913 drm_encoder_helper_add(encoder, &meson_venc_hdmi_encoder_helper_funcs); 914 915 ret = drm_encoder_init(drm, encoder, &meson_venc_hdmi_encoder_funcs, 916 DRM_MODE_ENCODER_TMDS, "meson_hdmi"); 917 if (ret) { 918 dev_err(priv->dev, "Failed to init HDMI encoder\n"); 919 return ret; 920 } 921 922 encoder->possible_crtcs = BIT(0); 923 924 DRM_DEBUG_DRIVER("encoder initialized\n"); 925 926 /* Enable clocks */ 927 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); 928 929 /* Bring HDMITX MEM output of power down */ 930 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); 931 932 /* Reset HDMITX APB & TX & PHY */ 933 reset_control_reset(meson_dw_hdmi->hdmitx_apb); 934 reset_control_reset(meson_dw_hdmi->hdmitx_ctrl); 935 reset_control_reset(meson_dw_hdmi->hdmitx_phy); 936 937 /* Enable APB3 fail on error */ 938 if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 939 writel_bits_relaxed(BIT(15), BIT(15), 940 meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG); 941 writel_bits_relaxed(BIT(15), BIT(15), 942 meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG); 943 } 944 945 /* Bring out of reset */ 946 meson_dw_hdmi->data->top_write(meson_dw_hdmi, 947 HDMITX_TOP_SW_RESET, 0); 948 949 msleep(20); 950 951 meson_dw_hdmi->data->top_write(meson_dw_hdmi, 952 HDMITX_TOP_CLK_CNTL, 0xff); 953 954 /* Enable HDMI-TX Interrupt */ 955 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, 956 HDMITX_TOP_INTR_CORE); 957 958 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN, 959 HDMITX_TOP_INTR_CORE); 960 961 /* Bridge / Connector */ 962 963 dw_plat_data->mode_valid = dw_hdmi_mode_valid; 964 dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops; 965 dw_plat_data->phy_name = "meson_dw_hdmi_phy"; 966 dw_plat_data->phy_data = meson_dw_hdmi; 967 dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24; 968 dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; 969 970 platform_set_drvdata(pdev, meson_dw_hdmi); 971 972 meson_dw_hdmi->hdmi = dw_hdmi_bind(pdev, encoder, 973 &meson_dw_hdmi->dw_plat_data); 974 if (IS_ERR(meson_dw_hdmi->hdmi)) 975 return PTR_ERR(meson_dw_hdmi->hdmi); 976 977 DRM_DEBUG_DRIVER("HDMI controller initialized\n"); 978 979 return 0; 980 } 981 982 static void meson_dw_hdmi_unbind(struct device *dev, struct device *master, 983 void *data) 984 { 985 struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev); 986 987 dw_hdmi_unbind(meson_dw_hdmi->hdmi); 988 } 989 990 static const struct component_ops meson_dw_hdmi_ops = { 991 .bind = meson_dw_hdmi_bind, 992 .unbind = meson_dw_hdmi_unbind, 993 }; 994 995 static int meson_dw_hdmi_probe(struct platform_device *pdev) 996 { 997 return component_add(&pdev->dev, &meson_dw_hdmi_ops); 998 } 999 1000 static int meson_dw_hdmi_remove(struct platform_device *pdev) 1001 { 1002 component_del(&pdev->dev, &meson_dw_hdmi_ops); 1003 1004 return 0; 1005 } 1006 1007 static const struct of_device_id meson_dw_hdmi_of_table[] = { 1008 { .compatible = "amlogic,meson-gxbb-dw-hdmi", 1009 .data = &meson_dw_hdmi_gx_data }, 1010 { .compatible = "amlogic,meson-gxl-dw-hdmi", 1011 .data = &meson_dw_hdmi_gx_data }, 1012 { .compatible = "amlogic,meson-gxm-dw-hdmi", 1013 .data = &meson_dw_hdmi_gx_data }, 1014 { .compatible = "amlogic,meson-g12a-dw-hdmi", 1015 .data = &meson_dw_hdmi_g12a_data }, 1016 { } 1017 }; 1018 MODULE_DEVICE_TABLE(of, meson_dw_hdmi_of_table); 1019 1020 static struct platform_driver meson_dw_hdmi_platform_driver = { 1021 .probe = meson_dw_hdmi_probe, 1022 .remove = meson_dw_hdmi_remove, 1023 .driver = { 1024 .name = DRIVER_NAME, 1025 .of_match_table = meson_dw_hdmi_of_table, 1026 }, 1027 }; 1028 module_platform_driver(meson_dw_hdmi_platform_driver); 1029 1030 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 1031 MODULE_DESCRIPTION(DRIVER_DESC); 1032 MODULE_LICENSE("GPL"); 1033