1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/component.h> 23 #include <linux/of_graph.h> 24 #include <linux/reset.h> 25 #include <linux/clk.h> 26 #include <linux/regulator/consumer.h> 27 28 #include <drm/drmP.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/bridge/dw_hdmi.h> 33 34 #include <uapi/linux/media-bus-format.h> 35 #include <uapi/linux/videodev2.h> 36 37 #include "meson_drv.h" 38 #include "meson_venc.h" 39 #include "meson_vclk.h" 40 #include "meson_dw_hdmi.h" 41 #include "meson_registers.h" 42 43 #define DRIVER_NAME "meson-dw-hdmi" 44 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver" 45 46 /** 47 * DOC: HDMI Output 48 * 49 * HDMI Output is composed of : 50 * 51 * - A Synopsys DesignWare HDMI Controller IP 52 * - A TOP control block controlling the Clocks and PHY 53 * - A custom HDMI PHY in order convert video to TMDS signal 54 * 55 * .. code:: 56 * 57 * ___________________________________ 58 * | HDMI TOP |<= HPD 59 * |___________________________________| 60 * | | | 61 * | Synopsys HDMI | HDMI PHY |=> TMDS 62 * | Controller |________________| 63 * |___________________________________|<=> DDC 64 * 65 * 66 * The HDMI TOP block only supports HPD sensing. 67 * The Synopsys HDMI Controller interrupt is routed 68 * through the TOP Block interrupt. 69 * Communication to the TOP Block and the Synopsys 70 * HDMI Controller is done a pair of addr+read/write 71 * registers. 72 * The HDMI PHY is configured by registers in the 73 * HHI register block. 74 * 75 * Pixel data arrives in 4:4:4 format from the VENC 76 * block and the VPU HDMI mux selects either the ENCI 77 * encoder for the 576i or 480i formats or the ENCP 78 * encoder for all the other formats including 79 * interlaced HD formats. 80 * The VENC uses a DVI encoder on top of the ENCI 81 * or ENCP encoders to generate DVI timings for the 82 * HDMI controller. 83 * 84 * GXBB, GXL and GXM embeds the Synopsys DesignWare 85 * HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF 86 * audio source interfaces. 87 * 88 * We handle the following features : 89 * 90 * - HPD Rise & Fall interrupt 91 * - HDMI Controller Interrupt 92 * - HDMI PHY Init for 480i to 1080p60 93 * - VENC & HDMI Clock setup for 480i to 1080p60 94 * - VENC Mode setup for 480i to 1080p60 95 * 96 * What is missing : 97 * 98 * - PHY, Clock and Mode setup for 2k && 4k modes 99 * - SDDC Scrambling mode for HDMI 2.0a 100 * - HDCP Setup 101 * - CEC Management 102 */ 103 104 /* TOP Block Communication Channel */ 105 #define HDMITX_TOP_ADDR_REG 0x0 106 #define HDMITX_TOP_DATA_REG 0x4 107 #define HDMITX_TOP_CTRL_REG 0x8 108 109 /* Controller Communication Channel */ 110 #define HDMITX_DWC_ADDR_REG 0x10 111 #define HDMITX_DWC_DATA_REG 0x14 112 #define HDMITX_DWC_CTRL_REG 0x18 113 114 /* HHI Registers */ 115 #define HHI_MEM_PD_REG0 0x100 /* 0x40 */ 116 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ 117 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */ 118 #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */ 119 #define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */ 120 #define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */ 121 122 static DEFINE_SPINLOCK(reg_lock); 123 124 enum meson_venc_source { 125 MESON_VENC_SOURCE_NONE = 0, 126 MESON_VENC_SOURCE_ENCI = 1, 127 MESON_VENC_SOURCE_ENCP = 2, 128 }; 129 130 struct meson_dw_hdmi { 131 struct drm_encoder encoder; 132 struct dw_hdmi_plat_data dw_plat_data; 133 struct meson_drm *priv; 134 struct device *dev; 135 void __iomem *hdmitx; 136 struct reset_control *hdmitx_apb; 137 struct reset_control *hdmitx_ctrl; 138 struct reset_control *hdmitx_phy; 139 struct clk *hdmi_pclk; 140 struct clk *venci_clk; 141 struct regulator *hdmi_supply; 142 u32 irq_stat; 143 struct dw_hdmi *hdmi; 144 }; 145 #define encoder_to_meson_dw_hdmi(x) \ 146 container_of(x, struct meson_dw_hdmi, encoder) 147 148 static inline int dw_hdmi_is_compatible(struct meson_dw_hdmi *dw_hdmi, 149 const char *compat) 150 { 151 return of_device_is_compatible(dw_hdmi->dev->of_node, compat); 152 } 153 154 /* PHY (via TOP bridge) and Controller dedicated register interface */ 155 156 static unsigned int dw_hdmi_top_read(struct meson_dw_hdmi *dw_hdmi, 157 unsigned int addr) 158 { 159 unsigned long flags; 160 unsigned int data; 161 162 spin_lock_irqsave(®_lock, flags); 163 164 /* ADDR must be written twice */ 165 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); 166 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); 167 168 /* Read needs a second DATA read */ 169 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); 170 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); 171 172 spin_unlock_irqrestore(®_lock, flags); 173 174 return data; 175 } 176 177 static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi, 178 unsigned int addr, unsigned int data) 179 { 180 unsigned long flags; 181 182 spin_lock_irqsave(®_lock, flags); 183 184 /* ADDR must be written twice */ 185 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); 186 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); 187 188 /* Write needs single DATA write */ 189 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); 190 191 spin_unlock_irqrestore(®_lock, flags); 192 } 193 194 /* Helper to change specific bits in PHY registers */ 195 static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi *dw_hdmi, 196 unsigned int addr, 197 unsigned int mask, 198 unsigned int val) 199 { 200 unsigned int data = dw_hdmi_top_read(dw_hdmi, addr); 201 202 data &= ~mask; 203 data |= val; 204 205 dw_hdmi_top_write(dw_hdmi, addr, data); 206 } 207 208 static unsigned int dw_hdmi_dwc_read(struct meson_dw_hdmi *dw_hdmi, 209 unsigned int addr) 210 { 211 unsigned long flags; 212 unsigned int data; 213 214 spin_lock_irqsave(®_lock, flags); 215 216 /* ADDR must be written twice */ 217 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); 218 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); 219 220 /* Read needs a second DATA read */ 221 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); 222 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); 223 224 spin_unlock_irqrestore(®_lock, flags); 225 226 return data; 227 } 228 229 static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi, 230 unsigned int addr, unsigned int data) 231 { 232 unsigned long flags; 233 234 spin_lock_irqsave(®_lock, flags); 235 236 /* ADDR must be written twice */ 237 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); 238 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); 239 240 /* Write needs single DATA write */ 241 writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); 242 243 spin_unlock_irqrestore(®_lock, flags); 244 } 245 246 /* Helper to change specific bits in controller registers */ 247 static inline void dw_hdmi_dwc_write_bits(struct meson_dw_hdmi *dw_hdmi, 248 unsigned int addr, 249 unsigned int mask, 250 unsigned int val) 251 { 252 unsigned int data = dw_hdmi_dwc_read(dw_hdmi, addr); 253 254 data &= ~mask; 255 data |= val; 256 257 dw_hdmi_dwc_write(dw_hdmi, addr, data); 258 } 259 260 /* Bridge */ 261 262 /* Setup PHY bandwidth modes */ 263 static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi, 264 struct drm_display_mode *mode) 265 { 266 struct meson_drm *priv = dw_hdmi->priv; 267 unsigned int pixel_clock = mode->clock; 268 269 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || 270 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) { 271 if (pixel_clock >= 371250) { 272 /* 5.94Gbps, 3.7125Gbps */ 273 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x333d3282); 274 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b); 275 } else if (pixel_clock >= 297000) { 276 /* 2.97Gbps */ 277 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382); 278 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b); 279 } else if (pixel_clock >= 148500) { 280 /* 1.485Gbps */ 281 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303362); 282 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2016315b); 283 } else { 284 /* 742.5Mbps, and below */ 285 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33604142); 286 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x0016315b); 287 } 288 } else if (dw_hdmi_is_compatible(dw_hdmi, 289 "amlogic,meson-gxbb-dw-hdmi")) { 290 if (pixel_clock >= 371250) { 291 /* 5.94Gbps, 3.7125Gbps */ 292 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33353245); 293 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2100115b); 294 } else if (pixel_clock >= 297000) { 295 /* 2.97Gbps */ 296 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33634283); 297 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0xb000115b); 298 } else { 299 /* 1.485Gbps, and below */ 300 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33632122); 301 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2000115b); 302 } 303 } 304 } 305 306 static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi) 307 { 308 struct meson_drm *priv = dw_hdmi->priv; 309 310 /* Enable and software reset */ 311 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); 312 313 mdelay(2); 314 315 /* Enable and unreset */ 316 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); 317 318 mdelay(2); 319 } 320 321 static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, 322 struct drm_display_mode *mode) 323 { 324 struct meson_drm *priv = dw_hdmi->priv; 325 int vic = drm_match_cea_mode(mode); 326 unsigned int vclk_freq; 327 unsigned int venc_freq; 328 unsigned int hdmi_freq; 329 330 vclk_freq = mode->clock; 331 332 if (!vic) { 333 meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, vclk_freq, 334 vclk_freq, vclk_freq, false); 335 return; 336 } 337 338 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 339 vclk_freq *= 2; 340 341 venc_freq = vclk_freq; 342 hdmi_freq = vclk_freq; 343 344 if (meson_venc_hdmi_venc_repeat(vic)) 345 venc_freq *= 2; 346 347 vclk_freq = max(venc_freq, hdmi_freq); 348 349 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 350 venc_freq /= 2; 351 352 DRM_DEBUG_DRIVER("vclk:%d venc=%d hdmi=%d enci=%d\n", 353 vclk_freq, venc_freq, hdmi_freq, 354 priv->venc.hdmi_use_enci); 355 356 meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, vclk_freq, 357 venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); 358 } 359 360 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 361 struct drm_display_mode *mode) 362 { 363 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; 364 struct meson_drm *priv = dw_hdmi->priv; 365 unsigned int wr_clk = 366 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); 367 368 DRM_DEBUG_DRIVER("\"%s\"\n", mode->name); 369 370 /* Enable clocks */ 371 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); 372 373 /* Bring HDMITX MEM output of power down */ 374 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); 375 376 /* Bring out of reset */ 377 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0); 378 379 /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */ 380 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL, 381 0x3, 0x3); 382 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL, 383 0x3 << 4, 0x3 << 4); 384 385 /* Enable normal output to PHY */ 386 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); 387 388 /* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */ 389 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f); 390 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f); 391 392 /* Load TMDS pattern */ 393 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); 394 msleep(20); 395 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); 396 397 /* Setup PHY parameters */ 398 meson_hdmi_phy_setup_mode(dw_hdmi, mode); 399 400 /* Setup PHY */ 401 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 402 0xffff << 16, 0x0390 << 16); 403 404 /* BIT_INVERT */ 405 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || 406 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) 407 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 408 BIT(17), 0); 409 else 410 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 411 BIT(17), BIT(17)); 412 413 /* Disable clock, fifo, fifo_wr */ 414 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); 415 416 msleep(100); 417 418 /* Reset PHY 3 times in a row */ 419 meson_dw_hdmi_phy_reset(dw_hdmi); 420 meson_dw_hdmi_phy_reset(dw_hdmi); 421 meson_dw_hdmi_phy_reset(dw_hdmi); 422 423 /* Temporary Disable VENC video stream */ 424 if (priv->venc.hdmi_use_enci) 425 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 426 else 427 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 428 429 /* Temporary Disable HDMI video stream to HDMI-TX */ 430 writel_bits_relaxed(0x3, 0, 431 priv->io_base + _REG(VPU_HDMI_SETTING)); 432 writel_bits_relaxed(0xf << 8, 0, 433 priv->io_base + _REG(VPU_HDMI_SETTING)); 434 435 /* Re-Enable VENC video stream */ 436 if (priv->venc.hdmi_use_enci) 437 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 438 else 439 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); 440 441 /* Push back HDMI clock settings */ 442 writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), 443 priv->io_base + _REG(VPU_HDMI_SETTING)); 444 445 /* Enable and Select HDMI video source for HDMI-TX */ 446 if (priv->venc.hdmi_use_enci) 447 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, 448 priv->io_base + _REG(VPU_HDMI_SETTING)); 449 else 450 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, 451 priv->io_base + _REG(VPU_HDMI_SETTING)); 452 453 return 0; 454 } 455 456 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, 457 void *data) 458 { 459 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; 460 struct meson_drm *priv = dw_hdmi->priv; 461 462 DRM_DEBUG_DRIVER("\n"); 463 464 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); 465 } 466 467 static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi, 468 void *data) 469 { 470 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; 471 472 return !!dw_hdmi_top_read(dw_hdmi, HDMITX_TOP_STAT0) ? 473 connector_status_connected : connector_status_disconnected; 474 } 475 476 static void dw_hdmi_setup_hpd(struct dw_hdmi *hdmi, 477 void *data) 478 { 479 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; 480 481 /* Setup HPD Filter */ 482 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER, 483 (0xa << 12) | 0xa0); 484 485 /* Clear interrupts */ 486 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, 487 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL); 488 489 /* Unmask interrupts */ 490 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_INTR_MASKN, 491 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL, 492 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL); 493 } 494 495 static const struct dw_hdmi_phy_ops meson_dw_hdmi_phy_ops = { 496 .init = dw_hdmi_phy_init, 497 .disable = dw_hdmi_phy_disable, 498 .read_hpd = dw_hdmi_read_hpd, 499 .setup_hpd = dw_hdmi_setup_hpd, 500 }; 501 502 static irqreturn_t dw_hdmi_top_irq(int irq, void *dev_id) 503 { 504 struct meson_dw_hdmi *dw_hdmi = dev_id; 505 u32 stat; 506 507 stat = dw_hdmi_top_read(dw_hdmi, HDMITX_TOP_INTR_STAT); 508 dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat); 509 510 /* HPD Events, handle in the threaded interrupt handler */ 511 if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) { 512 dw_hdmi->irq_stat = stat; 513 return IRQ_WAKE_THREAD; 514 } 515 516 /* HDMI Controller Interrupt */ 517 if (stat & 1) 518 return IRQ_NONE; 519 520 /* TOFIX Handle HDCP Interrupts */ 521 522 return IRQ_HANDLED; 523 } 524 525 /* Threaded interrupt handler to manage HPD events */ 526 static irqreturn_t dw_hdmi_top_thread_irq(int irq, void *dev_id) 527 { 528 struct meson_dw_hdmi *dw_hdmi = dev_id; 529 u32 stat = dw_hdmi->irq_stat; 530 531 /* HPD Events */ 532 if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) { 533 bool hpd_connected = false; 534 535 if (stat & HDMITX_TOP_INTR_HPD_RISE) 536 hpd_connected = true; 537 538 dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected, 539 hpd_connected); 540 541 drm_helper_hpd_irq_event(dw_hdmi->encoder.dev); 542 } 543 544 return IRQ_HANDLED; 545 } 546 547 static enum drm_mode_status 548 dw_hdmi_mode_valid(struct drm_connector *connector, 549 const struct drm_display_mode *mode) 550 { 551 struct meson_drm *priv = connector->dev->dev_private; 552 unsigned int vclk_freq; 553 unsigned int venc_freq; 554 unsigned int hdmi_freq; 555 int vic = drm_match_cea_mode(mode); 556 enum drm_mode_status status; 557 558 DRM_DEBUG_DRIVER("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); 559 560 /* Check against non-VIC supported modes */ 561 if (!vic) { 562 status = meson_venc_hdmi_supported_mode(mode); 563 if (status != MODE_OK) 564 return status; 565 566 return meson_vclk_dmt_supported_freq(priv, mode->clock); 567 /* Check against supported VIC modes */ 568 } else if (!meson_venc_hdmi_supported_vic(vic)) 569 return MODE_BAD; 570 571 vclk_freq = mode->clock; 572 573 /* 480i/576i needs global pixel doubling */ 574 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 575 vclk_freq *= 2; 576 577 venc_freq = vclk_freq; 578 hdmi_freq = vclk_freq; 579 580 /* VENC double pixels for 1080i and 720p modes */ 581 if (meson_venc_hdmi_venc_repeat(vic)) 582 venc_freq *= 2; 583 584 vclk_freq = max(venc_freq, hdmi_freq); 585 586 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 587 venc_freq /= 2; 588 589 dev_dbg(connector->dev->dev, "%s: vclk:%d venc=%d hdmi=%d\n", __func__, 590 vclk_freq, venc_freq, hdmi_freq); 591 592 return meson_vclk_vic_supported_freq(vclk_freq); 593 } 594 595 /* Encoder */ 596 597 static void meson_venc_hdmi_encoder_destroy(struct drm_encoder *encoder) 598 { 599 drm_encoder_cleanup(encoder); 600 } 601 602 static const struct drm_encoder_funcs meson_venc_hdmi_encoder_funcs = { 603 .destroy = meson_venc_hdmi_encoder_destroy, 604 }; 605 606 static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 607 struct drm_crtc_state *crtc_state, 608 struct drm_connector_state *conn_state) 609 { 610 return 0; 611 } 612 613 static void meson_venc_hdmi_encoder_disable(struct drm_encoder *encoder) 614 { 615 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); 616 struct meson_drm *priv = dw_hdmi->priv; 617 618 DRM_DEBUG_DRIVER("\n"); 619 620 writel_bits_relaxed(0x3, 0, 621 priv->io_base + _REG(VPU_HDMI_SETTING)); 622 623 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 624 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 625 } 626 627 static void meson_venc_hdmi_encoder_enable(struct drm_encoder *encoder) 628 { 629 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); 630 struct meson_drm *priv = dw_hdmi->priv; 631 632 DRM_DEBUG_DRIVER("%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP"); 633 634 if (priv->venc.hdmi_use_enci) 635 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 636 else 637 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); 638 } 639 640 static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder, 641 struct drm_display_mode *mode, 642 struct drm_display_mode *adjusted_mode) 643 { 644 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); 645 struct meson_drm *priv = dw_hdmi->priv; 646 int vic = drm_match_cea_mode(mode); 647 648 DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode->name, vic); 649 650 /* VENC + VENC-DVI Mode setup */ 651 meson_venc_hdmi_mode_set(priv, vic, mode); 652 653 /* VCLK Set clock */ 654 dw_hdmi_set_vclk(dw_hdmi, mode); 655 656 /* Setup YUV444 to HDMI-TX, no 10bit diphering */ 657 writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); 658 } 659 660 static const struct drm_encoder_helper_funcs 661 meson_venc_hdmi_encoder_helper_funcs = { 662 .atomic_check = meson_venc_hdmi_encoder_atomic_check, 663 .disable = meson_venc_hdmi_encoder_disable, 664 .enable = meson_venc_hdmi_encoder_enable, 665 .mode_set = meson_venc_hdmi_encoder_mode_set, 666 }; 667 668 /* DW HDMI Regmap */ 669 670 static int meson_dw_hdmi_reg_read(void *context, unsigned int reg, 671 unsigned int *result) 672 { 673 *result = dw_hdmi_dwc_read(context, reg); 674 675 return 0; 676 677 } 678 679 static int meson_dw_hdmi_reg_write(void *context, unsigned int reg, 680 unsigned int val) 681 { 682 dw_hdmi_dwc_write(context, reg, val); 683 684 return 0; 685 } 686 687 static const struct regmap_config meson_dw_hdmi_regmap_config = { 688 .reg_bits = 32, 689 .val_bits = 8, 690 .reg_read = meson_dw_hdmi_reg_read, 691 .reg_write = meson_dw_hdmi_reg_write, 692 .max_register = 0x10000, 693 .fast_io = true, 694 }; 695 696 static bool meson_hdmi_connector_is_available(struct device *dev) 697 { 698 struct device_node *ep, *remote; 699 700 /* HDMI Connector is on the second port, first endpoint */ 701 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, 0); 702 if (!ep) 703 return false; 704 705 /* If the endpoint node exists, consider it enabled */ 706 remote = of_graph_get_remote_port(ep); 707 if (remote) { 708 of_node_put(ep); 709 return true; 710 } 711 712 of_node_put(ep); 713 of_node_put(remote); 714 715 return false; 716 } 717 718 static int meson_dw_hdmi_bind(struct device *dev, struct device *master, 719 void *data) 720 { 721 struct platform_device *pdev = to_platform_device(dev); 722 struct meson_dw_hdmi *meson_dw_hdmi; 723 struct drm_device *drm = data; 724 struct meson_drm *priv = drm->dev_private; 725 struct dw_hdmi_plat_data *dw_plat_data; 726 struct drm_encoder *encoder; 727 struct resource *res; 728 int irq; 729 int ret; 730 731 DRM_DEBUG_DRIVER("\n"); 732 733 if (!meson_hdmi_connector_is_available(dev)) { 734 dev_info(drm->dev, "HDMI Output connector not available\n"); 735 return -ENODEV; 736 } 737 738 meson_dw_hdmi = devm_kzalloc(dev, sizeof(*meson_dw_hdmi), 739 GFP_KERNEL); 740 if (!meson_dw_hdmi) 741 return -ENOMEM; 742 743 meson_dw_hdmi->priv = priv; 744 meson_dw_hdmi->dev = dev; 745 dw_plat_data = &meson_dw_hdmi->dw_plat_data; 746 encoder = &meson_dw_hdmi->encoder; 747 748 meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi"); 749 if (IS_ERR(meson_dw_hdmi->hdmi_supply)) { 750 if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER) 751 return -EPROBE_DEFER; 752 meson_dw_hdmi->hdmi_supply = NULL; 753 } else { 754 ret = regulator_enable(meson_dw_hdmi->hdmi_supply); 755 if (ret) 756 return ret; 757 } 758 759 meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev, 760 "hdmitx_apb"); 761 if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) { 762 dev_err(dev, "Failed to get hdmitx_apb reset\n"); 763 return PTR_ERR(meson_dw_hdmi->hdmitx_apb); 764 } 765 766 meson_dw_hdmi->hdmitx_ctrl = devm_reset_control_get_exclusive(dev, 767 "hdmitx"); 768 if (IS_ERR(meson_dw_hdmi->hdmitx_ctrl)) { 769 dev_err(dev, "Failed to get hdmitx reset\n"); 770 return PTR_ERR(meson_dw_hdmi->hdmitx_ctrl); 771 } 772 773 meson_dw_hdmi->hdmitx_phy = devm_reset_control_get_exclusive(dev, 774 "hdmitx_phy"); 775 if (IS_ERR(meson_dw_hdmi->hdmitx_phy)) { 776 dev_err(dev, "Failed to get hdmitx_phy reset\n"); 777 return PTR_ERR(meson_dw_hdmi->hdmitx_phy); 778 } 779 780 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 781 meson_dw_hdmi->hdmitx = devm_ioremap_resource(dev, res); 782 if (IS_ERR(meson_dw_hdmi->hdmitx)) 783 return PTR_ERR(meson_dw_hdmi->hdmitx); 784 785 meson_dw_hdmi->hdmi_pclk = devm_clk_get(dev, "isfr"); 786 if (IS_ERR(meson_dw_hdmi->hdmi_pclk)) { 787 dev_err(dev, "Unable to get HDMI pclk\n"); 788 return PTR_ERR(meson_dw_hdmi->hdmi_pclk); 789 } 790 clk_prepare_enable(meson_dw_hdmi->hdmi_pclk); 791 792 meson_dw_hdmi->venci_clk = devm_clk_get(dev, "venci"); 793 if (IS_ERR(meson_dw_hdmi->venci_clk)) { 794 dev_err(dev, "Unable to get venci clk\n"); 795 return PTR_ERR(meson_dw_hdmi->venci_clk); 796 } 797 clk_prepare_enable(meson_dw_hdmi->venci_clk); 798 799 dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi, 800 &meson_dw_hdmi_regmap_config); 801 if (IS_ERR(dw_plat_data->regm)) 802 return PTR_ERR(dw_plat_data->regm); 803 804 irq = platform_get_irq(pdev, 0); 805 if (irq < 0) { 806 dev_err(dev, "Failed to get hdmi top irq\n"); 807 return irq; 808 } 809 810 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_top_irq, 811 dw_hdmi_top_thread_irq, IRQF_SHARED, 812 "dw_hdmi_top_irq", meson_dw_hdmi); 813 if (ret) { 814 dev_err(dev, "Failed to request hdmi top irq\n"); 815 return ret; 816 } 817 818 /* Encoder */ 819 820 drm_encoder_helper_add(encoder, &meson_venc_hdmi_encoder_helper_funcs); 821 822 ret = drm_encoder_init(drm, encoder, &meson_venc_hdmi_encoder_funcs, 823 DRM_MODE_ENCODER_TMDS, "meson_hdmi"); 824 if (ret) { 825 dev_err(priv->dev, "Failed to init HDMI encoder\n"); 826 return ret; 827 } 828 829 encoder->possible_crtcs = BIT(0); 830 831 DRM_DEBUG_DRIVER("encoder initialized\n"); 832 833 /* Enable clocks */ 834 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); 835 836 /* Bring HDMITX MEM output of power down */ 837 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); 838 839 /* Reset HDMITX APB & TX & PHY */ 840 reset_control_reset(meson_dw_hdmi->hdmitx_apb); 841 reset_control_reset(meson_dw_hdmi->hdmitx_ctrl); 842 reset_control_reset(meson_dw_hdmi->hdmitx_phy); 843 844 /* Enable APB3 fail on error */ 845 writel_bits_relaxed(BIT(15), BIT(15), 846 meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG); 847 writel_bits_relaxed(BIT(15), BIT(15), 848 meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG); 849 850 /* Bring out of reset */ 851 dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_SW_RESET, 0); 852 853 msleep(20); 854 855 dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_CLK_CNTL, 0xff); 856 857 /* Enable HDMI-TX Interrupt */ 858 dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, 859 HDMITX_TOP_INTR_CORE); 860 861 dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN, 862 HDMITX_TOP_INTR_CORE); 863 864 /* Bridge / Connector */ 865 866 dw_plat_data->mode_valid = dw_hdmi_mode_valid; 867 dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops; 868 dw_plat_data->phy_name = "meson_dw_hdmi_phy"; 869 dw_plat_data->phy_data = meson_dw_hdmi; 870 dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24; 871 dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; 872 873 platform_set_drvdata(pdev, meson_dw_hdmi); 874 875 meson_dw_hdmi->hdmi = dw_hdmi_bind(pdev, encoder, 876 &meson_dw_hdmi->dw_plat_data); 877 if (IS_ERR(meson_dw_hdmi->hdmi)) 878 return PTR_ERR(meson_dw_hdmi->hdmi); 879 880 DRM_DEBUG_DRIVER("HDMI controller initialized\n"); 881 882 return 0; 883 } 884 885 static void meson_dw_hdmi_unbind(struct device *dev, struct device *master, 886 void *data) 887 { 888 struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev); 889 890 dw_hdmi_unbind(meson_dw_hdmi->hdmi); 891 } 892 893 static const struct component_ops meson_dw_hdmi_ops = { 894 .bind = meson_dw_hdmi_bind, 895 .unbind = meson_dw_hdmi_unbind, 896 }; 897 898 static int meson_dw_hdmi_probe(struct platform_device *pdev) 899 { 900 return component_add(&pdev->dev, &meson_dw_hdmi_ops); 901 } 902 903 static int meson_dw_hdmi_remove(struct platform_device *pdev) 904 { 905 component_del(&pdev->dev, &meson_dw_hdmi_ops); 906 907 return 0; 908 } 909 910 static const struct of_device_id meson_dw_hdmi_of_table[] = { 911 { .compatible = "amlogic,meson-gxbb-dw-hdmi" }, 912 { .compatible = "amlogic,meson-gxl-dw-hdmi" }, 913 { .compatible = "amlogic,meson-gxm-dw-hdmi" }, 914 { } 915 }; 916 MODULE_DEVICE_TABLE(of, meson_dw_hdmi_of_table); 917 918 static struct platform_driver meson_dw_hdmi_platform_driver = { 919 .probe = meson_dw_hdmi_probe, 920 .remove = meson_dw_hdmi_remove, 921 .driver = { 922 .name = DRIVER_NAME, 923 .of_match_table = meson_dw_hdmi_of_table, 924 }, 925 }; 926 module_platform_driver(meson_dw_hdmi_platform_driver); 927 928 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 929 MODULE_DESCRIPTION(DRIVER_DESC); 930 MODULE_LICENSE("GPL"); 931