1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7 #ifndef __MESON_DRV_H 8 #define __MESON_DRV_H 9 10 #include <linux/device.h> 11 #include <linux/of.h> 12 #include <linux/regmap.h> 13 14 struct drm_crtc; 15 struct drm_device; 16 struct drm_plane; 17 struct meson_drm; 18 19 struct meson_drm { 20 struct device *dev; 21 void __iomem *io_base; 22 struct regmap *hhi; 23 int vsync_irq; 24 25 struct meson_canvas *canvas; 26 u8 canvas_id_osd1; 27 u8 canvas_id_vd1_0; 28 u8 canvas_id_vd1_1; 29 u8 canvas_id_vd1_2; 30 31 struct drm_device *drm; 32 struct drm_crtc *crtc; 33 struct drm_plane *primary_plane; 34 struct drm_plane *overlay_plane; 35 36 /* Components Data */ 37 struct { 38 bool osd1_enabled; 39 bool osd1_interlace; 40 bool osd1_commit; 41 uint32_t osd1_ctrl_stat; 42 uint32_t osd1_blk0_cfg[5]; 43 uint32_t osd1_addr; 44 uint32_t osd1_stride; 45 uint32_t osd1_height; 46 uint32_t osd_sc_ctrl0; 47 uint32_t osd_sc_i_wh_m1; 48 uint32_t osd_sc_o_h_start_end; 49 uint32_t osd_sc_o_v_start_end; 50 uint32_t osd_sc_v_ini_phase; 51 uint32_t osd_sc_v_phase_step; 52 uint32_t osd_sc_h_ini_phase; 53 uint32_t osd_sc_h_phase_step; 54 uint32_t osd_sc_h_ctrl0; 55 uint32_t osd_sc_v_ctrl0; 56 uint32_t osd_blend_din0_scope_h; 57 uint32_t osd_blend_din0_scope_v; 58 uint32_t osb_blend0_size; 59 uint32_t osb_blend1_size; 60 61 bool vd1_enabled; 62 bool vd1_commit; 63 unsigned int vd1_planes; 64 uint32_t vd1_if0_gen_reg; 65 uint32_t vd1_if0_luma_x0; 66 uint32_t vd1_if0_luma_y0; 67 uint32_t vd1_if0_chroma_x0; 68 uint32_t vd1_if0_chroma_y0; 69 uint32_t vd1_if0_repeat_loop; 70 uint32_t vd1_if0_luma0_rpt_pat; 71 uint32_t vd1_if0_chroma0_rpt_pat; 72 uint32_t vd1_range_map_y; 73 uint32_t vd1_range_map_cb; 74 uint32_t vd1_range_map_cr; 75 uint32_t viu_vd1_fmt_w; 76 uint32_t vd1_if0_canvas0; 77 uint32_t vd1_if0_gen_reg2; 78 uint32_t viu_vd1_fmt_ctrl; 79 uint32_t vd1_addr0; 80 uint32_t vd1_addr1; 81 uint32_t vd1_addr2; 82 uint32_t vd1_stride0; 83 uint32_t vd1_stride1; 84 uint32_t vd1_stride2; 85 uint32_t vd1_height0; 86 uint32_t vd1_height1; 87 uint32_t vd1_height2; 88 uint32_t vpp_pic_in_height; 89 uint32_t vpp_postblend_vd1_h_start_end; 90 uint32_t vpp_postblend_vd1_v_start_end; 91 uint32_t vpp_hsc_region12_startp; 92 uint32_t vpp_hsc_region34_startp; 93 uint32_t vpp_hsc_region4_endp; 94 uint32_t vpp_hsc_start_phase_step; 95 uint32_t vpp_hsc_region1_phase_slope; 96 uint32_t vpp_hsc_region3_phase_slope; 97 uint32_t vpp_line_in_length; 98 uint32_t vpp_preblend_h_size; 99 uint32_t vpp_vsc_region12_startp; 100 uint32_t vpp_vsc_region34_startp; 101 uint32_t vpp_vsc_region4_endp; 102 uint32_t vpp_vsc_start_phase_step; 103 uint32_t vpp_vsc_ini_phase; 104 uint32_t vpp_vsc_phase_ctrl; 105 uint32_t vpp_hsc_phase_ctrl; 106 uint32_t vpp_blend_vd2_h_start_end; 107 uint32_t vpp_blend_vd2_v_start_end; 108 } viu; 109 110 struct { 111 unsigned int current_mode; 112 bool hdmi_repeat; 113 bool venc_repeat; 114 bool hdmi_use_enci; 115 } venc; 116 }; 117 118 static inline int meson_vpu_is_compatible(struct meson_drm *priv, 119 const char *compat) 120 { 121 return of_device_is_compatible(priv->dev->of_node, compat); 122 } 123 124 #endif /* __MESON_DRV_H */ 125