1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7 #ifndef __MESON_DRV_H 8 #define __MESON_DRV_H 9 10 #include <linux/device.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/regmap.h> 14 15 struct drm_crtc; 16 struct drm_device; 17 struct drm_plane; 18 struct meson_drm; 19 struct meson_afbcd_ops; 20 21 enum vpu_compatible { 22 VPU_COMPATIBLE_GXBB = 0, 23 VPU_COMPATIBLE_GXL = 1, 24 VPU_COMPATIBLE_GXM = 2, 25 VPU_COMPATIBLE_G12A = 3, 26 }; 27 28 enum { 29 MESON_ENC_CVBS = 0, 30 MESON_ENC_HDMI, 31 MESON_ENC_DSI, 32 MESON_ENC_LAST, 33 }; 34 35 struct meson_drm_match_data { 36 enum vpu_compatible compat; 37 struct meson_afbcd_ops *afbcd_ops; 38 }; 39 40 struct meson_drm_soc_limits { 41 unsigned int max_hdmi_phy_freq; 42 }; 43 44 struct meson_drm { 45 struct device *dev; 46 enum vpu_compatible compat; 47 void __iomem *io_base; 48 struct regmap *hhi; 49 int vsync_irq; 50 51 struct meson_canvas *canvas; 52 u8 canvas_id_osd1; 53 u8 canvas_id_vd1_0; 54 u8 canvas_id_vd1_1; 55 u8 canvas_id_vd1_2; 56 57 struct drm_device *drm; 58 struct drm_crtc *crtc; 59 struct drm_plane *primary_plane; 60 struct drm_plane *overlay_plane; 61 void *encoders[MESON_ENC_LAST]; 62 63 const struct meson_drm_soc_limits *limits; 64 65 /* Components Data */ 66 struct { 67 bool osd1_enabled; 68 bool osd1_interlace; 69 bool osd1_commit; 70 bool osd1_afbcd; 71 uint32_t osd1_ctrl_stat; 72 uint32_t osd1_ctrl_stat2; 73 uint32_t osd1_blk0_cfg[5]; 74 uint32_t osd1_blk1_cfg4; 75 uint32_t osd1_blk2_cfg4; 76 uint32_t osd1_addr; 77 uint32_t osd1_stride; 78 uint32_t osd1_height; 79 uint32_t osd1_width; 80 uint32_t osd_sc_ctrl0; 81 uint32_t osd_sc_i_wh_m1; 82 uint32_t osd_sc_o_h_start_end; 83 uint32_t osd_sc_o_v_start_end; 84 uint32_t osd_sc_v_ini_phase; 85 uint32_t osd_sc_v_phase_step; 86 uint32_t osd_sc_h_ini_phase; 87 uint32_t osd_sc_h_phase_step; 88 uint32_t osd_sc_h_ctrl0; 89 uint32_t osd_sc_v_ctrl0; 90 uint32_t osd_blend_din0_scope_h; 91 uint32_t osd_blend_din0_scope_v; 92 uint32_t osb_blend0_size; 93 uint32_t osb_blend1_size; 94 95 bool vd1_enabled; 96 bool vd1_commit; 97 bool vd1_afbc; 98 unsigned int vd1_planes; 99 uint32_t vd1_if0_gen_reg; 100 uint32_t vd1_if0_luma_x0; 101 uint32_t vd1_if0_luma_y0; 102 uint32_t vd1_if0_chroma_x0; 103 uint32_t vd1_if0_chroma_y0; 104 uint32_t vd1_if0_repeat_loop; 105 uint32_t vd1_if0_luma0_rpt_pat; 106 uint32_t vd1_if0_chroma0_rpt_pat; 107 uint32_t vd1_range_map_y; 108 uint32_t vd1_range_map_cb; 109 uint32_t vd1_range_map_cr; 110 uint32_t viu_vd1_fmt_w; 111 uint32_t vd1_if0_canvas0; 112 uint32_t vd1_if0_gen_reg2; 113 uint32_t viu_vd1_fmt_ctrl; 114 uint32_t vd1_addr0; 115 uint32_t vd1_addr1; 116 uint32_t vd1_addr2; 117 uint32_t vd1_stride0; 118 uint32_t vd1_stride1; 119 uint32_t vd1_stride2; 120 uint32_t vd1_height0; 121 uint32_t vd1_height1; 122 uint32_t vd1_height2; 123 uint32_t vd1_afbc_mode; 124 uint32_t vd1_afbc_en; 125 uint32_t vd1_afbc_head_addr; 126 uint32_t vd1_afbc_body_addr; 127 uint32_t vd1_afbc_conv_ctrl; 128 uint32_t vd1_afbc_dec_def_color; 129 uint32_t vd1_afbc_vd_cfmt_ctrl; 130 uint32_t vd1_afbc_vd_cfmt_w; 131 uint32_t vd1_afbc_vd_cfmt_h; 132 uint32_t vd1_afbc_mif_hor_scope; 133 uint32_t vd1_afbc_mif_ver_scope; 134 uint32_t vd1_afbc_size_out; 135 uint32_t vd1_afbc_pixel_hor_scope; 136 uint32_t vd1_afbc_pixel_ver_scope; 137 uint32_t vd1_afbc_size_in; 138 uint32_t vpp_pic_in_height; 139 uint32_t vpp_postblend_vd1_h_start_end; 140 uint32_t vpp_postblend_vd1_v_start_end; 141 uint32_t vpp_hsc_region12_startp; 142 uint32_t vpp_hsc_region34_startp; 143 uint32_t vpp_hsc_region4_endp; 144 uint32_t vpp_hsc_start_phase_step; 145 uint32_t vpp_hsc_region1_phase_slope; 146 uint32_t vpp_hsc_region3_phase_slope; 147 uint32_t vpp_line_in_length; 148 uint32_t vpp_preblend_h_size; 149 uint32_t vpp_vsc_region12_startp; 150 uint32_t vpp_vsc_region34_startp; 151 uint32_t vpp_vsc_region4_endp; 152 uint32_t vpp_vsc_start_phase_step; 153 uint32_t vpp_vsc_ini_phase; 154 uint32_t vpp_vsc_phase_ctrl; 155 uint32_t vpp_hsc_phase_ctrl; 156 uint32_t vpp_blend_vd2_h_start_end; 157 uint32_t vpp_blend_vd2_v_start_end; 158 } viu; 159 160 struct { 161 unsigned int current_mode; 162 bool hdmi_repeat; 163 bool venc_repeat; 164 bool hdmi_use_enci; 165 } venc; 166 167 struct { 168 dma_addr_t addr_dma; 169 uint32_t *addr; 170 unsigned int offset; 171 } rdma; 172 173 struct { 174 struct meson_afbcd_ops *ops; 175 u64 modifier; 176 u32 format; 177 } afbcd; 178 }; 179 180 static inline int meson_vpu_is_compatible(struct meson_drm *priv, 181 enum vpu_compatible family) 182 { 183 return priv->compat == family; 184 } 185 186 #endif /* __MESON_DRV_H */ 187