1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of the 8 * License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef __MESON_DRV_H 20 #define __MESON_DRV_H 21 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/of.h> 25 #include <linux/soc/amlogic/meson-canvas.h> 26 #include <drm/drmP.h> 27 28 struct meson_drm { 29 struct device *dev; 30 void __iomem *io_base; 31 struct regmap *hhi; 32 struct regmap *dmc; 33 int vsync_irq; 34 35 struct meson_canvas *canvas; 36 u8 canvas_id_osd1; 37 u8 canvas_id_vd1_0; 38 u8 canvas_id_vd1_1; 39 u8 canvas_id_vd1_2; 40 41 struct drm_device *drm; 42 struct drm_crtc *crtc; 43 struct drm_plane *primary_plane; 44 struct drm_plane *overlay_plane; 45 46 /* Components Data */ 47 struct { 48 bool osd1_enabled; 49 bool osd1_interlace; 50 bool osd1_commit; 51 uint32_t osd1_ctrl_stat; 52 uint32_t osd1_blk0_cfg[5]; 53 uint32_t osd1_addr; 54 uint32_t osd1_stride; 55 uint32_t osd1_height; 56 uint32_t osd_sc_ctrl0; 57 uint32_t osd_sc_i_wh_m1; 58 uint32_t osd_sc_o_h_start_end; 59 uint32_t osd_sc_o_v_start_end; 60 uint32_t osd_sc_v_ini_phase; 61 uint32_t osd_sc_v_phase_step; 62 uint32_t osd_sc_h_ini_phase; 63 uint32_t osd_sc_h_phase_step; 64 uint32_t osd_sc_h_ctrl0; 65 uint32_t osd_sc_v_ctrl0; 66 67 bool vd1_enabled; 68 bool vd1_commit; 69 unsigned int vd1_planes; 70 uint32_t vd1_if0_gen_reg; 71 uint32_t vd1_if0_luma_x0; 72 uint32_t vd1_if0_luma_y0; 73 uint32_t vd1_if0_chroma_x0; 74 uint32_t vd1_if0_chroma_y0; 75 uint32_t vd1_if0_repeat_loop; 76 uint32_t vd1_if0_luma0_rpt_pat; 77 uint32_t vd1_if0_chroma0_rpt_pat; 78 uint32_t vd1_range_map_y; 79 uint32_t vd1_range_map_cb; 80 uint32_t vd1_range_map_cr; 81 uint32_t viu_vd1_fmt_w; 82 uint32_t vd1_if0_canvas0; 83 uint32_t vd1_if0_gen_reg2; 84 uint32_t viu_vd1_fmt_ctrl; 85 uint32_t vd1_addr0; 86 uint32_t vd1_addr1; 87 uint32_t vd1_addr2; 88 uint32_t vd1_stride0; 89 uint32_t vd1_stride1; 90 uint32_t vd1_stride2; 91 uint32_t vd1_height0; 92 uint32_t vd1_height1; 93 uint32_t vd1_height2; 94 uint32_t vpp_pic_in_height; 95 uint32_t vpp_postblend_vd1_h_start_end; 96 uint32_t vpp_postblend_vd1_v_start_end; 97 uint32_t vpp_hsc_region12_startp; 98 uint32_t vpp_hsc_region34_startp; 99 uint32_t vpp_hsc_region4_endp; 100 uint32_t vpp_hsc_start_phase_step; 101 uint32_t vpp_hsc_region1_phase_slope; 102 uint32_t vpp_hsc_region3_phase_slope; 103 uint32_t vpp_line_in_length; 104 uint32_t vpp_preblend_h_size; 105 uint32_t vpp_vsc_region12_startp; 106 uint32_t vpp_vsc_region34_startp; 107 uint32_t vpp_vsc_region4_endp; 108 uint32_t vpp_vsc_start_phase_step; 109 uint32_t vpp_vsc_ini_phase; 110 uint32_t vpp_vsc_phase_ctrl; 111 uint32_t vpp_hsc_phase_ctrl; 112 uint32_t vpp_blend_vd2_h_start_end; 113 uint32_t vpp_blend_vd2_v_start_end; 114 } viu; 115 116 struct { 117 unsigned int current_mode; 118 bool hdmi_repeat; 119 bool venc_repeat; 120 bool hdmi_use_enci; 121 } venc; 122 }; 123 124 static inline int meson_vpu_is_compatible(struct meson_drm *priv, 125 const char *compat) 126 { 127 return of_device_is_compatible(priv->dev->of_node, compat); 128 } 129 130 #endif /* __MESON_DRV_H */ 131