1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * Copyright (C) 2014 Endless Mobile 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of the 10 * License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Written by: 21 * Jasper St. Pierre <jstpierre@mecheye.net> 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/platform_device.h> 28 #include <drm/drmP.h> 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_flip_work.h> 32 #include <drm/drm_crtc_helper.h> 33 34 #include "meson_crtc.h" 35 #include "meson_plane.h" 36 #include "meson_venc.h" 37 #include "meson_vpp.h" 38 #include "meson_viu.h" 39 #include "meson_registers.h" 40 41 /* CRTC definition */ 42 43 struct meson_crtc { 44 struct drm_crtc base; 45 struct drm_pending_vblank_event *event; 46 struct meson_drm *priv; 47 }; 48 #define to_meson_crtc(x) container_of(x, struct meson_crtc, base) 49 50 /* CRTC */ 51 52 static int meson_crtc_enable_vblank(struct drm_crtc *crtc) 53 { 54 struct meson_crtc *meson_crtc = to_meson_crtc(crtc); 55 struct meson_drm *priv = meson_crtc->priv; 56 57 meson_venc_enable_vsync(priv); 58 59 return 0; 60 } 61 62 static void meson_crtc_disable_vblank(struct drm_crtc *crtc) 63 { 64 struct meson_crtc *meson_crtc = to_meson_crtc(crtc); 65 struct meson_drm *priv = meson_crtc->priv; 66 67 meson_venc_disable_vsync(priv); 68 } 69 70 static const struct drm_crtc_funcs meson_crtc_funcs = { 71 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 72 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 73 .destroy = drm_crtc_cleanup, 74 .page_flip = drm_atomic_helper_page_flip, 75 .reset = drm_atomic_helper_crtc_reset, 76 .set_config = drm_atomic_helper_set_config, 77 .enable_vblank = meson_crtc_enable_vblank, 78 .disable_vblank = meson_crtc_disable_vblank, 79 80 }; 81 82 static void meson_crtc_enable(struct drm_crtc *crtc) 83 { 84 struct meson_crtc *meson_crtc = to_meson_crtc(crtc); 85 struct drm_crtc_state *crtc_state = crtc->state; 86 struct meson_drm *priv = meson_crtc->priv; 87 88 DRM_DEBUG_DRIVER("\n"); 89 90 if (!crtc_state) { 91 DRM_ERROR("Invalid crtc_state\n"); 92 return; 93 } 94 95 /* Enable VPP Postblend */ 96 writel(crtc_state->mode.hdisplay, 97 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); 98 99 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE, 100 priv->io_base + _REG(VPP_MISC)); 101 102 priv->viu.osd1_enabled = true; 103 } 104 105 static void meson_crtc_disable(struct drm_crtc *crtc) 106 { 107 struct meson_crtc *meson_crtc = to_meson_crtc(crtc); 108 struct meson_drm *priv = meson_crtc->priv; 109 110 priv->viu.osd1_enabled = false; 111 priv->viu.osd1_commit = false; 112 113 /* Disable VPP Postblend */ 114 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0, 115 priv->io_base + _REG(VPP_MISC)); 116 117 if (crtc->state->event && !crtc->state->active) { 118 spin_lock_irq(&crtc->dev->event_lock); 119 drm_crtc_send_vblank_event(crtc, crtc->state->event); 120 spin_unlock_irq(&crtc->dev->event_lock); 121 122 crtc->state->event = NULL; 123 } 124 } 125 126 static void meson_crtc_atomic_begin(struct drm_crtc *crtc, 127 struct drm_crtc_state *state) 128 { 129 struct meson_crtc *meson_crtc = to_meson_crtc(crtc); 130 unsigned long flags; 131 132 if (crtc->state->event) { 133 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 134 135 spin_lock_irqsave(&crtc->dev->event_lock, flags); 136 meson_crtc->event = crtc->state->event; 137 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 138 crtc->state->event = NULL; 139 } 140 } 141 142 static void meson_crtc_atomic_flush(struct drm_crtc *crtc, 143 struct drm_crtc_state *old_crtc_state) 144 { 145 struct meson_crtc *meson_crtc = to_meson_crtc(crtc); 146 struct meson_drm *priv = meson_crtc->priv; 147 148 priv->viu.osd1_commit = true; 149 } 150 151 static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = { 152 .enable = meson_crtc_enable, 153 .disable = meson_crtc_disable, 154 .atomic_begin = meson_crtc_atomic_begin, 155 .atomic_flush = meson_crtc_atomic_flush, 156 }; 157 158 void meson_crtc_irq(struct meson_drm *priv) 159 { 160 struct meson_crtc *meson_crtc = to_meson_crtc(priv->crtc); 161 unsigned long flags; 162 163 /* Update the OSD registers */ 164 if (priv->viu.osd1_enabled && priv->viu.osd1_commit) { 165 writel_relaxed(priv->viu.osd1_ctrl_stat, 166 priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); 167 writel_relaxed(priv->viu.osd1_blk0_cfg[0], 168 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); 169 writel_relaxed(priv->viu.osd1_blk0_cfg[1], 170 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1)); 171 writel_relaxed(priv->viu.osd1_blk0_cfg[2], 172 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2)); 173 writel_relaxed(priv->viu.osd1_blk0_cfg[3], 174 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3)); 175 writel_relaxed(priv->viu.osd1_blk0_cfg[4], 176 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4)); 177 178 /* If output is interlace, make use of the Scaler */ 179 if (priv->viu.osd1_interlace) { 180 struct drm_plane *plane = priv->primary_plane; 181 struct drm_plane_state *state = plane->state; 182 struct drm_rect dest = { 183 .x1 = state->crtc_x, 184 .y1 = state->crtc_y, 185 .x2 = state->crtc_x + state->crtc_w, 186 .y2 = state->crtc_y + state->crtc_h, 187 }; 188 189 meson_vpp_setup_interlace_vscaler_osd1(priv, &dest); 190 } else 191 meson_vpp_disable_interlace_vscaler_osd1(priv); 192 193 /* Enable OSD1 */ 194 writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND, 195 priv->io_base + _REG(VPP_MISC)); 196 197 priv->viu.osd1_commit = false; 198 } 199 200 drm_crtc_handle_vblank(priv->crtc); 201 202 spin_lock_irqsave(&priv->drm->event_lock, flags); 203 if (meson_crtc->event) { 204 drm_crtc_send_vblank_event(priv->crtc, meson_crtc->event); 205 drm_crtc_vblank_put(priv->crtc); 206 meson_crtc->event = NULL; 207 } 208 spin_unlock_irqrestore(&priv->drm->event_lock, flags); 209 } 210 211 int meson_crtc_create(struct meson_drm *priv) 212 { 213 struct meson_crtc *meson_crtc; 214 struct drm_crtc *crtc; 215 int ret; 216 217 meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc), 218 GFP_KERNEL); 219 if (!meson_crtc) 220 return -ENOMEM; 221 222 meson_crtc->priv = priv; 223 crtc = &meson_crtc->base; 224 ret = drm_crtc_init_with_planes(priv->drm, crtc, 225 priv->primary_plane, NULL, 226 &meson_crtc_funcs, "meson_crtc"); 227 if (ret) { 228 dev_err(priv->drm->dev, "Failed to init CRTC\n"); 229 return ret; 230 } 231 232 drm_crtc_helper_add(crtc, &meson_crtc_helper_funcs); 233 234 priv->crtc = crtc; 235 236 return 0; 237 } 238