1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/iopoll.h> 9 #include <linux/irq.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/phy/phy.h> 13 #include <linux/platform_device.h> 14 15 #include <video/mipi_display.h> 16 #include <video/videomode.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_bridge_connector.h> 21 #include <drm/drm_mipi_dsi.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_panel.h> 24 #include <drm/drm_print.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_simple_kms_helper.h> 27 28 #include "mtk_disp_drv.h" 29 #include "mtk_drm_ddp_comp.h" 30 31 #define DSI_START 0x00 32 33 #define DSI_INTEN 0x08 34 35 #define DSI_INTSTA 0x0c 36 #define LPRX_RD_RDY_INT_FLAG BIT(0) 37 #define CMD_DONE_INT_FLAG BIT(1) 38 #define TE_RDY_INT_FLAG BIT(2) 39 #define VM_DONE_INT_FLAG BIT(3) 40 #define EXT_TE_RDY_INT_FLAG BIT(4) 41 #define DSI_BUSY BIT(31) 42 43 #define DSI_CON_CTRL 0x10 44 #define DSI_RESET BIT(0) 45 #define DSI_EN BIT(1) 46 #define DPHY_RESET BIT(2) 47 48 #define DSI_MODE_CTRL 0x14 49 #define MODE (3) 50 #define CMD_MODE 0 51 #define SYNC_PULSE_MODE 1 52 #define SYNC_EVENT_MODE 2 53 #define BURST_MODE 3 54 #define FRM_MODE BIT(16) 55 #define MIX_MODE BIT(17) 56 57 #define DSI_TXRX_CTRL 0x18 58 #define VC_NUM BIT(1) 59 #define LANE_NUM (0xf << 2) 60 #define DIS_EOT BIT(6) 61 #define NULL_EN BIT(7) 62 #define TE_FREERUN BIT(8) 63 #define EXT_TE_EN BIT(9) 64 #define EXT_TE_EDGE BIT(10) 65 #define MAX_RTN_SIZE (0xf << 12) 66 #define HSTX_CKLP_EN BIT(16) 67 68 #define DSI_PSCTRL 0x1c 69 #define DSI_PS_WC 0x3fff 70 #define DSI_PS_SEL (3 << 16) 71 #define PACKED_PS_16BIT_RGB565 (0 << 16) 72 #define LOOSELY_PS_18BIT_RGB666 (1 << 16) 73 #define PACKED_PS_18BIT_RGB666 (2 << 16) 74 #define PACKED_PS_24BIT_RGB888 (3 << 16) 75 76 #define DSI_VSA_NL 0x20 77 #define DSI_VBP_NL 0x24 78 #define DSI_VFP_NL 0x28 79 #define DSI_VACT_NL 0x2C 80 #define DSI_SIZE_CON 0x38 81 #define DSI_HSA_WC 0x50 82 #define DSI_HBP_WC 0x54 83 #define DSI_HFP_WC 0x58 84 85 #define DSI_CMDQ_SIZE 0x60 86 #define CMDQ_SIZE 0x3f 87 88 #define DSI_HSTX_CKL_WC 0x64 89 90 #define DSI_RX_DATA0 0x74 91 #define DSI_RX_DATA1 0x78 92 #define DSI_RX_DATA2 0x7c 93 #define DSI_RX_DATA3 0x80 94 95 #define DSI_RACK 0x84 96 #define RACK BIT(0) 97 98 #define DSI_PHY_LCCON 0x104 99 #define LC_HS_TX_EN BIT(0) 100 #define LC_ULPM_EN BIT(1) 101 #define LC_WAKEUP_EN BIT(2) 102 103 #define DSI_PHY_LD0CON 0x108 104 #define LD0_HS_TX_EN BIT(0) 105 #define LD0_ULPM_EN BIT(1) 106 #define LD0_WAKEUP_EN BIT(2) 107 108 #define DSI_PHY_TIMECON0 0x110 109 #define LPX (0xff << 0) 110 #define HS_PREP (0xff << 8) 111 #define HS_ZERO (0xff << 16) 112 #define HS_TRAIL (0xff << 24) 113 114 #define DSI_PHY_TIMECON1 0x114 115 #define TA_GO (0xff << 0) 116 #define TA_SURE (0xff << 8) 117 #define TA_GET (0xff << 16) 118 #define DA_HS_EXIT (0xff << 24) 119 120 #define DSI_PHY_TIMECON2 0x118 121 #define CONT_DET (0xff << 0) 122 #define CLK_ZERO (0xff << 16) 123 #define CLK_TRAIL (0xff << 24) 124 125 #define DSI_PHY_TIMECON3 0x11c 126 #define CLK_HS_PREP (0xff << 0) 127 #define CLK_HS_POST (0xff << 8) 128 #define CLK_HS_EXIT (0xff << 16) 129 130 #define DSI_VM_CMD_CON 0x130 131 #define VM_CMD_EN BIT(0) 132 #define TS_VFP_EN BIT(5) 133 134 #define DSI_SHADOW_DEBUG 0x190U 135 #define FORCE_COMMIT BIT(0) 136 #define BYPASS_SHADOW BIT(1) 137 138 #define CONFIG (0xff << 0) 139 #define SHORT_PACKET 0 140 #define LONG_PACKET 2 141 #define BTA BIT(2) 142 #define DATA_ID (0xff << 8) 143 #define DATA_0 (0xff << 16) 144 #define DATA_1 (0xff << 24) 145 146 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) 147 148 #define MTK_DSI_HOST_IS_READ(type) \ 149 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ 150 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ 151 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ 152 (type == MIPI_DSI_DCS_READ)) 153 154 struct mtk_phy_timing { 155 u32 lpx; 156 u32 da_hs_prepare; 157 u32 da_hs_zero; 158 u32 da_hs_trail; 159 160 u32 ta_go; 161 u32 ta_sure; 162 u32 ta_get; 163 u32 da_hs_exit; 164 165 u32 clk_hs_zero; 166 u32 clk_hs_trail; 167 168 u32 clk_hs_prepare; 169 u32 clk_hs_post; 170 u32 clk_hs_exit; 171 }; 172 173 struct phy; 174 175 struct mtk_dsi_driver_data { 176 const u32 reg_cmdq_off; 177 bool has_shadow_ctl; 178 bool has_size_ctl; 179 }; 180 181 struct mtk_dsi { 182 struct device *dev; 183 struct mipi_dsi_host host; 184 struct drm_encoder encoder; 185 struct drm_bridge bridge; 186 struct drm_bridge *next_bridge; 187 struct drm_connector *connector; 188 struct phy *phy; 189 190 void __iomem *regs; 191 192 struct clk *engine_clk; 193 struct clk *digital_clk; 194 struct clk *hs_clk; 195 196 u32 data_rate; 197 198 unsigned long mode_flags; 199 enum mipi_dsi_pixel_format format; 200 unsigned int lanes; 201 struct videomode vm; 202 struct mtk_phy_timing phy_timing; 203 int refcount; 204 bool enabled; 205 u32 irq_data; 206 wait_queue_head_t irq_wait_queue; 207 const struct mtk_dsi_driver_data *driver_data; 208 }; 209 210 static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b) 211 { 212 return container_of(b, struct mtk_dsi, bridge); 213 } 214 215 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h) 216 { 217 return container_of(h, struct mtk_dsi, host); 218 } 219 220 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) 221 { 222 u32 temp = readl(dsi->regs + offset); 223 224 writel((temp & ~mask) | (data & mask), dsi->regs + offset); 225 } 226 227 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) 228 { 229 u32 timcon0, timcon1, timcon2, timcon3; 230 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); 231 struct mtk_phy_timing *timing = &dsi->phy_timing; 232 233 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; 234 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; 235 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - 236 timing->da_hs_prepare; 237 timing->da_hs_trail = timing->da_hs_prepare + 1; 238 239 timing->ta_go = 4 * timing->lpx - 2; 240 timing->ta_sure = timing->lpx + 2; 241 timing->ta_get = 4 * timing->lpx; 242 timing->da_hs_exit = 2 * timing->lpx + 1; 243 244 timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); 245 timing->clk_hs_post = timing->clk_hs_prepare + 8; 246 timing->clk_hs_trail = timing->clk_hs_prepare; 247 timing->clk_hs_zero = timing->clk_hs_trail * 4; 248 timing->clk_hs_exit = 2 * timing->clk_hs_trail; 249 250 timcon0 = timing->lpx | timing->da_hs_prepare << 8 | 251 timing->da_hs_zero << 16 | timing->da_hs_trail << 24; 252 timcon1 = timing->ta_go | timing->ta_sure << 8 | 253 timing->ta_get << 16 | timing->da_hs_exit << 24; 254 timcon2 = 1 << 8 | timing->clk_hs_zero << 16 | 255 timing->clk_hs_trail << 24; 256 timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 | 257 timing->clk_hs_exit << 16; 258 259 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); 260 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); 261 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); 262 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); 263 } 264 265 static void mtk_dsi_enable(struct mtk_dsi *dsi) 266 { 267 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN); 268 } 269 270 static void mtk_dsi_disable(struct mtk_dsi *dsi) 271 { 272 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0); 273 } 274 275 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi) 276 { 277 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET); 278 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0); 279 } 280 281 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi) 282 { 283 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET); 284 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0); 285 } 286 287 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) 288 { 289 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 290 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 291 } 292 293 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) 294 { 295 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 296 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN); 297 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0); 298 } 299 300 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) 301 { 302 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); 303 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 304 } 305 306 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) 307 { 308 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 309 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN); 310 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0); 311 } 312 313 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi) 314 { 315 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN; 316 } 317 318 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter) 319 { 320 if (enter && !mtk_dsi_clk_hs_state(dsi)) 321 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN); 322 else if (!enter && mtk_dsi_clk_hs_state(dsi)) 323 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 324 } 325 326 static void mtk_dsi_set_mode(struct mtk_dsi *dsi) 327 { 328 u32 vid_mode = CMD_MODE; 329 330 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 331 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 332 vid_mode = BURST_MODE; 333 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 334 vid_mode = SYNC_PULSE_MODE; 335 else 336 vid_mode = SYNC_EVENT_MODE; 337 } 338 339 writel(vid_mode, dsi->regs + DSI_MODE_CTRL); 340 } 341 342 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) 343 { 344 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); 345 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); 346 } 347 348 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) 349 { 350 struct videomode *vm = &dsi->vm; 351 u32 dsi_buf_bpp, ps_wc; 352 u32 ps_bpp_mode; 353 354 if (dsi->format == MIPI_DSI_FMT_RGB565) 355 dsi_buf_bpp = 2; 356 else 357 dsi_buf_bpp = 3; 358 359 ps_wc = vm->hactive * dsi_buf_bpp; 360 ps_bpp_mode = ps_wc; 361 362 switch (dsi->format) { 363 case MIPI_DSI_FMT_RGB888: 364 ps_bpp_mode |= PACKED_PS_24BIT_RGB888; 365 break; 366 case MIPI_DSI_FMT_RGB666: 367 ps_bpp_mode |= PACKED_PS_18BIT_RGB666; 368 break; 369 case MIPI_DSI_FMT_RGB666_PACKED: 370 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; 371 break; 372 case MIPI_DSI_FMT_RGB565: 373 ps_bpp_mode |= PACKED_PS_16BIT_RGB565; 374 break; 375 } 376 377 writel(vm->vactive, dsi->regs + DSI_VACT_NL); 378 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); 379 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); 380 } 381 382 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) 383 { 384 u32 tmp_reg; 385 386 switch (dsi->lanes) { 387 case 1: 388 tmp_reg = 1 << 2; 389 break; 390 case 2: 391 tmp_reg = 3 << 2; 392 break; 393 case 3: 394 tmp_reg = 7 << 2; 395 break; 396 case 4: 397 tmp_reg = 0xf << 2; 398 break; 399 default: 400 tmp_reg = 0xf << 2; 401 break; 402 } 403 404 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 405 tmp_reg |= HSTX_CKLP_EN; 406 407 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 408 tmp_reg |= DIS_EOT; 409 410 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); 411 } 412 413 static void mtk_dsi_ps_control(struct mtk_dsi *dsi) 414 { 415 u32 dsi_tmp_buf_bpp; 416 u32 tmp_reg; 417 418 switch (dsi->format) { 419 case MIPI_DSI_FMT_RGB888: 420 tmp_reg = PACKED_PS_24BIT_RGB888; 421 dsi_tmp_buf_bpp = 3; 422 break; 423 case MIPI_DSI_FMT_RGB666: 424 tmp_reg = LOOSELY_PS_18BIT_RGB666; 425 dsi_tmp_buf_bpp = 3; 426 break; 427 case MIPI_DSI_FMT_RGB666_PACKED: 428 tmp_reg = PACKED_PS_18BIT_RGB666; 429 dsi_tmp_buf_bpp = 3; 430 break; 431 case MIPI_DSI_FMT_RGB565: 432 tmp_reg = PACKED_PS_16BIT_RGB565; 433 dsi_tmp_buf_bpp = 2; 434 break; 435 default: 436 tmp_reg = PACKED_PS_24BIT_RGB888; 437 dsi_tmp_buf_bpp = 3; 438 break; 439 } 440 441 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; 442 writel(tmp_reg, dsi->regs + DSI_PSCTRL); 443 } 444 445 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) 446 { 447 u32 horizontal_sync_active_byte; 448 u32 horizontal_backporch_byte; 449 u32 horizontal_frontporch_byte; 450 u32 horizontal_front_back_byte; 451 u32 data_phy_cycles_byte; 452 u32 dsi_tmp_buf_bpp, data_phy_cycles; 453 u32 delta; 454 struct mtk_phy_timing *timing = &dsi->phy_timing; 455 456 struct videomode *vm = &dsi->vm; 457 458 if (dsi->format == MIPI_DSI_FMT_RGB565) 459 dsi_tmp_buf_bpp = 2; 460 else 461 dsi_tmp_buf_bpp = 3; 462 463 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL); 464 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL); 465 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); 466 writel(vm->vactive, dsi->regs + DSI_VACT_NL); 467 468 if (dsi->driver_data->has_size_ctl) 469 writel(vm->vactive << 16 | vm->hactive, 470 dsi->regs + DSI_SIZE_CON); 471 472 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); 473 474 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 475 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10; 476 else 477 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) * 478 dsi_tmp_buf_bpp - 10; 479 480 data_phy_cycles = timing->lpx + timing->da_hs_prepare + 481 timing->da_hs_zero + timing->da_hs_exit + 3; 482 483 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12; 484 delta += dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET ? 2 : 0; 485 486 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp; 487 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte; 488 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta; 489 490 if (horizontal_front_back_byte > data_phy_cycles_byte) { 491 horizontal_frontporch_byte -= data_phy_cycles_byte * 492 horizontal_frontporch_byte / 493 horizontal_front_back_byte; 494 495 horizontal_backporch_byte -= data_phy_cycles_byte * 496 horizontal_backporch_byte / 497 horizontal_front_back_byte; 498 } else { 499 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); 500 } 501 502 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); 503 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); 504 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); 505 506 mtk_dsi_ps_control(dsi); 507 } 508 509 static void mtk_dsi_start(struct mtk_dsi *dsi) 510 { 511 writel(0, dsi->regs + DSI_START); 512 writel(1, dsi->regs + DSI_START); 513 } 514 515 static void mtk_dsi_stop(struct mtk_dsi *dsi) 516 { 517 writel(0, dsi->regs + DSI_START); 518 } 519 520 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) 521 { 522 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); 523 } 524 525 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) 526 { 527 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 528 529 writel(inten, dsi->regs + DSI_INTEN); 530 } 531 532 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit) 533 { 534 dsi->irq_data |= irq_bit; 535 } 536 537 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit) 538 { 539 dsi->irq_data &= ~irq_bit; 540 } 541 542 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag, 543 unsigned int timeout) 544 { 545 s32 ret = 0; 546 unsigned long jiffies = msecs_to_jiffies(timeout); 547 548 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue, 549 dsi->irq_data & irq_flag, 550 jiffies); 551 if (ret == 0) { 552 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag); 553 554 mtk_dsi_enable(dsi); 555 mtk_dsi_reset_engine(dsi); 556 } 557 558 return ret; 559 } 560 561 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) 562 { 563 struct mtk_dsi *dsi = dev_id; 564 u32 status, tmp; 565 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 566 567 status = readl(dsi->regs + DSI_INTSTA) & flag; 568 569 if (status) { 570 do { 571 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); 572 tmp = readl(dsi->regs + DSI_INTSTA); 573 } while (tmp & DSI_BUSY); 574 575 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0); 576 mtk_dsi_irq_data_set(dsi, status); 577 wake_up_interruptible(&dsi->irq_wait_queue); 578 } 579 580 return IRQ_HANDLED; 581 } 582 583 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) 584 { 585 mtk_dsi_irq_data_clear(dsi, irq_flag); 586 mtk_dsi_set_cmd_mode(dsi); 587 588 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) { 589 DRM_ERROR("failed to switch cmd mode\n"); 590 return -ETIME; 591 } else { 592 return 0; 593 } 594 } 595 596 static int mtk_dsi_poweron(struct mtk_dsi *dsi) 597 { 598 struct device *dev = dsi->host.dev; 599 int ret; 600 u32 bit_per_pixel; 601 602 if (++dsi->refcount != 1) 603 return 0; 604 605 switch (dsi->format) { 606 case MIPI_DSI_FMT_RGB565: 607 bit_per_pixel = 16; 608 break; 609 case MIPI_DSI_FMT_RGB666_PACKED: 610 bit_per_pixel = 18; 611 break; 612 case MIPI_DSI_FMT_RGB666: 613 case MIPI_DSI_FMT_RGB888: 614 default: 615 bit_per_pixel = 24; 616 break; 617 } 618 619 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel, 620 dsi->lanes); 621 622 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate); 623 if (ret < 0) { 624 dev_err(dev, "Failed to set data rate: %d\n", ret); 625 goto err_refcount; 626 } 627 628 phy_power_on(dsi->phy); 629 630 ret = clk_prepare_enable(dsi->engine_clk); 631 if (ret < 0) { 632 dev_err(dev, "Failed to enable engine clock: %d\n", ret); 633 goto err_phy_power_off; 634 } 635 636 ret = clk_prepare_enable(dsi->digital_clk); 637 if (ret < 0) { 638 dev_err(dev, "Failed to enable digital clock: %d\n", ret); 639 goto err_disable_engine_clk; 640 } 641 642 mtk_dsi_enable(dsi); 643 644 if (dsi->driver_data->has_shadow_ctl) 645 writel(FORCE_COMMIT | BYPASS_SHADOW, 646 dsi->regs + DSI_SHADOW_DEBUG); 647 648 mtk_dsi_reset_engine(dsi); 649 mtk_dsi_phy_timconfig(dsi); 650 651 mtk_dsi_rxtx_control(dsi); 652 usleep_range(30, 100); 653 mtk_dsi_reset_dphy(dsi); 654 mtk_dsi_ps_control_vact(dsi); 655 mtk_dsi_set_vm_cmd(dsi); 656 mtk_dsi_config_vdo_timing(dsi); 657 mtk_dsi_set_interrupt_enable(dsi); 658 659 mtk_dsi_clk_ulp_mode_leave(dsi); 660 mtk_dsi_lane0_ulp_mode_leave(dsi); 661 mtk_dsi_clk_hs_mode(dsi, 0); 662 663 return 0; 664 err_disable_engine_clk: 665 clk_disable_unprepare(dsi->engine_clk); 666 err_phy_power_off: 667 phy_power_off(dsi->phy); 668 err_refcount: 669 dsi->refcount--; 670 return ret; 671 } 672 673 static void mtk_dsi_poweroff(struct mtk_dsi *dsi) 674 { 675 if (WARN_ON(dsi->refcount == 0)) 676 return; 677 678 if (--dsi->refcount != 0) 679 return; 680 681 /* 682 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since 683 * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(), 684 * which needs irq for vblank, and mtk_dsi_stop() will disable irq. 685 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(), 686 * after dsi is fully set. 687 */ 688 mtk_dsi_stop(dsi); 689 690 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); 691 mtk_dsi_reset_engine(dsi); 692 mtk_dsi_lane0_ulp_mode_enter(dsi); 693 mtk_dsi_clk_ulp_mode_enter(dsi); 694 695 mtk_dsi_disable(dsi); 696 697 clk_disable_unprepare(dsi->engine_clk); 698 clk_disable_unprepare(dsi->digital_clk); 699 700 phy_power_off(dsi->phy); 701 } 702 703 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) 704 { 705 int ret; 706 707 if (dsi->enabled) 708 return; 709 710 ret = mtk_dsi_poweron(dsi); 711 if (ret < 0) { 712 DRM_ERROR("failed to power on dsi\n"); 713 return; 714 } 715 716 mtk_dsi_set_mode(dsi); 717 mtk_dsi_clk_hs_mode(dsi, 1); 718 719 mtk_dsi_start(dsi); 720 721 dsi->enabled = true; 722 } 723 724 static void mtk_output_dsi_disable(struct mtk_dsi *dsi) 725 { 726 if (!dsi->enabled) 727 return; 728 729 mtk_dsi_poweroff(dsi); 730 731 dsi->enabled = false; 732 } 733 734 static int mtk_dsi_bridge_attach(struct drm_bridge *bridge, 735 enum drm_bridge_attach_flags flags) 736 { 737 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 738 739 /* Attach the panel or bridge to the dsi bridge */ 740 return drm_bridge_attach(bridge->encoder, dsi->next_bridge, 741 &dsi->bridge, flags); 742 } 743 744 static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge, 745 const struct drm_display_mode *mode, 746 const struct drm_display_mode *adjusted) 747 { 748 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 749 750 drm_display_mode_to_videomode(adjusted, &dsi->vm); 751 } 752 753 static void mtk_dsi_bridge_disable(struct drm_bridge *bridge) 754 { 755 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 756 757 mtk_output_dsi_disable(dsi); 758 } 759 760 static void mtk_dsi_bridge_enable(struct drm_bridge *bridge) 761 { 762 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 763 764 mtk_output_dsi_enable(dsi); 765 } 766 767 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = { 768 .attach = mtk_dsi_bridge_attach, 769 .disable = mtk_dsi_bridge_disable, 770 .enable = mtk_dsi_bridge_enable, 771 .mode_set = mtk_dsi_bridge_mode_set, 772 }; 773 774 void mtk_dsi_ddp_start(struct device *dev) 775 { 776 struct mtk_dsi *dsi = dev_get_drvdata(dev); 777 778 mtk_dsi_poweron(dsi); 779 } 780 781 void mtk_dsi_ddp_stop(struct device *dev) 782 { 783 struct mtk_dsi *dsi = dev_get_drvdata(dev); 784 785 mtk_dsi_poweroff(dsi); 786 } 787 788 static int mtk_dsi_host_attach(struct mipi_dsi_host *host, 789 struct mipi_dsi_device *device) 790 { 791 struct mtk_dsi *dsi = host_to_dsi(host); 792 793 dsi->lanes = device->lanes; 794 dsi->format = device->format; 795 dsi->mode_flags = device->mode_flags; 796 797 return 0; 798 } 799 800 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi) 801 { 802 int ret; 803 u32 val; 804 805 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY), 806 4, 2000000); 807 if (ret) { 808 DRM_WARN("polling dsi wait not busy timeout!\n"); 809 810 mtk_dsi_enable(dsi); 811 mtk_dsi_reset_engine(dsi); 812 } 813 } 814 815 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data) 816 { 817 switch (type) { 818 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 819 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 820 return 1; 821 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 822 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 823 return 2; 824 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 825 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 826 return read_data[1] + read_data[2] * 16; 827 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 828 DRM_INFO("type is 0x02, try again\n"); 829 break; 830 default: 831 DRM_INFO("type(0x%x) not recognized\n", type); 832 break; 833 } 834 835 return 0; 836 } 837 838 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) 839 { 840 const char *tx_buf = msg->tx_buf; 841 u8 config, cmdq_size, cmdq_off, type = msg->type; 842 u32 reg_val, cmdq_mask, i; 843 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off; 844 845 if (MTK_DSI_HOST_IS_READ(type)) 846 config = BTA; 847 else 848 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET; 849 850 if (msg->tx_len > 2) { 851 cmdq_size = 1 + (msg->tx_len + 3) / 4; 852 cmdq_off = 4; 853 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; 854 reg_val = (msg->tx_len << 16) | (type << 8) | config; 855 } else { 856 cmdq_size = 1; 857 cmdq_off = 2; 858 cmdq_mask = CONFIG | DATA_ID; 859 reg_val = (type << 8) | config; 860 } 861 862 for (i = 0; i < msg->tx_len; i++) 863 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U), 864 (0xffUL << (((i + cmdq_off) & 3U) * 8U)), 865 tx_buf[i] << (((i + cmdq_off) & 3U) * 8U)); 866 867 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val); 868 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); 869 } 870 871 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi, 872 const struct mipi_dsi_msg *msg, u8 flag) 873 { 874 mtk_dsi_wait_for_idle(dsi); 875 mtk_dsi_irq_data_clear(dsi, flag); 876 mtk_dsi_cmdq(dsi, msg); 877 mtk_dsi_start(dsi); 878 879 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000)) 880 return -ETIME; 881 else 882 return 0; 883 } 884 885 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host, 886 const struct mipi_dsi_msg *msg) 887 { 888 struct mtk_dsi *dsi = host_to_dsi(host); 889 u32 recv_cnt, i; 890 u8 read_data[16]; 891 void *src_addr; 892 u8 irq_flag = CMD_DONE_INT_FLAG; 893 894 if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) { 895 DRM_ERROR("dsi engine is not command mode\n"); 896 return -EINVAL; 897 } 898 899 if (MTK_DSI_HOST_IS_READ(msg->type)) 900 irq_flag |= LPRX_RD_RDY_INT_FLAG; 901 902 if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0) 903 return -ETIME; 904 905 if (!MTK_DSI_HOST_IS_READ(msg->type)) 906 return 0; 907 908 if (!msg->rx_buf) { 909 DRM_ERROR("dsi receive buffer size may be NULL\n"); 910 return -EINVAL; 911 } 912 913 for (i = 0; i < 16; i++) 914 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i); 915 916 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data); 917 918 if (recv_cnt > 2) 919 src_addr = &read_data[4]; 920 else 921 src_addr = &read_data[1]; 922 923 if (recv_cnt > 10) 924 recv_cnt = 10; 925 926 if (recv_cnt > msg->rx_len) 927 recv_cnt = msg->rx_len; 928 929 if (recv_cnt) 930 memcpy(msg->rx_buf, src_addr, recv_cnt); 931 932 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n", 933 recv_cnt, *((u8 *)(msg->tx_buf))); 934 935 return recv_cnt; 936 } 937 938 static const struct mipi_dsi_host_ops mtk_dsi_ops = { 939 .attach = mtk_dsi_host_attach, 940 .transfer = mtk_dsi_host_transfer, 941 }; 942 943 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) 944 { 945 int ret; 946 947 ret = drm_simple_encoder_init(drm, &dsi->encoder, 948 DRM_MODE_ENCODER_DSI); 949 if (ret) { 950 DRM_ERROR("Failed to encoder init to drm\n"); 951 return ret; 952 } 953 954 dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev); 955 956 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, 957 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 958 if (ret) 959 goto err_cleanup_encoder; 960 961 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder); 962 if (IS_ERR(dsi->connector)) { 963 DRM_ERROR("Unable to create bridge connector\n"); 964 ret = PTR_ERR(dsi->connector); 965 goto err_cleanup_encoder; 966 } 967 drm_connector_attach_encoder(dsi->connector, &dsi->encoder); 968 969 return 0; 970 971 err_cleanup_encoder: 972 drm_encoder_cleanup(&dsi->encoder); 973 return ret; 974 } 975 976 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) 977 { 978 int ret; 979 struct drm_device *drm = data; 980 struct mtk_dsi *dsi = dev_get_drvdata(dev); 981 982 ret = mtk_dsi_encoder_init(drm, dsi); 983 984 return ret; 985 } 986 987 static void mtk_dsi_unbind(struct device *dev, struct device *master, 988 void *data) 989 { 990 struct mtk_dsi *dsi = dev_get_drvdata(dev); 991 992 drm_encoder_cleanup(&dsi->encoder); 993 } 994 995 static const struct component_ops mtk_dsi_component_ops = { 996 .bind = mtk_dsi_bind, 997 .unbind = mtk_dsi_unbind, 998 }; 999 1000 static int mtk_dsi_probe(struct platform_device *pdev) 1001 { 1002 struct mtk_dsi *dsi; 1003 struct device *dev = &pdev->dev; 1004 struct drm_panel *panel; 1005 struct resource *regs; 1006 int irq_num; 1007 int ret; 1008 1009 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1010 if (!dsi) 1011 return -ENOMEM; 1012 1013 dsi->host.ops = &mtk_dsi_ops; 1014 dsi->host.dev = dev; 1015 ret = mipi_dsi_host_register(&dsi->host); 1016 if (ret < 0) { 1017 dev_err(dev, "failed to register DSI host: %d\n", ret); 1018 return ret; 1019 } 1020 1021 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, 1022 &panel, &dsi->next_bridge); 1023 if (ret) 1024 goto err_unregister_host; 1025 1026 if (panel) { 1027 dsi->next_bridge = devm_drm_panel_bridge_add(dev, panel); 1028 if (IS_ERR(dsi->next_bridge)) { 1029 ret = PTR_ERR(dsi->next_bridge); 1030 goto err_unregister_host; 1031 } 1032 } 1033 1034 dsi->driver_data = of_device_get_match_data(dev); 1035 1036 dsi->engine_clk = devm_clk_get(dev, "engine"); 1037 if (IS_ERR(dsi->engine_clk)) { 1038 ret = PTR_ERR(dsi->engine_clk); 1039 1040 if (ret != -EPROBE_DEFER) 1041 dev_err(dev, "Failed to get engine clock: %d\n", ret); 1042 goto err_unregister_host; 1043 } 1044 1045 dsi->digital_clk = devm_clk_get(dev, "digital"); 1046 if (IS_ERR(dsi->digital_clk)) { 1047 ret = PTR_ERR(dsi->digital_clk); 1048 1049 if (ret != -EPROBE_DEFER) 1050 dev_err(dev, "Failed to get digital clock: %d\n", ret); 1051 goto err_unregister_host; 1052 } 1053 1054 dsi->hs_clk = devm_clk_get(dev, "hs"); 1055 if (IS_ERR(dsi->hs_clk)) { 1056 ret = PTR_ERR(dsi->hs_clk); 1057 dev_err(dev, "Failed to get hs clock: %d\n", ret); 1058 goto err_unregister_host; 1059 } 1060 1061 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1062 dsi->regs = devm_ioremap_resource(dev, regs); 1063 if (IS_ERR(dsi->regs)) { 1064 ret = PTR_ERR(dsi->regs); 1065 dev_err(dev, "Failed to ioremap memory: %d\n", ret); 1066 goto err_unregister_host; 1067 } 1068 1069 dsi->phy = devm_phy_get(dev, "dphy"); 1070 if (IS_ERR(dsi->phy)) { 1071 ret = PTR_ERR(dsi->phy); 1072 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret); 1073 goto err_unregister_host; 1074 } 1075 1076 irq_num = platform_get_irq(pdev, 0); 1077 if (irq_num < 0) { 1078 dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num); 1079 ret = irq_num; 1080 goto err_unregister_host; 1081 } 1082 1083 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, 1084 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi); 1085 if (ret) { 1086 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n"); 1087 goto err_unregister_host; 1088 } 1089 1090 init_waitqueue_head(&dsi->irq_wait_queue); 1091 1092 platform_set_drvdata(pdev, dsi); 1093 1094 dsi->bridge.funcs = &mtk_dsi_bridge_funcs; 1095 dsi->bridge.of_node = dev->of_node; 1096 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 1097 1098 drm_bridge_add(&dsi->bridge); 1099 1100 ret = component_add(&pdev->dev, &mtk_dsi_component_ops); 1101 if (ret) { 1102 dev_err(&pdev->dev, "failed to add component: %d\n", ret); 1103 goto err_unregister_host; 1104 } 1105 1106 return 0; 1107 1108 err_unregister_host: 1109 mipi_dsi_host_unregister(&dsi->host); 1110 return ret; 1111 } 1112 1113 static int mtk_dsi_remove(struct platform_device *pdev) 1114 { 1115 struct mtk_dsi *dsi = platform_get_drvdata(pdev); 1116 1117 mtk_output_dsi_disable(dsi); 1118 drm_bridge_remove(&dsi->bridge); 1119 component_del(&pdev->dev, &mtk_dsi_component_ops); 1120 mipi_dsi_host_unregister(&dsi->host); 1121 1122 return 0; 1123 } 1124 1125 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { 1126 .reg_cmdq_off = 0x200, 1127 }; 1128 1129 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { 1130 .reg_cmdq_off = 0x180, 1131 }; 1132 1133 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { 1134 .reg_cmdq_off = 0x200, 1135 .has_shadow_ctl = true, 1136 .has_size_ctl = true, 1137 }; 1138 1139 static const struct of_device_id mtk_dsi_of_match[] = { 1140 { .compatible = "mediatek,mt2701-dsi", 1141 .data = &mt2701_dsi_driver_data }, 1142 { .compatible = "mediatek,mt8173-dsi", 1143 .data = &mt8173_dsi_driver_data }, 1144 { .compatible = "mediatek,mt8183-dsi", 1145 .data = &mt8183_dsi_driver_data }, 1146 { }, 1147 }; 1148 MODULE_DEVICE_TABLE(of, mtk_dsi_of_match); 1149 1150 struct platform_driver mtk_dsi_driver = { 1151 .probe = mtk_dsi_probe, 1152 .remove = mtk_dsi_remove, 1153 .driver = { 1154 .name = "mtk-dsi", 1155 .of_match_table = mtk_dsi_of_match, 1156 }, 1157 }; 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