1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <drm/drmP.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_crtc_helper.h> 17 #include <drm/drm_mipi_dsi.h> 18 #include <drm/drm_panel.h> 19 #include <drm/drm_of.h> 20 #include <linux/clk.h> 21 #include <linux/component.h> 22 #include <linux/irq.h> 23 #include <linux/of.h> 24 #include <linux/of_platform.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <video/mipi_display.h> 28 #include <video/videomode.h> 29 30 #include "mtk_drm_ddp_comp.h" 31 32 #define DSI_START 0x00 33 34 #define DSI_INTEN 0x08 35 36 #define DSI_INTSTA 0x0c 37 #define LPRX_RD_RDY_INT_FLAG BIT(0) 38 #define CMD_DONE_INT_FLAG BIT(1) 39 #define TE_RDY_INT_FLAG BIT(2) 40 #define VM_DONE_INT_FLAG BIT(3) 41 #define EXT_TE_RDY_INT_FLAG BIT(4) 42 #define DSI_BUSY BIT(31) 43 44 #define DSI_CON_CTRL 0x10 45 #define DSI_RESET BIT(0) 46 #define DSI_EN BIT(1) 47 48 #define DSI_MODE_CTRL 0x14 49 #define MODE (3) 50 #define CMD_MODE 0 51 #define SYNC_PULSE_MODE 1 52 #define SYNC_EVENT_MODE 2 53 #define BURST_MODE 3 54 #define FRM_MODE BIT(16) 55 #define MIX_MODE BIT(17) 56 57 #define DSI_TXRX_CTRL 0x18 58 #define VC_NUM BIT(1) 59 #define LANE_NUM (0xf << 2) 60 #define DIS_EOT BIT(6) 61 #define NULL_EN BIT(7) 62 #define TE_FREERUN BIT(8) 63 #define EXT_TE_EN BIT(9) 64 #define EXT_TE_EDGE BIT(10) 65 #define MAX_RTN_SIZE (0xf << 12) 66 #define HSTX_CKLP_EN BIT(16) 67 68 #define DSI_PSCTRL 0x1c 69 #define DSI_PS_WC 0x3fff 70 #define DSI_PS_SEL (3 << 16) 71 #define PACKED_PS_16BIT_RGB565 (0 << 16) 72 #define LOOSELY_PS_18BIT_RGB666 (1 << 16) 73 #define PACKED_PS_18BIT_RGB666 (2 << 16) 74 #define PACKED_PS_24BIT_RGB888 (3 << 16) 75 76 #define DSI_VSA_NL 0x20 77 #define DSI_VBP_NL 0x24 78 #define DSI_VFP_NL 0x28 79 #define DSI_VACT_NL 0x2C 80 #define DSI_HSA_WC 0x50 81 #define DSI_HBP_WC 0x54 82 #define DSI_HFP_WC 0x58 83 84 #define DSI_CMDQ_SIZE 0x60 85 #define CMDQ_SIZE 0x3f 86 87 #define DSI_HSTX_CKL_WC 0x64 88 89 #define DSI_RX_DATA0 0x74 90 #define DSI_RX_DATA1 0x78 91 #define DSI_RX_DATA2 0x7c 92 #define DSI_RX_DATA3 0x80 93 94 #define DSI_RACK 0x84 95 #define RACK BIT(0) 96 97 #define DSI_PHY_LCCON 0x104 98 #define LC_HS_TX_EN BIT(0) 99 #define LC_ULPM_EN BIT(1) 100 #define LC_WAKEUP_EN BIT(2) 101 102 #define DSI_PHY_LD0CON 0x108 103 #define LD0_HS_TX_EN BIT(0) 104 #define LD0_ULPM_EN BIT(1) 105 #define LD0_WAKEUP_EN BIT(2) 106 107 #define DSI_PHY_TIMECON0 0x110 108 #define LPX (0xff << 0) 109 #define HS_PREP (0xff << 8) 110 #define HS_ZERO (0xff << 16) 111 #define HS_TRAIL (0xff << 24) 112 113 #define DSI_PHY_TIMECON1 0x114 114 #define TA_GO (0xff << 0) 115 #define TA_SURE (0xff << 8) 116 #define TA_GET (0xff << 16) 117 #define DA_HS_EXIT (0xff << 24) 118 119 #define DSI_PHY_TIMECON2 0x118 120 #define CONT_DET (0xff << 0) 121 #define CLK_ZERO (0xff << 16) 122 #define CLK_TRAIL (0xff << 24) 123 124 #define DSI_PHY_TIMECON3 0x11c 125 #define CLK_HS_PREP (0xff << 0) 126 #define CLK_HS_POST (0xff << 8) 127 #define CLK_HS_EXIT (0xff << 16) 128 129 #define DSI_VM_CMD_CON 0x130 130 #define VM_CMD_EN BIT(0) 131 #define TS_VFP_EN BIT(5) 132 133 #define DSI_CMDQ0 0x180 134 #define CONFIG (0xff << 0) 135 #define SHORT_PACKET 0 136 #define LONG_PACKET 2 137 #define BTA BIT(2) 138 #define DATA_ID (0xff << 8) 139 #define DATA_0 (0xff << 16) 140 #define DATA_1 (0xff << 24) 141 142 #define T_LPX 5 143 #define T_HS_PREP 6 144 #define T_HS_TRAIL 8 145 #define T_HS_EXIT 7 146 #define T_HS_ZERO 10 147 148 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) 149 150 #define MTK_DSI_HOST_IS_READ(type) \ 151 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ 152 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ 153 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ 154 (type == MIPI_DSI_DCS_READ)) 155 156 struct phy; 157 158 struct mtk_dsi { 159 struct mtk_ddp_comp ddp_comp; 160 struct device *dev; 161 struct mipi_dsi_host host; 162 struct drm_encoder encoder; 163 struct drm_connector conn; 164 struct drm_panel *panel; 165 struct drm_bridge *bridge; 166 struct phy *phy; 167 168 void __iomem *regs; 169 170 struct clk *engine_clk; 171 struct clk *digital_clk; 172 struct clk *hs_clk; 173 174 u32 data_rate; 175 176 unsigned long mode_flags; 177 enum mipi_dsi_pixel_format format; 178 unsigned int lanes; 179 struct videomode vm; 180 int refcount; 181 bool enabled; 182 u32 irq_data; 183 wait_queue_head_t irq_wait_queue; 184 }; 185 186 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e) 187 { 188 return container_of(e, struct mtk_dsi, encoder); 189 } 190 191 static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c) 192 { 193 return container_of(c, struct mtk_dsi, conn); 194 } 195 196 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h) 197 { 198 return container_of(h, struct mtk_dsi, host); 199 } 200 201 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) 202 { 203 u32 temp = readl(dsi->regs + offset); 204 205 writel((temp & ~mask) | (data & mask), dsi->regs + offset); 206 } 207 208 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) 209 { 210 u32 timcon0, timcon1, timcon2, timcon3; 211 u32 ui, cycle_time; 212 213 ui = 1000 / dsi->data_rate + 0x01; 214 cycle_time = 8000 / dsi->data_rate + 0x01; 215 216 timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24; 217 timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 | 218 T_HS_EXIT << 24; 219 timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) | 220 (NS_TO_CYCLE(0x150, cycle_time) << 16); 221 timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 | 222 NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8; 223 224 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); 225 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); 226 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); 227 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); 228 } 229 230 static void mtk_dsi_enable(struct mtk_dsi *dsi) 231 { 232 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN); 233 } 234 235 static void mtk_dsi_disable(struct mtk_dsi *dsi) 236 { 237 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0); 238 } 239 240 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi) 241 { 242 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET); 243 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0); 244 } 245 246 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) 247 { 248 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 249 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 250 } 251 252 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) 253 { 254 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 255 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN); 256 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0); 257 } 258 259 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) 260 { 261 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); 262 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 263 } 264 265 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) 266 { 267 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 268 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN); 269 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0); 270 } 271 272 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi) 273 { 274 u32 tmp_reg1; 275 276 tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON); 277 return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false; 278 } 279 280 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter) 281 { 282 if (enter && !mtk_dsi_clk_hs_state(dsi)) 283 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN); 284 else if (!enter && mtk_dsi_clk_hs_state(dsi)) 285 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 286 } 287 288 static void mtk_dsi_set_mode(struct mtk_dsi *dsi) 289 { 290 u32 vid_mode = CMD_MODE; 291 292 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 293 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 294 vid_mode = BURST_MODE; 295 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 296 vid_mode = SYNC_PULSE_MODE; 297 else 298 vid_mode = SYNC_EVENT_MODE; 299 } 300 301 writel(vid_mode, dsi->regs + DSI_MODE_CTRL); 302 } 303 304 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) 305 { 306 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); 307 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); 308 } 309 310 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) 311 { 312 struct videomode *vm = &dsi->vm; 313 u32 dsi_buf_bpp, ps_wc; 314 u32 ps_bpp_mode; 315 316 if (dsi->format == MIPI_DSI_FMT_RGB565) 317 dsi_buf_bpp = 2; 318 else 319 dsi_buf_bpp = 3; 320 321 ps_wc = vm->hactive * dsi_buf_bpp; 322 ps_bpp_mode = ps_wc; 323 324 switch (dsi->format) { 325 case MIPI_DSI_FMT_RGB888: 326 ps_bpp_mode |= PACKED_PS_24BIT_RGB888; 327 break; 328 case MIPI_DSI_FMT_RGB666: 329 ps_bpp_mode |= PACKED_PS_18BIT_RGB666; 330 break; 331 case MIPI_DSI_FMT_RGB666_PACKED: 332 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; 333 break; 334 case MIPI_DSI_FMT_RGB565: 335 ps_bpp_mode |= PACKED_PS_16BIT_RGB565; 336 break; 337 } 338 339 writel(vm->vactive, dsi->regs + DSI_VACT_NL); 340 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); 341 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); 342 } 343 344 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) 345 { 346 u32 tmp_reg; 347 348 switch (dsi->lanes) { 349 case 1: 350 tmp_reg = 1 << 2; 351 break; 352 case 2: 353 tmp_reg = 3 << 2; 354 break; 355 case 3: 356 tmp_reg = 7 << 2; 357 break; 358 case 4: 359 tmp_reg = 0xf << 2; 360 break; 361 default: 362 tmp_reg = 0xf << 2; 363 break; 364 } 365 366 tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; 367 tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; 368 369 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); 370 } 371 372 static void mtk_dsi_ps_control(struct mtk_dsi *dsi) 373 { 374 u32 dsi_tmp_buf_bpp; 375 u32 tmp_reg; 376 377 switch (dsi->format) { 378 case MIPI_DSI_FMT_RGB888: 379 tmp_reg = PACKED_PS_24BIT_RGB888; 380 dsi_tmp_buf_bpp = 3; 381 break; 382 case MIPI_DSI_FMT_RGB666: 383 tmp_reg = LOOSELY_PS_18BIT_RGB666; 384 dsi_tmp_buf_bpp = 3; 385 break; 386 case MIPI_DSI_FMT_RGB666_PACKED: 387 tmp_reg = PACKED_PS_18BIT_RGB666; 388 dsi_tmp_buf_bpp = 3; 389 break; 390 case MIPI_DSI_FMT_RGB565: 391 tmp_reg = PACKED_PS_16BIT_RGB565; 392 dsi_tmp_buf_bpp = 2; 393 break; 394 default: 395 tmp_reg = PACKED_PS_24BIT_RGB888; 396 dsi_tmp_buf_bpp = 3; 397 break; 398 } 399 400 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; 401 writel(tmp_reg, dsi->regs + DSI_PSCTRL); 402 } 403 404 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) 405 { 406 u32 horizontal_sync_active_byte; 407 u32 horizontal_backporch_byte; 408 u32 horizontal_frontporch_byte; 409 u32 dsi_tmp_buf_bpp; 410 411 struct videomode *vm = &dsi->vm; 412 413 if (dsi->format == MIPI_DSI_FMT_RGB565) 414 dsi_tmp_buf_bpp = 2; 415 else 416 dsi_tmp_buf_bpp = 3; 417 418 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL); 419 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL); 420 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); 421 writel(vm->vactive, dsi->regs + DSI_VACT_NL); 422 423 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); 424 425 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 426 horizontal_backporch_byte = 427 (vm->hback_porch * dsi_tmp_buf_bpp - 10); 428 else 429 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) * 430 dsi_tmp_buf_bpp - 10); 431 432 horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12); 433 434 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); 435 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); 436 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); 437 438 mtk_dsi_ps_control(dsi); 439 } 440 441 static void mtk_dsi_start(struct mtk_dsi *dsi) 442 { 443 writel(0, dsi->regs + DSI_START); 444 writel(1, dsi->regs + DSI_START); 445 } 446 447 static void mtk_dsi_stop(struct mtk_dsi *dsi) 448 { 449 writel(0, dsi->regs + DSI_START); 450 } 451 452 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) 453 { 454 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); 455 } 456 457 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) 458 { 459 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 460 461 writel(inten, dsi->regs + DSI_INTEN); 462 } 463 464 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit) 465 { 466 dsi->irq_data |= irq_bit; 467 } 468 469 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit) 470 { 471 dsi->irq_data &= ~irq_bit; 472 } 473 474 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag, 475 unsigned int timeout) 476 { 477 s32 ret = 0; 478 unsigned long jiffies = msecs_to_jiffies(timeout); 479 480 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue, 481 dsi->irq_data & irq_flag, 482 jiffies); 483 if (ret == 0) { 484 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag); 485 486 mtk_dsi_enable(dsi); 487 mtk_dsi_reset_engine(dsi); 488 } 489 490 return ret; 491 } 492 493 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) 494 { 495 struct mtk_dsi *dsi = dev_id; 496 u32 status, tmp; 497 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 498 499 status = readl(dsi->regs + DSI_INTSTA) & flag; 500 501 if (status) { 502 do { 503 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); 504 tmp = readl(dsi->regs + DSI_INTSTA); 505 } while (tmp & DSI_BUSY); 506 507 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0); 508 mtk_dsi_irq_data_set(dsi, status); 509 wake_up_interruptible(&dsi->irq_wait_queue); 510 } 511 512 return IRQ_HANDLED; 513 } 514 515 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) 516 { 517 mtk_dsi_irq_data_clear(dsi, irq_flag); 518 mtk_dsi_set_cmd_mode(dsi); 519 520 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) { 521 DRM_ERROR("failed to switch cmd mode\n"); 522 return -ETIME; 523 } else { 524 return 0; 525 } 526 } 527 528 static int mtk_dsi_poweron(struct mtk_dsi *dsi) 529 { 530 struct device *dev = dsi->dev; 531 int ret; 532 u64 pixel_clock, total_bits; 533 u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits; 534 535 if (++dsi->refcount != 1) 536 return 0; 537 538 switch (dsi->format) { 539 case MIPI_DSI_FMT_RGB565: 540 bit_per_pixel = 16; 541 break; 542 case MIPI_DSI_FMT_RGB666_PACKED: 543 bit_per_pixel = 18; 544 break; 545 case MIPI_DSI_FMT_RGB666: 546 case MIPI_DSI_FMT_RGB888: 547 default: 548 bit_per_pixel = 24; 549 break; 550 } 551 552 /** 553 * vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000 554 * htotal_time = htotal * byte_per_pixel / num_lanes 555 * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit 556 * mipi_ratio = (htotal_time + overhead_time) / htotal_time 557 * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes; 558 */ 559 pixel_clock = dsi->vm.pixelclock * 1000; 560 htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch + 561 dsi->vm.hsync_len; 562 htotal_bits = htotal * bit_per_pixel; 563 564 overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL + 565 T_HS_EXIT; 566 overhead_bits = overhead_cycles * dsi->lanes * 8; 567 total_bits = htotal_bits + overhead_bits; 568 569 dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits, 570 htotal * dsi->lanes); 571 572 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate); 573 if (ret < 0) { 574 dev_err(dev, "Failed to set data rate: %d\n", ret); 575 goto err_refcount; 576 } 577 578 phy_power_on(dsi->phy); 579 580 ret = clk_prepare_enable(dsi->engine_clk); 581 if (ret < 0) { 582 dev_err(dev, "Failed to enable engine clock: %d\n", ret); 583 goto err_phy_power_off; 584 } 585 586 ret = clk_prepare_enable(dsi->digital_clk); 587 if (ret < 0) { 588 dev_err(dev, "Failed to enable digital clock: %d\n", ret); 589 goto err_disable_engine_clk; 590 } 591 592 mtk_dsi_enable(dsi); 593 mtk_dsi_reset_engine(dsi); 594 mtk_dsi_phy_timconfig(dsi); 595 596 mtk_dsi_rxtx_control(dsi); 597 mtk_dsi_ps_control_vact(dsi); 598 mtk_dsi_set_vm_cmd(dsi); 599 mtk_dsi_config_vdo_timing(dsi); 600 mtk_dsi_set_interrupt_enable(dsi); 601 602 mtk_dsi_clk_ulp_mode_leave(dsi); 603 mtk_dsi_lane0_ulp_mode_leave(dsi); 604 mtk_dsi_clk_hs_mode(dsi, 0); 605 606 if (dsi->panel) { 607 if (drm_panel_prepare(dsi->panel)) { 608 DRM_ERROR("failed to prepare the panel\n"); 609 goto err_disable_digital_clk; 610 } 611 } 612 613 return 0; 614 err_disable_digital_clk: 615 clk_disable_unprepare(dsi->digital_clk); 616 err_disable_engine_clk: 617 clk_disable_unprepare(dsi->engine_clk); 618 err_phy_power_off: 619 phy_power_off(dsi->phy); 620 err_refcount: 621 dsi->refcount--; 622 return ret; 623 } 624 625 static void mtk_dsi_poweroff(struct mtk_dsi *dsi) 626 { 627 if (WARN_ON(dsi->refcount == 0)) 628 return; 629 630 if (--dsi->refcount != 0) 631 return; 632 633 if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) { 634 if (dsi->panel) { 635 if (drm_panel_unprepare(dsi->panel)) { 636 DRM_ERROR("failed to unprepare the panel\n"); 637 return; 638 } 639 } 640 } 641 642 mtk_dsi_reset_engine(dsi); 643 mtk_dsi_lane0_ulp_mode_enter(dsi); 644 mtk_dsi_clk_ulp_mode_enter(dsi); 645 646 mtk_dsi_disable(dsi); 647 648 clk_disable_unprepare(dsi->engine_clk); 649 clk_disable_unprepare(dsi->digital_clk); 650 651 phy_power_off(dsi->phy); 652 } 653 654 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) 655 { 656 int ret; 657 658 if (dsi->enabled) 659 return; 660 661 ret = mtk_dsi_poweron(dsi); 662 if (ret < 0) { 663 DRM_ERROR("failed to power on dsi\n"); 664 return; 665 } 666 667 mtk_dsi_set_mode(dsi); 668 mtk_dsi_clk_hs_mode(dsi, 1); 669 670 mtk_dsi_start(dsi); 671 672 if (dsi->panel) { 673 if (drm_panel_enable(dsi->panel)) { 674 DRM_ERROR("failed to enable the panel\n"); 675 goto err_dsi_power_off; 676 } 677 } 678 679 dsi->enabled = true; 680 681 return; 682 err_dsi_power_off: 683 mtk_dsi_stop(dsi); 684 mtk_dsi_poweroff(dsi); 685 } 686 687 static void mtk_output_dsi_disable(struct mtk_dsi *dsi) 688 { 689 if (!dsi->enabled) 690 return; 691 692 if (dsi->panel) { 693 if (drm_panel_disable(dsi->panel)) { 694 DRM_ERROR("failed to disable the panel\n"); 695 return; 696 } 697 } 698 699 mtk_dsi_stop(dsi); 700 mtk_dsi_poweroff(dsi); 701 702 dsi->enabled = false; 703 } 704 705 static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder) 706 { 707 drm_encoder_cleanup(encoder); 708 } 709 710 static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = { 711 .destroy = mtk_dsi_encoder_destroy, 712 }; 713 714 static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder, 715 const struct drm_display_mode *mode, 716 struct drm_display_mode *adjusted_mode) 717 { 718 return true; 719 } 720 721 static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder, 722 struct drm_display_mode *mode, 723 struct drm_display_mode *adjusted) 724 { 725 struct mtk_dsi *dsi = encoder_to_dsi(encoder); 726 727 dsi->vm.pixelclock = adjusted->clock; 728 dsi->vm.hactive = adjusted->hdisplay; 729 dsi->vm.hback_porch = adjusted->htotal - adjusted->hsync_end; 730 dsi->vm.hfront_porch = adjusted->hsync_start - adjusted->hdisplay; 731 dsi->vm.hsync_len = adjusted->hsync_end - adjusted->hsync_start; 732 733 dsi->vm.vactive = adjusted->vdisplay; 734 dsi->vm.vback_porch = adjusted->vtotal - adjusted->vsync_end; 735 dsi->vm.vfront_porch = adjusted->vsync_start - adjusted->vdisplay; 736 dsi->vm.vsync_len = adjusted->vsync_end - adjusted->vsync_start; 737 } 738 739 static void mtk_dsi_encoder_disable(struct drm_encoder *encoder) 740 { 741 struct mtk_dsi *dsi = encoder_to_dsi(encoder); 742 743 mtk_output_dsi_disable(dsi); 744 } 745 746 static void mtk_dsi_encoder_enable(struct drm_encoder *encoder) 747 { 748 struct mtk_dsi *dsi = encoder_to_dsi(encoder); 749 750 mtk_output_dsi_enable(dsi); 751 } 752 753 static int mtk_dsi_connector_get_modes(struct drm_connector *connector) 754 { 755 struct mtk_dsi *dsi = connector_to_dsi(connector); 756 757 return drm_panel_get_modes(dsi->panel); 758 } 759 760 static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = { 761 .mode_fixup = mtk_dsi_encoder_mode_fixup, 762 .mode_set = mtk_dsi_encoder_mode_set, 763 .disable = mtk_dsi_encoder_disable, 764 .enable = mtk_dsi_encoder_enable, 765 }; 766 767 static const struct drm_connector_funcs mtk_dsi_connector_funcs = { 768 .dpms = drm_atomic_helper_connector_dpms, 769 .fill_modes = drm_helper_probe_single_connector_modes, 770 .destroy = drm_connector_cleanup, 771 .reset = drm_atomic_helper_connector_reset, 772 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 773 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 774 }; 775 776 static const struct drm_connector_helper_funcs 777 mtk_dsi_connector_helper_funcs = { 778 .get_modes = mtk_dsi_connector_get_modes, 779 }; 780 781 static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi) 782 { 783 int ret; 784 785 ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs, 786 DRM_MODE_CONNECTOR_DSI); 787 if (ret) { 788 DRM_ERROR("Failed to connector init to drm\n"); 789 return ret; 790 } 791 792 drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs); 793 794 dsi->conn.dpms = DRM_MODE_DPMS_OFF; 795 drm_mode_connector_attach_encoder(&dsi->conn, &dsi->encoder); 796 797 if (dsi->panel) { 798 ret = drm_panel_attach(dsi->panel, &dsi->conn); 799 if (ret) { 800 DRM_ERROR("Failed to attach panel to drm\n"); 801 goto err_connector_cleanup; 802 } 803 } 804 805 return 0; 806 807 err_connector_cleanup: 808 drm_connector_cleanup(&dsi->conn); 809 return ret; 810 } 811 812 static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi) 813 { 814 int ret; 815 816 ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs, 817 DRM_MODE_ENCODER_DSI, NULL); 818 if (ret) { 819 DRM_ERROR("Failed to encoder init to drm\n"); 820 return ret; 821 } 822 drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs); 823 824 /* 825 * Currently display data paths are statically assigned to a crtc each. 826 * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 827 */ 828 dsi->encoder.possible_crtcs = 1; 829 830 /* If there's a bridge, attach to it and let it create the connector */ 831 ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL); 832 if (ret) { 833 DRM_ERROR("Failed to attach bridge to drm\n"); 834 835 /* Otherwise create our own connector and attach to a panel */ 836 ret = mtk_dsi_create_connector(drm, dsi); 837 if (ret) 838 goto err_encoder_cleanup; 839 } 840 841 return 0; 842 843 err_encoder_cleanup: 844 drm_encoder_cleanup(&dsi->encoder); 845 return ret; 846 } 847 848 static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi) 849 { 850 drm_encoder_cleanup(&dsi->encoder); 851 /* Skip connector cleanup if creation was delegated to the bridge */ 852 if (dsi->conn.dev) 853 drm_connector_cleanup(&dsi->conn); 854 } 855 856 static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp) 857 { 858 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp); 859 860 mtk_dsi_poweron(dsi); 861 } 862 863 static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp) 864 { 865 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp); 866 867 mtk_dsi_poweroff(dsi); 868 } 869 870 static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = { 871 .start = mtk_dsi_ddp_start, 872 .stop = mtk_dsi_ddp_stop, 873 }; 874 875 static int mtk_dsi_host_attach(struct mipi_dsi_host *host, 876 struct mipi_dsi_device *device) 877 { 878 struct mtk_dsi *dsi = host_to_dsi(host); 879 880 dsi->lanes = device->lanes; 881 dsi->format = device->format; 882 dsi->mode_flags = device->mode_flags; 883 884 if (dsi->conn.dev) 885 drm_helper_hpd_irq_event(dsi->conn.dev); 886 887 return 0; 888 } 889 890 static int mtk_dsi_host_detach(struct mipi_dsi_host *host, 891 struct mipi_dsi_device *device) 892 { 893 struct mtk_dsi *dsi = host_to_dsi(host); 894 895 if (dsi->conn.dev) 896 drm_helper_hpd_irq_event(dsi->conn.dev); 897 898 return 0; 899 } 900 901 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi) 902 { 903 u32 timeout_ms = 500000; /* total 1s ~ 2s timeout */ 904 905 while (timeout_ms--) { 906 if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY)) 907 break; 908 909 usleep_range(2, 4); 910 } 911 912 if (timeout_ms == 0) { 913 DRM_WARN("polling dsi wait not busy timeout!\n"); 914 915 mtk_dsi_enable(dsi); 916 mtk_dsi_reset_engine(dsi); 917 } 918 } 919 920 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data) 921 { 922 switch (type) { 923 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 924 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 925 return 1; 926 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 927 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 928 return 2; 929 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 930 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 931 return read_data[1] + read_data[2] * 16; 932 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 933 DRM_INFO("type is 0x02, try again\n"); 934 break; 935 default: 936 DRM_INFO("type(0x%x) cannot be non-recognite\n", type); 937 break; 938 } 939 940 return 0; 941 } 942 943 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) 944 { 945 const char *tx_buf = msg->tx_buf; 946 u8 config, cmdq_size, cmdq_off, type = msg->type; 947 u32 reg_val, cmdq_mask, i; 948 949 if (MTK_DSI_HOST_IS_READ(type)) 950 config = BTA; 951 else 952 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET; 953 954 if (msg->tx_len > 2) { 955 cmdq_size = 1 + (msg->tx_len + 3) / 4; 956 cmdq_off = 4; 957 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; 958 reg_val = (msg->tx_len << 16) | (type << 8) | config; 959 } else { 960 cmdq_size = 1; 961 cmdq_off = 2; 962 cmdq_mask = CONFIG | DATA_ID; 963 reg_val = (type << 8) | config; 964 } 965 966 for (i = 0; i < msg->tx_len; i++) 967 writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i); 968 969 mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val); 970 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); 971 } 972 973 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi, 974 const struct mipi_dsi_msg *msg, u8 flag) 975 { 976 mtk_dsi_wait_for_idle(dsi); 977 mtk_dsi_irq_data_clear(dsi, flag); 978 mtk_dsi_cmdq(dsi, msg); 979 mtk_dsi_start(dsi); 980 981 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000)) 982 return -ETIME; 983 else 984 return 0; 985 } 986 987 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host, 988 const struct mipi_dsi_msg *msg) 989 { 990 struct mtk_dsi *dsi = host_to_dsi(host); 991 u32 recv_cnt, i; 992 u8 read_data[16]; 993 void *src_addr; 994 u8 irq_flag = CMD_DONE_INT_FLAG; 995 996 if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) { 997 DRM_ERROR("dsi engine is not command mode\n"); 998 return -EINVAL; 999 } 1000 1001 if (MTK_DSI_HOST_IS_READ(msg->type)) 1002 irq_flag |= LPRX_RD_RDY_INT_FLAG; 1003 1004 if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0) 1005 return -ETIME; 1006 1007 if (!MTK_DSI_HOST_IS_READ(msg->type)) 1008 return 0; 1009 1010 if (!msg->rx_buf) { 1011 DRM_ERROR("dsi receive buffer size may be NULL\n"); 1012 return -EINVAL; 1013 } 1014 1015 for (i = 0; i < 16; i++) 1016 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i); 1017 1018 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data); 1019 1020 if (recv_cnt > 2) 1021 src_addr = &read_data[4]; 1022 else 1023 src_addr = &read_data[1]; 1024 1025 if (recv_cnt > 10) 1026 recv_cnt = 10; 1027 1028 if (recv_cnt > msg->rx_len) 1029 recv_cnt = msg->rx_len; 1030 1031 if (recv_cnt) 1032 memcpy(msg->rx_buf, src_addr, recv_cnt); 1033 1034 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n", 1035 recv_cnt, *((u8 *)(msg->tx_buf))); 1036 1037 return recv_cnt; 1038 } 1039 1040 static const struct mipi_dsi_host_ops mtk_dsi_ops = { 1041 .attach = mtk_dsi_host_attach, 1042 .detach = mtk_dsi_host_detach, 1043 .transfer = mtk_dsi_host_transfer, 1044 }; 1045 1046 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) 1047 { 1048 int ret; 1049 struct drm_device *drm = data; 1050 struct mtk_dsi *dsi = dev_get_drvdata(dev); 1051 1052 ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp); 1053 if (ret < 0) { 1054 dev_err(dev, "Failed to register component %s: %d\n", 1055 dev->of_node->full_name, ret); 1056 return ret; 1057 } 1058 1059 ret = mipi_dsi_host_register(&dsi->host); 1060 if (ret < 0) { 1061 dev_err(dev, "failed to register DSI host: %d\n", ret); 1062 goto err_ddp_comp_unregister; 1063 } 1064 1065 ret = mtk_dsi_create_conn_enc(drm, dsi); 1066 if (ret) { 1067 DRM_ERROR("Encoder create failed with %d\n", ret); 1068 goto err_unregister; 1069 } 1070 1071 return 0; 1072 1073 err_unregister: 1074 mipi_dsi_host_unregister(&dsi->host); 1075 err_ddp_comp_unregister: 1076 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); 1077 return ret; 1078 } 1079 1080 static void mtk_dsi_unbind(struct device *dev, struct device *master, 1081 void *data) 1082 { 1083 struct drm_device *drm = data; 1084 struct mtk_dsi *dsi = dev_get_drvdata(dev); 1085 1086 mtk_dsi_destroy_conn_enc(dsi); 1087 mipi_dsi_host_unregister(&dsi->host); 1088 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); 1089 } 1090 1091 static const struct component_ops mtk_dsi_component_ops = { 1092 .bind = mtk_dsi_bind, 1093 .unbind = mtk_dsi_unbind, 1094 }; 1095 1096 static int mtk_dsi_probe(struct platform_device *pdev) 1097 { 1098 struct mtk_dsi *dsi; 1099 struct device *dev = &pdev->dev; 1100 struct resource *regs; 1101 int irq_num; 1102 int comp_id; 1103 int ret; 1104 1105 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1106 if (!dsi) 1107 return -ENOMEM; 1108 1109 dsi->host.ops = &mtk_dsi_ops; 1110 dsi->host.dev = dev; 1111 1112 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, 1113 &dsi->panel, &dsi->bridge); 1114 if (ret) 1115 return ret; 1116 1117 dsi->engine_clk = devm_clk_get(dev, "engine"); 1118 if (IS_ERR(dsi->engine_clk)) { 1119 ret = PTR_ERR(dsi->engine_clk); 1120 dev_err(dev, "Failed to get engine clock: %d\n", ret); 1121 return ret; 1122 } 1123 1124 dsi->digital_clk = devm_clk_get(dev, "digital"); 1125 if (IS_ERR(dsi->digital_clk)) { 1126 ret = PTR_ERR(dsi->digital_clk); 1127 dev_err(dev, "Failed to get digital clock: %d\n", ret); 1128 return ret; 1129 } 1130 1131 dsi->hs_clk = devm_clk_get(dev, "hs"); 1132 if (IS_ERR(dsi->hs_clk)) { 1133 ret = PTR_ERR(dsi->hs_clk); 1134 dev_err(dev, "Failed to get hs clock: %d\n", ret); 1135 return ret; 1136 } 1137 1138 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1139 dsi->regs = devm_ioremap_resource(dev, regs); 1140 if (IS_ERR(dsi->regs)) { 1141 ret = PTR_ERR(dsi->regs); 1142 dev_err(dev, "Failed to ioremap memory: %d\n", ret); 1143 return ret; 1144 } 1145 1146 dsi->phy = devm_phy_get(dev, "dphy"); 1147 if (IS_ERR(dsi->phy)) { 1148 ret = PTR_ERR(dsi->phy); 1149 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret); 1150 return ret; 1151 } 1152 1153 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI); 1154 if (comp_id < 0) { 1155 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 1156 return comp_id; 1157 } 1158 1159 ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id, 1160 &mtk_dsi_funcs); 1161 if (ret) { 1162 dev_err(dev, "Failed to initialize component: %d\n", ret); 1163 return ret; 1164 } 1165 1166 irq_num = platform_get_irq(pdev, 0); 1167 if (irq_num < 0) { 1168 dev_err(&pdev->dev, "failed to request dsi irq resource\n"); 1169 return -EPROBE_DEFER; 1170 } 1171 1172 irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW); 1173 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, 1174 IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi); 1175 if (ret) { 1176 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n"); 1177 return -EPROBE_DEFER; 1178 } 1179 1180 init_waitqueue_head(&dsi->irq_wait_queue); 1181 1182 platform_set_drvdata(pdev, dsi); 1183 1184 return component_add(&pdev->dev, &mtk_dsi_component_ops); 1185 } 1186 1187 static int mtk_dsi_remove(struct platform_device *pdev) 1188 { 1189 struct mtk_dsi *dsi = platform_get_drvdata(pdev); 1190 1191 mtk_output_dsi_disable(dsi); 1192 component_del(&pdev->dev, &mtk_dsi_component_ops); 1193 1194 return 0; 1195 } 1196 1197 static const struct of_device_id mtk_dsi_of_match[] = { 1198 { .compatible = "mediatek,mt2701-dsi" }, 1199 { .compatible = "mediatek,mt8173-dsi" }, 1200 { }, 1201 }; 1202 1203 struct platform_driver mtk_dsi_driver = { 1204 .probe = mtk_dsi_probe, 1205 .remove = mtk_dsi_remove, 1206 .driver = { 1207 .name = "mtk-dsi", 1208 .of_match_table = mtk_dsi_of_match, 1209 }, 1210 }; 1211