1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of_address.h> 11 #include <linux/of_platform.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_fb_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 27 #include "mtk_drm_crtc.h" 28 #include "mtk_drm_ddp_comp.h" 29 #include "mtk_drm_drv.h" 30 #include "mtk_drm_gem.h" 31 32 #define DRIVER_NAME "mediatek" 33 #define DRIVER_DESC "Mediatek SoC DRM" 34 #define DRIVER_DATE "20150513" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 38 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 39 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 40 }; 41 42 static struct drm_framebuffer * 43 mtk_drm_mode_fb_create(struct drm_device *dev, 44 struct drm_file *file, 45 const struct drm_mode_fb_cmd2 *cmd) 46 { 47 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 48 49 if (info->num_planes != 1) 50 return ERR_PTR(-EINVAL); 51 52 return drm_gem_fb_create(dev, file, cmd); 53 } 54 55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 56 .fb_create = mtk_drm_mode_fb_create, 57 .atomic_check = drm_atomic_helper_check, 58 .atomic_commit = drm_atomic_helper_commit, 59 }; 60 61 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { 62 DDP_COMPONENT_OVL0, 63 DDP_COMPONENT_RDMA0, 64 DDP_COMPONENT_COLOR0, 65 DDP_COMPONENT_BLS, 66 DDP_COMPONENT_DSI0, 67 }; 68 69 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { 70 DDP_COMPONENT_RDMA1, 71 DDP_COMPONENT_DPI0, 72 }; 73 74 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = { 75 DDP_COMPONENT_OVL0, 76 DDP_COMPONENT_RDMA0, 77 DDP_COMPONENT_COLOR0, 78 DDP_COMPONENT_BLS, 79 DDP_COMPONENT_DPI0, 80 }; 81 82 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = { 83 DDP_COMPONENT_RDMA1, 84 DDP_COMPONENT_DSI0, 85 }; 86 87 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { 88 DDP_COMPONENT_OVL0, 89 DDP_COMPONENT_COLOR0, 90 DDP_COMPONENT_AAL0, 91 DDP_COMPONENT_OD0, 92 DDP_COMPONENT_RDMA0, 93 DDP_COMPONENT_DPI0, 94 DDP_COMPONENT_PWM0, 95 }; 96 97 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 98 DDP_COMPONENT_OVL1, 99 DDP_COMPONENT_COLOR1, 100 DDP_COMPONENT_AAL1, 101 DDP_COMPONENT_OD1, 102 DDP_COMPONENT_RDMA1, 103 DDP_COMPONENT_DPI1, 104 DDP_COMPONENT_PWM1, 105 }; 106 107 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 108 DDP_COMPONENT_RDMA2, 109 DDP_COMPONENT_DSI3, 110 DDP_COMPONENT_PWM2, 111 }; 112 113 static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = { 114 DDP_COMPONENT_OVL0, 115 DDP_COMPONENT_COLOR0, 116 DDP_COMPONENT_CCORR, 117 DDP_COMPONENT_AAL0, 118 DDP_COMPONENT_GAMMA, 119 DDP_COMPONENT_DITHER, 120 DDP_COMPONENT_RDMA0, 121 DDP_COMPONENT_DSI0, 122 }; 123 124 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 125 DDP_COMPONENT_OVL0, 126 DDP_COMPONENT_COLOR0, 127 DDP_COMPONENT_AAL0, 128 DDP_COMPONENT_OD0, 129 DDP_COMPONENT_RDMA0, 130 DDP_COMPONENT_UFOE, 131 DDP_COMPONENT_DSI0, 132 DDP_COMPONENT_PWM0, 133 }; 134 135 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 136 DDP_COMPONENT_OVL1, 137 DDP_COMPONENT_COLOR1, 138 DDP_COMPONENT_GAMMA, 139 DDP_COMPONENT_RDMA1, 140 DDP_COMPONENT_DPI0, 141 }; 142 143 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { 144 DDP_COMPONENT_OVL0, 145 DDP_COMPONENT_OVL_2L0, 146 DDP_COMPONENT_RDMA0, 147 DDP_COMPONENT_COLOR0, 148 DDP_COMPONENT_CCORR, 149 DDP_COMPONENT_AAL0, 150 DDP_COMPONENT_GAMMA, 151 DDP_COMPONENT_DITHER, 152 DDP_COMPONENT_DSI0, 153 }; 154 155 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { 156 DDP_COMPONENT_OVL_2L1, 157 DDP_COMPONENT_RDMA1, 158 DDP_COMPONENT_DPI0, 159 }; 160 161 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 162 .main_path = mt2701_mtk_ddp_main, 163 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 164 .ext_path = mt2701_mtk_ddp_ext, 165 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 166 .shadow_register = true, 167 }; 168 169 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 170 .main_path = mt7623_mtk_ddp_main, 171 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 172 .ext_path = mt7623_mtk_ddp_ext, 173 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 174 .shadow_register = true, 175 }; 176 177 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 178 .main_path = mt2712_mtk_ddp_main, 179 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 180 .ext_path = mt2712_mtk_ddp_ext, 181 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 182 .third_path = mt2712_mtk_ddp_third, 183 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 184 }; 185 186 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 187 .main_path = mt8167_mtk_ddp_main, 188 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 189 }; 190 191 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 192 .main_path = mt8173_mtk_ddp_main, 193 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 194 .ext_path = mt8173_mtk_ddp_ext, 195 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 196 }; 197 198 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 199 .main_path = mt8183_mtk_ddp_main, 200 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 201 .ext_path = mt8183_mtk_ddp_ext, 202 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 203 }; 204 205 static int mtk_drm_kms_init(struct drm_device *drm) 206 { 207 struct mtk_drm_private *private = drm->dev_private; 208 struct platform_device *pdev; 209 struct device_node *np; 210 struct device *dma_dev; 211 int ret; 212 213 if (!iommu_present(&platform_bus_type)) 214 return -EPROBE_DEFER; 215 216 pdev = of_find_device_by_node(private->mutex_node); 217 if (!pdev) { 218 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", 219 private->mutex_node); 220 of_node_put(private->mutex_node); 221 return -EPROBE_DEFER; 222 } 223 private->mutex_dev = &pdev->dev; 224 225 ret = drmm_mode_config_init(drm); 226 if (ret) 227 goto put_mutex_dev; 228 229 drm->mode_config.min_width = 64; 230 drm->mode_config.min_height = 64; 231 232 /* 233 * set max width and height as default value(4096x4096). 234 * this value would be used to check framebuffer size limitation 235 * at drm_mode_addfb(). 236 */ 237 drm->mode_config.max_width = 4096; 238 drm->mode_config.max_height = 4096; 239 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 240 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 241 242 ret = component_bind_all(drm->dev, drm); 243 if (ret) 244 goto put_mutex_dev; 245 246 /* 247 * We currently support two fixed data streams, each optional, 248 * and each statically assigned to a crtc: 249 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 250 */ 251 ret = mtk_drm_crtc_create(drm, private->data->main_path, 252 private->data->main_len); 253 if (ret < 0) 254 goto err_component_unbind; 255 /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */ 256 ret = mtk_drm_crtc_create(drm, private->data->ext_path, 257 private->data->ext_len); 258 if (ret < 0) 259 goto err_component_unbind; 260 261 ret = mtk_drm_crtc_create(drm, private->data->third_path, 262 private->data->third_len); 263 if (ret < 0) 264 goto err_component_unbind; 265 266 /* Use OVL device for all DMA memory allocations */ 267 np = private->comp_node[private->data->main_path[0]] ?: 268 private->comp_node[private->data->ext_path[0]]; 269 pdev = of_find_device_by_node(np); 270 if (!pdev) { 271 ret = -ENODEV; 272 dev_err(drm->dev, "Need at least one OVL device\n"); 273 goto err_component_unbind; 274 } 275 276 dma_dev = &pdev->dev; 277 private->dma_dev = dma_dev; 278 279 /* 280 * Configure the DMA segment size to make sure we get contiguous IOVA 281 * when importing PRIME buffers. 282 */ 283 ret = dma_set_max_seg_size(dma_dev, UINT_MAX); 284 if (ret) { 285 dev_err(dma_dev, "Failed to set DMA segment size\n"); 286 goto err_component_unbind; 287 } 288 289 ret = drm_vblank_init(drm, MAX_CRTC); 290 if (ret < 0) 291 goto err_component_unbind; 292 293 drm_kms_helper_poll_init(drm); 294 drm_mode_config_reset(drm); 295 296 return 0; 297 298 err_component_unbind: 299 component_unbind_all(drm->dev, drm); 300 put_mutex_dev: 301 put_device(private->mutex_dev); 302 return ret; 303 } 304 305 static void mtk_drm_kms_deinit(struct drm_device *drm) 306 { 307 drm_kms_helper_poll_fini(drm); 308 drm_atomic_helper_shutdown(drm); 309 310 component_unbind_all(drm->dev, drm); 311 } 312 313 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 314 315 /* 316 * We need to override this because the device used to import the memory is 317 * not dev->dev, as drm_gem_prime_import() expects. 318 */ 319 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev, 320 struct dma_buf *dma_buf) 321 { 322 struct mtk_drm_private *private = dev->dev_private; 323 324 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 325 } 326 327 static const struct drm_driver mtk_drm_driver = { 328 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 329 330 .dumb_create = mtk_drm_gem_dumb_create, 331 332 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 333 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 334 .gem_prime_import = mtk_drm_gem_prime_import, 335 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 336 .gem_prime_mmap = drm_gem_prime_mmap, 337 .fops = &mtk_drm_fops, 338 339 .name = DRIVER_NAME, 340 .desc = DRIVER_DESC, 341 .date = DRIVER_DATE, 342 .major = DRIVER_MAJOR, 343 .minor = DRIVER_MINOR, 344 }; 345 346 static int compare_of(struct device *dev, void *data) 347 { 348 return dev->of_node == data; 349 } 350 351 static int mtk_drm_bind(struct device *dev) 352 { 353 struct mtk_drm_private *private = dev_get_drvdata(dev); 354 struct drm_device *drm; 355 int ret; 356 357 drm = drm_dev_alloc(&mtk_drm_driver, dev); 358 if (IS_ERR(drm)) 359 return PTR_ERR(drm); 360 361 drm->dev_private = private; 362 private->drm = drm; 363 364 ret = mtk_drm_kms_init(drm); 365 if (ret < 0) 366 goto err_free; 367 368 ret = drm_dev_register(drm, 0); 369 if (ret < 0) 370 goto err_deinit; 371 372 drm_fbdev_generic_setup(drm, 32); 373 374 return 0; 375 376 err_deinit: 377 mtk_drm_kms_deinit(drm); 378 err_free: 379 drm_dev_put(drm); 380 return ret; 381 } 382 383 static void mtk_drm_unbind(struct device *dev) 384 { 385 struct mtk_drm_private *private = dev_get_drvdata(dev); 386 387 drm_dev_unregister(private->drm); 388 mtk_drm_kms_deinit(private->drm); 389 drm_dev_put(private->drm); 390 private->num_pipes = 0; 391 private->drm = NULL; 392 } 393 394 static const struct component_master_ops mtk_drm_ops = { 395 .bind = mtk_drm_bind, 396 .unbind = mtk_drm_unbind, 397 }; 398 399 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 400 { .compatible = "mediatek,mt2701-disp-ovl", 401 .data = (void *)MTK_DISP_OVL }, 402 { .compatible = "mediatek,mt8167-disp-ovl", 403 .data = (void *)MTK_DISP_OVL }, 404 { .compatible = "mediatek,mt8173-disp-ovl", 405 .data = (void *)MTK_DISP_OVL }, 406 { .compatible = "mediatek,mt8183-disp-ovl", 407 .data = (void *)MTK_DISP_OVL }, 408 { .compatible = "mediatek,mt8183-disp-ovl-2l", 409 .data = (void *)MTK_DISP_OVL_2L }, 410 { .compatible = "mediatek,mt2701-disp-rdma", 411 .data = (void *)MTK_DISP_RDMA }, 412 { .compatible = "mediatek,mt8167-disp-rdma", 413 .data = (void *)MTK_DISP_RDMA }, 414 { .compatible = "mediatek,mt8173-disp-rdma", 415 .data = (void *)MTK_DISP_RDMA }, 416 { .compatible = "mediatek,mt8183-disp-rdma", 417 .data = (void *)MTK_DISP_RDMA }, 418 { .compatible = "mediatek,mt8173-disp-wdma", 419 .data = (void *)MTK_DISP_WDMA }, 420 { .compatible = "mediatek,mt8167-disp-ccorr", 421 .data = (void *)MTK_DISP_CCORR }, 422 { .compatible = "mediatek,mt8183-disp-ccorr", 423 .data = (void *)MTK_DISP_CCORR }, 424 { .compatible = "mediatek,mt2701-disp-color", 425 .data = (void *)MTK_DISP_COLOR }, 426 { .compatible = "mediatek,mt8167-disp-color", 427 .data = (void *)MTK_DISP_COLOR }, 428 { .compatible = "mediatek,mt8173-disp-color", 429 .data = (void *)MTK_DISP_COLOR }, 430 { .compatible = "mediatek,mt8167-disp-aal", 431 .data = (void *)MTK_DISP_AAL}, 432 { .compatible = "mediatek,mt8173-disp-aal", 433 .data = (void *)MTK_DISP_AAL}, 434 { .compatible = "mediatek,mt8183-disp-aal", 435 .data = (void *)MTK_DISP_AAL}, 436 { .compatible = "mediatek,mt8167-disp-gamma", 437 .data = (void *)MTK_DISP_GAMMA, }, 438 { .compatible = "mediatek,mt8173-disp-gamma", 439 .data = (void *)MTK_DISP_GAMMA, }, 440 { .compatible = "mediatek,mt8183-disp-gamma", 441 .data = (void *)MTK_DISP_GAMMA, }, 442 { .compatible = "mediatek,mt8167-disp-dither", 443 .data = (void *)MTK_DISP_DITHER }, 444 { .compatible = "mediatek,mt8183-disp-dither", 445 .data = (void *)MTK_DISP_DITHER }, 446 { .compatible = "mediatek,mt8173-disp-ufoe", 447 .data = (void *)MTK_DISP_UFOE }, 448 { .compatible = "mediatek,mt2701-dsi", 449 .data = (void *)MTK_DSI }, 450 { .compatible = "mediatek,mt8167-dsi", 451 .data = (void *)MTK_DSI }, 452 { .compatible = "mediatek,mt8173-dsi", 453 .data = (void *)MTK_DSI }, 454 { .compatible = "mediatek,mt8183-dsi", 455 .data = (void *)MTK_DSI }, 456 { .compatible = "mediatek,mt2701-dpi", 457 .data = (void *)MTK_DPI }, 458 { .compatible = "mediatek,mt8173-dpi", 459 .data = (void *)MTK_DPI }, 460 { .compatible = "mediatek,mt8183-dpi", 461 .data = (void *)MTK_DPI }, 462 { .compatible = "mediatek,mt2701-disp-mutex", 463 .data = (void *)MTK_DISP_MUTEX }, 464 { .compatible = "mediatek,mt2712-disp-mutex", 465 .data = (void *)MTK_DISP_MUTEX }, 466 { .compatible = "mediatek,mt8167-disp-mutex", 467 .data = (void *)MTK_DISP_MUTEX }, 468 { .compatible = "mediatek,mt8173-disp-mutex", 469 .data = (void *)MTK_DISP_MUTEX }, 470 { .compatible = "mediatek,mt8183-disp-mutex", 471 .data = (void *)MTK_DISP_MUTEX }, 472 { .compatible = "mediatek,mt2701-disp-pwm", 473 .data = (void *)MTK_DISP_BLS }, 474 { .compatible = "mediatek,mt8167-disp-pwm", 475 .data = (void *)MTK_DISP_PWM }, 476 { .compatible = "mediatek,mt8173-disp-pwm", 477 .data = (void *)MTK_DISP_PWM }, 478 { .compatible = "mediatek,mt8173-disp-od", 479 .data = (void *)MTK_DISP_OD }, 480 { } 481 }; 482 483 static const struct of_device_id mtk_drm_of_ids[] = { 484 { .compatible = "mediatek,mt2701-mmsys", 485 .data = &mt2701_mmsys_driver_data}, 486 { .compatible = "mediatek,mt7623-mmsys", 487 .data = &mt7623_mmsys_driver_data}, 488 { .compatible = "mediatek,mt2712-mmsys", 489 .data = &mt2712_mmsys_driver_data}, 490 { .compatible = "mediatek,mt8167-mmsys", 491 .data = &mt8167_mmsys_driver_data}, 492 { .compatible = "mediatek,mt8173-mmsys", 493 .data = &mt8173_mmsys_driver_data}, 494 { .compatible = "mediatek,mt8183-mmsys", 495 .data = &mt8183_mmsys_driver_data}, 496 { } 497 }; 498 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 499 500 static int mtk_drm_probe(struct platform_device *pdev) 501 { 502 struct device *dev = &pdev->dev; 503 struct device_node *phandle = dev->parent->of_node; 504 const struct of_device_id *of_id; 505 struct mtk_drm_private *private; 506 struct device_node *node; 507 struct component_match *match = NULL; 508 int ret; 509 int i; 510 511 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 512 if (!private) 513 return -ENOMEM; 514 515 private->mmsys_dev = dev->parent; 516 if (!private->mmsys_dev) { 517 dev_err(dev, "Failed to get MMSYS device\n"); 518 return -ENODEV; 519 } 520 521 of_id = of_match_node(mtk_drm_of_ids, phandle); 522 if (!of_id) 523 return -ENODEV; 524 525 private->data = of_id->data; 526 527 /* Iterate over sibling DISP function blocks */ 528 for_each_child_of_node(phandle->parent, node) { 529 const struct of_device_id *of_id; 530 enum mtk_ddp_comp_type comp_type; 531 int comp_id; 532 533 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 534 if (!of_id) 535 continue; 536 537 if (!of_device_is_available(node)) { 538 dev_dbg(dev, "Skipping disabled component %pOF\n", 539 node); 540 continue; 541 } 542 543 comp_type = (enum mtk_ddp_comp_type)of_id->data; 544 545 if (comp_type == MTK_DISP_MUTEX) { 546 private->mutex_node = of_node_get(node); 547 continue; 548 } 549 550 comp_id = mtk_ddp_comp_get_id(node, comp_type); 551 if (comp_id < 0) { 552 dev_warn(dev, "Skipping unknown component %pOF\n", 553 node); 554 continue; 555 } 556 557 private->comp_node[comp_id] = of_node_get(node); 558 559 /* 560 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI 561 * blocks have separate component platform drivers and initialize their own 562 * DDP component structure. The others are initialized here. 563 */ 564 if (comp_type == MTK_DISP_AAL || 565 comp_type == MTK_DISP_CCORR || 566 comp_type == MTK_DISP_COLOR || 567 comp_type == MTK_DISP_GAMMA || 568 comp_type == MTK_DISP_OVL || 569 comp_type == MTK_DISP_OVL_2L || 570 comp_type == MTK_DISP_RDMA || 571 comp_type == MTK_DSI || 572 comp_type == MTK_DPI) { 573 dev_info(dev, "Adding component match for %pOF\n", 574 node); 575 drm_of_component_match_add(dev, &match, compare_of, 576 node); 577 } 578 579 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 580 if (ret) { 581 of_node_put(node); 582 goto err_node; 583 } 584 } 585 586 if (!private->mutex_node) { 587 dev_err(dev, "Failed to find disp-mutex node\n"); 588 ret = -ENODEV; 589 goto err_node; 590 } 591 592 pm_runtime_enable(dev); 593 594 platform_set_drvdata(pdev, private); 595 596 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 597 if (ret) 598 goto err_pm; 599 600 return 0; 601 602 err_pm: 603 pm_runtime_disable(dev); 604 err_node: 605 of_node_put(private->mutex_node); 606 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) { 607 of_node_put(private->comp_node[i]); 608 if (private->ddp_comp[i].larb_dev) 609 put_device(private->ddp_comp[i].larb_dev); 610 } 611 return ret; 612 } 613 614 static int mtk_drm_remove(struct platform_device *pdev) 615 { 616 struct mtk_drm_private *private = platform_get_drvdata(pdev); 617 int i; 618 619 component_master_del(&pdev->dev, &mtk_drm_ops); 620 pm_runtime_disable(&pdev->dev); 621 of_node_put(private->mutex_node); 622 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 623 of_node_put(private->comp_node[i]); 624 625 return 0; 626 } 627 628 #ifdef CONFIG_PM_SLEEP 629 static int mtk_drm_sys_suspend(struct device *dev) 630 { 631 struct mtk_drm_private *private = dev_get_drvdata(dev); 632 struct drm_device *drm = private->drm; 633 int ret; 634 635 ret = drm_mode_config_helper_suspend(drm); 636 637 return ret; 638 } 639 640 static int mtk_drm_sys_resume(struct device *dev) 641 { 642 struct mtk_drm_private *private = dev_get_drvdata(dev); 643 struct drm_device *drm = private->drm; 644 int ret; 645 646 ret = drm_mode_config_helper_resume(drm); 647 648 return ret; 649 } 650 #endif 651 652 static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, 653 mtk_drm_sys_resume); 654 655 static struct platform_driver mtk_drm_platform_driver = { 656 .probe = mtk_drm_probe, 657 .remove = mtk_drm_remove, 658 .driver = { 659 .name = "mediatek-drm", 660 .pm = &mtk_drm_pm_ops, 661 }, 662 }; 663 664 static struct platform_driver * const mtk_drm_drivers[] = { 665 &mtk_disp_aal_driver, 666 &mtk_disp_ccorr_driver, 667 &mtk_disp_color_driver, 668 &mtk_disp_gamma_driver, 669 &mtk_disp_ovl_driver, 670 &mtk_disp_rdma_driver, 671 &mtk_dpi_driver, 672 &mtk_drm_platform_driver, 673 &mtk_dsi_driver, 674 }; 675 676 static int __init mtk_drm_init(void) 677 { 678 return platform_register_drivers(mtk_drm_drivers, 679 ARRAY_SIZE(mtk_drm_drivers)); 680 } 681 682 static void __exit mtk_drm_exit(void) 683 { 684 platform_unregister_drivers(mtk_drm_drivers, 685 ARRAY_SIZE(mtk_drm_drivers)); 686 } 687 688 module_init(mtk_drm_init); 689 module_exit(mtk_drm_exit); 690 691 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 692 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 693 MODULE_LICENSE("GPL v2"); 694