1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of_address.h> 11 #include <linux/of_platform.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_fb_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 27 #include "mtk_drm_crtc.h" 28 #include "mtk_drm_ddp_comp.h" 29 #include "mtk_drm_drv.h" 30 #include "mtk_drm_gem.h" 31 32 #define DRIVER_NAME "mediatek" 33 #define DRIVER_DESC "Mediatek SoC DRM" 34 #define DRIVER_DATE "20150513" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 38 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 39 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 40 }; 41 42 static struct drm_framebuffer * 43 mtk_drm_mode_fb_create(struct drm_device *dev, 44 struct drm_file *file, 45 const struct drm_mode_fb_cmd2 *cmd) 46 { 47 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 48 49 if (info->num_planes != 1) 50 return ERR_PTR(-EINVAL); 51 52 return drm_gem_fb_create(dev, file, cmd); 53 } 54 55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 56 .fb_create = mtk_drm_mode_fb_create, 57 .atomic_check = drm_atomic_helper_check, 58 .atomic_commit = drm_atomic_helper_commit, 59 }; 60 61 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { 62 DDP_COMPONENT_OVL0, 63 DDP_COMPONENT_RDMA0, 64 DDP_COMPONENT_COLOR0, 65 DDP_COMPONENT_BLS, 66 DDP_COMPONENT_DSI0, 67 }; 68 69 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { 70 DDP_COMPONENT_RDMA1, 71 DDP_COMPONENT_DPI0, 72 }; 73 74 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = { 75 DDP_COMPONENT_OVL0, 76 DDP_COMPONENT_RDMA0, 77 DDP_COMPONENT_COLOR0, 78 DDP_COMPONENT_BLS, 79 DDP_COMPONENT_DPI0, 80 }; 81 82 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = { 83 DDP_COMPONENT_RDMA1, 84 DDP_COMPONENT_DSI0, 85 }; 86 87 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { 88 DDP_COMPONENT_OVL0, 89 DDP_COMPONENT_COLOR0, 90 DDP_COMPONENT_AAL0, 91 DDP_COMPONENT_OD0, 92 DDP_COMPONENT_RDMA0, 93 DDP_COMPONENT_DPI0, 94 DDP_COMPONENT_PWM0, 95 }; 96 97 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 98 DDP_COMPONENT_OVL1, 99 DDP_COMPONENT_COLOR1, 100 DDP_COMPONENT_AAL1, 101 DDP_COMPONENT_OD1, 102 DDP_COMPONENT_RDMA1, 103 DDP_COMPONENT_DPI1, 104 DDP_COMPONENT_PWM1, 105 }; 106 107 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 108 DDP_COMPONENT_RDMA2, 109 DDP_COMPONENT_DSI3, 110 DDP_COMPONENT_PWM2, 111 }; 112 113 static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = { 114 DDP_COMPONENT_OVL0, 115 DDP_COMPONENT_COLOR0, 116 DDP_COMPONENT_CCORR, 117 DDP_COMPONENT_AAL0, 118 DDP_COMPONENT_GAMMA, 119 DDP_COMPONENT_DITHER, 120 DDP_COMPONENT_RDMA0, 121 DDP_COMPONENT_DSI0, 122 }; 123 124 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 125 DDP_COMPONENT_OVL0, 126 DDP_COMPONENT_COLOR0, 127 DDP_COMPONENT_AAL0, 128 DDP_COMPONENT_OD0, 129 DDP_COMPONENT_RDMA0, 130 DDP_COMPONENT_UFOE, 131 DDP_COMPONENT_DSI0, 132 DDP_COMPONENT_PWM0, 133 }; 134 135 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 136 DDP_COMPONENT_OVL1, 137 DDP_COMPONENT_COLOR1, 138 DDP_COMPONENT_GAMMA, 139 DDP_COMPONENT_RDMA1, 140 DDP_COMPONENT_DPI0, 141 }; 142 143 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { 144 DDP_COMPONENT_OVL0, 145 DDP_COMPONENT_OVL_2L0, 146 DDP_COMPONENT_RDMA0, 147 DDP_COMPONENT_COLOR0, 148 DDP_COMPONENT_CCORR, 149 DDP_COMPONENT_AAL0, 150 DDP_COMPONENT_GAMMA, 151 DDP_COMPONENT_DITHER, 152 DDP_COMPONENT_DSI0, 153 }; 154 155 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { 156 DDP_COMPONENT_OVL_2L1, 157 DDP_COMPONENT_RDMA1, 158 DDP_COMPONENT_DPI0, 159 }; 160 161 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 162 .main_path = mt2701_mtk_ddp_main, 163 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 164 .ext_path = mt2701_mtk_ddp_ext, 165 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 166 .shadow_register = true, 167 }; 168 169 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 170 .main_path = mt7623_mtk_ddp_main, 171 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 172 .ext_path = mt7623_mtk_ddp_ext, 173 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 174 .shadow_register = true, 175 }; 176 177 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 178 .main_path = mt2712_mtk_ddp_main, 179 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 180 .ext_path = mt2712_mtk_ddp_ext, 181 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 182 .third_path = mt2712_mtk_ddp_third, 183 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 184 }; 185 186 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 187 .main_path = mt8167_mtk_ddp_main, 188 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 189 }; 190 191 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 192 .main_path = mt8173_mtk_ddp_main, 193 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 194 .ext_path = mt8173_mtk_ddp_ext, 195 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 196 }; 197 198 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 199 .main_path = mt8183_mtk_ddp_main, 200 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 201 .ext_path = mt8183_mtk_ddp_ext, 202 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 203 }; 204 205 static int mtk_drm_kms_init(struct drm_device *drm) 206 { 207 struct mtk_drm_private *private = drm->dev_private; 208 struct platform_device *pdev; 209 struct device_node *np; 210 struct device *dma_dev; 211 int ret; 212 213 if (drm_firmware_drivers_only()) 214 return -ENODEV; 215 216 if (!iommu_present(&platform_bus_type)) 217 return -EPROBE_DEFER; 218 219 pdev = of_find_device_by_node(private->mutex_node); 220 if (!pdev) { 221 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", 222 private->mutex_node); 223 of_node_put(private->mutex_node); 224 return -EPROBE_DEFER; 225 } 226 private->mutex_dev = &pdev->dev; 227 228 ret = drmm_mode_config_init(drm); 229 if (ret) 230 goto put_mutex_dev; 231 232 drm->mode_config.min_width = 64; 233 drm->mode_config.min_height = 64; 234 235 /* 236 * set max width and height as default value(4096x4096). 237 * this value would be used to check framebuffer size limitation 238 * at drm_mode_addfb(). 239 */ 240 drm->mode_config.max_width = 4096; 241 drm->mode_config.max_height = 4096; 242 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 243 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 244 245 ret = component_bind_all(drm->dev, drm); 246 if (ret) 247 goto put_mutex_dev; 248 249 /* 250 * We currently support two fixed data streams, each optional, 251 * and each statically assigned to a crtc: 252 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 253 */ 254 ret = mtk_drm_crtc_create(drm, private->data->main_path, 255 private->data->main_len); 256 if (ret < 0) 257 goto err_component_unbind; 258 /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */ 259 ret = mtk_drm_crtc_create(drm, private->data->ext_path, 260 private->data->ext_len); 261 if (ret < 0) 262 goto err_component_unbind; 263 264 ret = mtk_drm_crtc_create(drm, private->data->third_path, 265 private->data->third_len); 266 if (ret < 0) 267 goto err_component_unbind; 268 269 /* Use OVL device for all DMA memory allocations */ 270 np = private->comp_node[private->data->main_path[0]] ?: 271 private->comp_node[private->data->ext_path[0]]; 272 pdev = of_find_device_by_node(np); 273 if (!pdev) { 274 ret = -ENODEV; 275 dev_err(drm->dev, "Need at least one OVL device\n"); 276 goto err_component_unbind; 277 } 278 279 dma_dev = &pdev->dev; 280 private->dma_dev = dma_dev; 281 282 /* 283 * Configure the DMA segment size to make sure we get contiguous IOVA 284 * when importing PRIME buffers. 285 */ 286 ret = dma_set_max_seg_size(dma_dev, UINT_MAX); 287 if (ret) { 288 dev_err(dma_dev, "Failed to set DMA segment size\n"); 289 goto err_component_unbind; 290 } 291 292 ret = drm_vblank_init(drm, MAX_CRTC); 293 if (ret < 0) 294 goto err_component_unbind; 295 296 drm_kms_helper_poll_init(drm); 297 drm_mode_config_reset(drm); 298 299 return 0; 300 301 err_component_unbind: 302 component_unbind_all(drm->dev, drm); 303 put_mutex_dev: 304 put_device(private->mutex_dev); 305 return ret; 306 } 307 308 static void mtk_drm_kms_deinit(struct drm_device *drm) 309 { 310 drm_kms_helper_poll_fini(drm); 311 drm_atomic_helper_shutdown(drm); 312 313 component_unbind_all(drm->dev, drm); 314 } 315 316 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 317 318 /* 319 * We need to override this because the device used to import the memory is 320 * not dev->dev, as drm_gem_prime_import() expects. 321 */ 322 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev, 323 struct dma_buf *dma_buf) 324 { 325 struct mtk_drm_private *private = dev->dev_private; 326 327 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 328 } 329 330 static const struct drm_driver mtk_drm_driver = { 331 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 332 333 .dumb_create = mtk_drm_gem_dumb_create, 334 335 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 336 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 337 .gem_prime_import = mtk_drm_gem_prime_import, 338 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 339 .gem_prime_mmap = drm_gem_prime_mmap, 340 .fops = &mtk_drm_fops, 341 342 .name = DRIVER_NAME, 343 .desc = DRIVER_DESC, 344 .date = DRIVER_DATE, 345 .major = DRIVER_MAJOR, 346 .minor = DRIVER_MINOR, 347 }; 348 349 static int compare_of(struct device *dev, void *data) 350 { 351 return dev->of_node == data; 352 } 353 354 static int mtk_drm_bind(struct device *dev) 355 { 356 struct mtk_drm_private *private = dev_get_drvdata(dev); 357 struct drm_device *drm; 358 int ret; 359 360 drm = drm_dev_alloc(&mtk_drm_driver, dev); 361 if (IS_ERR(drm)) 362 return PTR_ERR(drm); 363 364 drm->dev_private = private; 365 private->drm = drm; 366 367 ret = mtk_drm_kms_init(drm); 368 if (ret < 0) 369 goto err_free; 370 371 ret = drm_dev_register(drm, 0); 372 if (ret < 0) 373 goto err_deinit; 374 375 drm_fbdev_generic_setup(drm, 32); 376 377 return 0; 378 379 err_deinit: 380 mtk_drm_kms_deinit(drm); 381 err_free: 382 drm_dev_put(drm); 383 return ret; 384 } 385 386 static void mtk_drm_unbind(struct device *dev) 387 { 388 struct mtk_drm_private *private = dev_get_drvdata(dev); 389 390 drm_dev_unregister(private->drm); 391 mtk_drm_kms_deinit(private->drm); 392 drm_dev_put(private->drm); 393 private->num_pipes = 0; 394 private->drm = NULL; 395 } 396 397 static const struct component_master_ops mtk_drm_ops = { 398 .bind = mtk_drm_bind, 399 .unbind = mtk_drm_unbind, 400 }; 401 402 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 403 { .compatible = "mediatek,mt2701-disp-ovl", 404 .data = (void *)MTK_DISP_OVL }, 405 { .compatible = "mediatek,mt8167-disp-ovl", 406 .data = (void *)MTK_DISP_OVL }, 407 { .compatible = "mediatek,mt8173-disp-ovl", 408 .data = (void *)MTK_DISP_OVL }, 409 { .compatible = "mediatek,mt8183-disp-ovl", 410 .data = (void *)MTK_DISP_OVL }, 411 { .compatible = "mediatek,mt8183-disp-ovl-2l", 412 .data = (void *)MTK_DISP_OVL_2L }, 413 { .compatible = "mediatek,mt2701-disp-rdma", 414 .data = (void *)MTK_DISP_RDMA }, 415 { .compatible = "mediatek,mt8167-disp-rdma", 416 .data = (void *)MTK_DISP_RDMA }, 417 { .compatible = "mediatek,mt8173-disp-rdma", 418 .data = (void *)MTK_DISP_RDMA }, 419 { .compatible = "mediatek,mt8183-disp-rdma", 420 .data = (void *)MTK_DISP_RDMA }, 421 { .compatible = "mediatek,mt8173-disp-wdma", 422 .data = (void *)MTK_DISP_WDMA }, 423 { .compatible = "mediatek,mt8167-disp-ccorr", 424 .data = (void *)MTK_DISP_CCORR }, 425 { .compatible = "mediatek,mt8183-disp-ccorr", 426 .data = (void *)MTK_DISP_CCORR }, 427 { .compatible = "mediatek,mt2701-disp-color", 428 .data = (void *)MTK_DISP_COLOR }, 429 { .compatible = "mediatek,mt8167-disp-color", 430 .data = (void *)MTK_DISP_COLOR }, 431 { .compatible = "mediatek,mt8173-disp-color", 432 .data = (void *)MTK_DISP_COLOR }, 433 { .compatible = "mediatek,mt8167-disp-aal", 434 .data = (void *)MTK_DISP_AAL}, 435 { .compatible = "mediatek,mt8173-disp-aal", 436 .data = (void *)MTK_DISP_AAL}, 437 { .compatible = "mediatek,mt8183-disp-aal", 438 .data = (void *)MTK_DISP_AAL}, 439 { .compatible = "mediatek,mt8167-disp-gamma", 440 .data = (void *)MTK_DISP_GAMMA, }, 441 { .compatible = "mediatek,mt8173-disp-gamma", 442 .data = (void *)MTK_DISP_GAMMA, }, 443 { .compatible = "mediatek,mt8183-disp-gamma", 444 .data = (void *)MTK_DISP_GAMMA, }, 445 { .compatible = "mediatek,mt8167-disp-dither", 446 .data = (void *)MTK_DISP_DITHER }, 447 { .compatible = "mediatek,mt8183-disp-dither", 448 .data = (void *)MTK_DISP_DITHER }, 449 { .compatible = "mediatek,mt8173-disp-ufoe", 450 .data = (void *)MTK_DISP_UFOE }, 451 { .compatible = "mediatek,mt2701-dsi", 452 .data = (void *)MTK_DSI }, 453 { .compatible = "mediatek,mt8167-dsi", 454 .data = (void *)MTK_DSI }, 455 { .compatible = "mediatek,mt8173-dsi", 456 .data = (void *)MTK_DSI }, 457 { .compatible = "mediatek,mt8183-dsi", 458 .data = (void *)MTK_DSI }, 459 { .compatible = "mediatek,mt2701-dpi", 460 .data = (void *)MTK_DPI }, 461 { .compatible = "mediatek,mt8173-dpi", 462 .data = (void *)MTK_DPI }, 463 { .compatible = "mediatek,mt8183-dpi", 464 .data = (void *)MTK_DPI }, 465 { .compatible = "mediatek,mt2701-disp-mutex", 466 .data = (void *)MTK_DISP_MUTEX }, 467 { .compatible = "mediatek,mt2712-disp-mutex", 468 .data = (void *)MTK_DISP_MUTEX }, 469 { .compatible = "mediatek,mt8167-disp-mutex", 470 .data = (void *)MTK_DISP_MUTEX }, 471 { .compatible = "mediatek,mt8173-disp-mutex", 472 .data = (void *)MTK_DISP_MUTEX }, 473 { .compatible = "mediatek,mt8183-disp-mutex", 474 .data = (void *)MTK_DISP_MUTEX }, 475 { .compatible = "mediatek,mt2701-disp-pwm", 476 .data = (void *)MTK_DISP_BLS }, 477 { .compatible = "mediatek,mt8167-disp-pwm", 478 .data = (void *)MTK_DISP_PWM }, 479 { .compatible = "mediatek,mt8173-disp-pwm", 480 .data = (void *)MTK_DISP_PWM }, 481 { .compatible = "mediatek,mt8173-disp-od", 482 .data = (void *)MTK_DISP_OD }, 483 { } 484 }; 485 486 static const struct of_device_id mtk_drm_of_ids[] = { 487 { .compatible = "mediatek,mt2701-mmsys", 488 .data = &mt2701_mmsys_driver_data}, 489 { .compatible = "mediatek,mt7623-mmsys", 490 .data = &mt7623_mmsys_driver_data}, 491 { .compatible = "mediatek,mt2712-mmsys", 492 .data = &mt2712_mmsys_driver_data}, 493 { .compatible = "mediatek,mt8167-mmsys", 494 .data = &mt8167_mmsys_driver_data}, 495 { .compatible = "mediatek,mt8173-mmsys", 496 .data = &mt8173_mmsys_driver_data}, 497 { .compatible = "mediatek,mt8183-mmsys", 498 .data = &mt8183_mmsys_driver_data}, 499 { } 500 }; 501 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 502 503 static int mtk_drm_probe(struct platform_device *pdev) 504 { 505 struct device *dev = &pdev->dev; 506 struct device_node *phandle = dev->parent->of_node; 507 const struct of_device_id *of_id; 508 struct mtk_drm_private *private; 509 struct device_node *node; 510 struct component_match *match = NULL; 511 int ret; 512 int i; 513 514 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 515 if (!private) 516 return -ENOMEM; 517 518 private->mmsys_dev = dev->parent; 519 if (!private->mmsys_dev) { 520 dev_err(dev, "Failed to get MMSYS device\n"); 521 return -ENODEV; 522 } 523 524 of_id = of_match_node(mtk_drm_of_ids, phandle); 525 if (!of_id) 526 return -ENODEV; 527 528 private->data = of_id->data; 529 530 /* Iterate over sibling DISP function blocks */ 531 for_each_child_of_node(phandle->parent, node) { 532 const struct of_device_id *of_id; 533 enum mtk_ddp_comp_type comp_type; 534 int comp_id; 535 536 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 537 if (!of_id) 538 continue; 539 540 if (!of_device_is_available(node)) { 541 dev_dbg(dev, "Skipping disabled component %pOF\n", 542 node); 543 continue; 544 } 545 546 comp_type = (enum mtk_ddp_comp_type)of_id->data; 547 548 if (comp_type == MTK_DISP_MUTEX) { 549 private->mutex_node = of_node_get(node); 550 continue; 551 } 552 553 comp_id = mtk_ddp_comp_get_id(node, comp_type); 554 if (comp_id < 0) { 555 dev_warn(dev, "Skipping unknown component %pOF\n", 556 node); 557 continue; 558 } 559 560 private->comp_node[comp_id] = of_node_get(node); 561 562 /* 563 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI 564 * blocks have separate component platform drivers and initialize their own 565 * DDP component structure. The others are initialized here. 566 */ 567 if (comp_type == MTK_DISP_AAL || 568 comp_type == MTK_DISP_CCORR || 569 comp_type == MTK_DISP_COLOR || 570 comp_type == MTK_DISP_GAMMA || 571 comp_type == MTK_DISP_OVL || 572 comp_type == MTK_DISP_OVL_2L || 573 comp_type == MTK_DISP_RDMA || 574 comp_type == MTK_DSI || 575 comp_type == MTK_DPI) { 576 dev_info(dev, "Adding component match for %pOF\n", 577 node); 578 drm_of_component_match_add(dev, &match, compare_of, 579 node); 580 } 581 582 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 583 if (ret) { 584 of_node_put(node); 585 goto err_node; 586 } 587 } 588 589 if (!private->mutex_node) { 590 dev_err(dev, "Failed to find disp-mutex node\n"); 591 ret = -ENODEV; 592 goto err_node; 593 } 594 595 pm_runtime_enable(dev); 596 597 platform_set_drvdata(pdev, private); 598 599 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 600 if (ret) 601 goto err_pm; 602 603 return 0; 604 605 err_pm: 606 pm_runtime_disable(dev); 607 err_node: 608 of_node_put(private->mutex_node); 609 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) { 610 of_node_put(private->comp_node[i]); 611 if (private->ddp_comp[i].larb_dev) 612 put_device(private->ddp_comp[i].larb_dev); 613 } 614 return ret; 615 } 616 617 static int mtk_drm_remove(struct platform_device *pdev) 618 { 619 struct mtk_drm_private *private = platform_get_drvdata(pdev); 620 int i; 621 622 component_master_del(&pdev->dev, &mtk_drm_ops); 623 pm_runtime_disable(&pdev->dev); 624 of_node_put(private->mutex_node); 625 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 626 of_node_put(private->comp_node[i]); 627 628 return 0; 629 } 630 631 #ifdef CONFIG_PM_SLEEP 632 static int mtk_drm_sys_suspend(struct device *dev) 633 { 634 struct mtk_drm_private *private = dev_get_drvdata(dev); 635 struct drm_device *drm = private->drm; 636 int ret; 637 638 ret = drm_mode_config_helper_suspend(drm); 639 640 return ret; 641 } 642 643 static int mtk_drm_sys_resume(struct device *dev) 644 { 645 struct mtk_drm_private *private = dev_get_drvdata(dev); 646 struct drm_device *drm = private->drm; 647 int ret; 648 649 ret = drm_mode_config_helper_resume(drm); 650 651 return ret; 652 } 653 #endif 654 655 static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, 656 mtk_drm_sys_resume); 657 658 static struct platform_driver mtk_drm_platform_driver = { 659 .probe = mtk_drm_probe, 660 .remove = mtk_drm_remove, 661 .driver = { 662 .name = "mediatek-drm", 663 .pm = &mtk_drm_pm_ops, 664 }, 665 }; 666 667 static struct platform_driver * const mtk_drm_drivers[] = { 668 &mtk_disp_aal_driver, 669 &mtk_disp_ccorr_driver, 670 &mtk_disp_color_driver, 671 &mtk_disp_gamma_driver, 672 &mtk_disp_ovl_driver, 673 &mtk_disp_rdma_driver, 674 &mtk_dpi_driver, 675 &mtk_drm_platform_driver, 676 &mtk_dsi_driver, 677 }; 678 679 static int __init mtk_drm_init(void) 680 { 681 return platform_register_drivers(mtk_drm_drivers, 682 ARRAY_SIZE(mtk_drm_drivers)); 683 } 684 685 static void __exit mtk_drm_exit(void) 686 { 687 platform_unregister_drivers(mtk_drm_drivers, 688 ARRAY_SIZE(mtk_drm_drivers)); 689 } 690 691 module_init(mtk_drm_init); 692 module_exit(mtk_drm_exit); 693 694 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 695 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 696 MODULE_LICENSE("GPL v2"); 697