1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <drm/drmP.h> 8 #include <drm/drm_atomic.h> 9 #include <drm/drm_atomic_helper.h> 10 #include <drm/drm_fb_helper.h> 11 #include <drm/drm_gem.h> 12 #include <drm/drm_gem_cma_helper.h> 13 #include <drm/drm_of.h> 14 #include <drm/drm_probe_helper.h> 15 #include <linux/component.h> 16 #include <linux/iommu.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/pm_runtime.h> 20 21 #include "mtk_drm_crtc.h" 22 #include "mtk_drm_ddp.h" 23 #include "mtk_drm_ddp_comp.h" 24 #include "mtk_drm_drv.h" 25 #include "mtk_drm_fb.h" 26 #include "mtk_drm_gem.h" 27 28 #define DRIVER_NAME "mediatek" 29 #define DRIVER_DESC "Mediatek SoC DRM" 30 #define DRIVER_DATE "20150513" 31 #define DRIVER_MAJOR 1 32 #define DRIVER_MINOR 0 33 34 static void mtk_atomic_schedule(struct mtk_drm_private *private, 35 struct drm_atomic_state *state) 36 { 37 private->commit.state = state; 38 schedule_work(&private->commit.work); 39 } 40 41 static void mtk_atomic_wait_for_fences(struct drm_atomic_state *state) 42 { 43 struct drm_plane *plane; 44 struct drm_plane_state *new_plane_state; 45 int i; 46 47 for_each_new_plane_in_state(state, plane, new_plane_state, i) 48 mtk_fb_wait(new_plane_state->fb); 49 } 50 51 static void mtk_atomic_complete(struct mtk_drm_private *private, 52 struct drm_atomic_state *state) 53 { 54 struct drm_device *drm = private->drm; 55 56 mtk_atomic_wait_for_fences(state); 57 58 /* 59 * Mediatek drm supports runtime PM, so plane registers cannot be 60 * written when their crtc is disabled. 61 * 62 * The comment for drm_atomic_helper_commit states: 63 * For drivers supporting runtime PM the recommended sequence is 64 * 65 * drm_atomic_helper_commit_modeset_disables(dev, state); 66 * drm_atomic_helper_commit_modeset_enables(dev, state); 67 * drm_atomic_helper_commit_planes(dev, state, 68 * DRM_PLANE_COMMIT_ACTIVE_ONLY); 69 * 70 * See the kerneldoc entries for these three functions for more details. 71 */ 72 drm_atomic_helper_commit_modeset_disables(drm, state); 73 drm_atomic_helper_commit_modeset_enables(drm, state); 74 drm_atomic_helper_commit_planes(drm, state, 75 DRM_PLANE_COMMIT_ACTIVE_ONLY); 76 77 drm_atomic_helper_wait_for_vblanks(drm, state); 78 79 drm_atomic_helper_cleanup_planes(drm, state); 80 drm_atomic_state_put(state); 81 } 82 83 static void mtk_atomic_work(struct work_struct *work) 84 { 85 struct mtk_drm_private *private = container_of(work, 86 struct mtk_drm_private, commit.work); 87 88 mtk_atomic_complete(private, private->commit.state); 89 } 90 91 static int mtk_atomic_commit(struct drm_device *drm, 92 struct drm_atomic_state *state, 93 bool async) 94 { 95 struct mtk_drm_private *private = drm->dev_private; 96 int ret; 97 98 ret = drm_atomic_helper_prepare_planes(drm, state); 99 if (ret) 100 return ret; 101 102 mutex_lock(&private->commit.lock); 103 flush_work(&private->commit.work); 104 105 ret = drm_atomic_helper_swap_state(state, true); 106 if (ret) { 107 mutex_unlock(&private->commit.lock); 108 drm_atomic_helper_cleanup_planes(drm, state); 109 return ret; 110 } 111 112 drm_atomic_state_get(state); 113 if (async) 114 mtk_atomic_schedule(private, state); 115 else 116 mtk_atomic_complete(private, state); 117 118 mutex_unlock(&private->commit.lock); 119 120 return 0; 121 } 122 123 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 124 .fb_create = mtk_drm_mode_fb_create, 125 .atomic_check = drm_atomic_helper_check, 126 .atomic_commit = mtk_atomic_commit, 127 }; 128 129 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { 130 DDP_COMPONENT_OVL0, 131 DDP_COMPONENT_RDMA0, 132 DDP_COMPONENT_COLOR0, 133 DDP_COMPONENT_BLS, 134 DDP_COMPONENT_DSI0, 135 }; 136 137 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { 138 DDP_COMPONENT_RDMA1, 139 DDP_COMPONENT_DPI0, 140 }; 141 142 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { 143 DDP_COMPONENT_OVL0, 144 DDP_COMPONENT_COLOR0, 145 DDP_COMPONENT_AAL0, 146 DDP_COMPONENT_OD0, 147 DDP_COMPONENT_RDMA0, 148 DDP_COMPONENT_DPI0, 149 DDP_COMPONENT_PWM0, 150 }; 151 152 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 153 DDP_COMPONENT_OVL1, 154 DDP_COMPONENT_COLOR1, 155 DDP_COMPONENT_AAL1, 156 DDP_COMPONENT_OD1, 157 DDP_COMPONENT_RDMA1, 158 DDP_COMPONENT_DPI1, 159 DDP_COMPONENT_PWM1, 160 }; 161 162 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 163 DDP_COMPONENT_RDMA2, 164 DDP_COMPONENT_DSI3, 165 DDP_COMPONENT_PWM2, 166 }; 167 168 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 169 DDP_COMPONENT_OVL0, 170 DDP_COMPONENT_COLOR0, 171 DDP_COMPONENT_AAL0, 172 DDP_COMPONENT_OD0, 173 DDP_COMPONENT_RDMA0, 174 DDP_COMPONENT_UFOE, 175 DDP_COMPONENT_DSI0, 176 DDP_COMPONENT_PWM0, 177 }; 178 179 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 180 DDP_COMPONENT_OVL1, 181 DDP_COMPONENT_COLOR1, 182 DDP_COMPONENT_GAMMA, 183 DDP_COMPONENT_RDMA1, 184 DDP_COMPONENT_DPI0, 185 }; 186 187 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 188 .main_path = mt2701_mtk_ddp_main, 189 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 190 .ext_path = mt2701_mtk_ddp_ext, 191 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 192 .shadow_register = true, 193 }; 194 195 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 196 .main_path = mt2712_mtk_ddp_main, 197 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 198 .ext_path = mt2712_mtk_ddp_ext, 199 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 200 .third_path = mt2712_mtk_ddp_third, 201 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 202 }; 203 204 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 205 .main_path = mt8173_mtk_ddp_main, 206 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 207 .ext_path = mt8173_mtk_ddp_ext, 208 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 209 }; 210 211 static int mtk_drm_kms_init(struct drm_device *drm) 212 { 213 struct mtk_drm_private *private = drm->dev_private; 214 struct platform_device *pdev; 215 struct device_node *np; 216 int ret; 217 218 if (!iommu_present(&platform_bus_type)) 219 return -EPROBE_DEFER; 220 221 pdev = of_find_device_by_node(private->mutex_node); 222 if (!pdev) { 223 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", 224 private->mutex_node); 225 of_node_put(private->mutex_node); 226 return -EPROBE_DEFER; 227 } 228 private->mutex_dev = &pdev->dev; 229 230 drm_mode_config_init(drm); 231 232 drm->mode_config.min_width = 64; 233 drm->mode_config.min_height = 64; 234 235 /* 236 * set max width and height as default value(4096x4096). 237 * this value would be used to check framebuffer size limitation 238 * at drm_mode_addfb(). 239 */ 240 drm->mode_config.max_width = 4096; 241 drm->mode_config.max_height = 4096; 242 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 243 244 ret = component_bind_all(drm->dev, drm); 245 if (ret) 246 goto err_config_cleanup; 247 248 /* 249 * We currently support two fixed data streams, each optional, 250 * and each statically assigned to a crtc: 251 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 252 */ 253 ret = mtk_drm_crtc_create(drm, private->data->main_path, 254 private->data->main_len); 255 if (ret < 0) 256 goto err_component_unbind; 257 /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */ 258 ret = mtk_drm_crtc_create(drm, private->data->ext_path, 259 private->data->ext_len); 260 if (ret < 0) 261 goto err_component_unbind; 262 263 ret = mtk_drm_crtc_create(drm, private->data->third_path, 264 private->data->third_len); 265 if (ret < 0) 266 goto err_component_unbind; 267 268 /* Use OVL device for all DMA memory allocations */ 269 np = private->comp_node[private->data->main_path[0]] ?: 270 private->comp_node[private->data->ext_path[0]]; 271 pdev = of_find_device_by_node(np); 272 if (!pdev) { 273 ret = -ENODEV; 274 dev_err(drm->dev, "Need at least one OVL device\n"); 275 goto err_component_unbind; 276 } 277 278 private->dma_dev = &pdev->dev; 279 280 /* 281 * We don't use the drm_irq_install() helpers provided by the DRM 282 * core, so we need to set this manually in order to allow the 283 * DRM_IOCTL_WAIT_VBLANK to operate correctly. 284 */ 285 drm->irq_enabled = true; 286 ret = drm_vblank_init(drm, MAX_CRTC); 287 if (ret < 0) 288 goto err_component_unbind; 289 290 drm_kms_helper_poll_init(drm); 291 drm_mode_config_reset(drm); 292 293 return 0; 294 295 err_component_unbind: 296 component_unbind_all(drm->dev, drm); 297 err_config_cleanup: 298 drm_mode_config_cleanup(drm); 299 300 return ret; 301 } 302 303 static void mtk_drm_kms_deinit(struct drm_device *drm) 304 { 305 drm_kms_helper_poll_fini(drm); 306 307 component_unbind_all(drm->dev, drm); 308 drm_mode_config_cleanup(drm); 309 } 310 311 static const struct file_operations mtk_drm_fops = { 312 .owner = THIS_MODULE, 313 .open = drm_open, 314 .release = drm_release, 315 .unlocked_ioctl = drm_ioctl, 316 .mmap = mtk_drm_gem_mmap, 317 .poll = drm_poll, 318 .read = drm_read, 319 .compat_ioctl = drm_compat_ioctl, 320 }; 321 322 static struct drm_driver mtk_drm_driver = { 323 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | 324 DRIVER_ATOMIC, 325 326 .gem_free_object_unlocked = mtk_drm_gem_free_object, 327 .gem_vm_ops = &drm_gem_cma_vm_ops, 328 .dumb_create = mtk_drm_gem_dumb_create, 329 330 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 331 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 332 .gem_prime_export = drm_gem_prime_export, 333 .gem_prime_import = drm_gem_prime_import, 334 .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table, 335 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 336 .gem_prime_mmap = mtk_drm_gem_mmap_buf, 337 .gem_prime_vmap = mtk_drm_gem_prime_vmap, 338 .gem_prime_vunmap = mtk_drm_gem_prime_vunmap, 339 .fops = &mtk_drm_fops, 340 341 .name = DRIVER_NAME, 342 .desc = DRIVER_DESC, 343 .date = DRIVER_DATE, 344 .major = DRIVER_MAJOR, 345 .minor = DRIVER_MINOR, 346 }; 347 348 static int compare_of(struct device *dev, void *data) 349 { 350 return dev->of_node == data; 351 } 352 353 static int mtk_drm_bind(struct device *dev) 354 { 355 struct mtk_drm_private *private = dev_get_drvdata(dev); 356 struct drm_device *drm; 357 int ret; 358 359 drm = drm_dev_alloc(&mtk_drm_driver, dev); 360 if (IS_ERR(drm)) 361 return PTR_ERR(drm); 362 363 drm->dev_private = private; 364 private->drm = drm; 365 366 ret = mtk_drm_kms_init(drm); 367 if (ret < 0) 368 goto err_free; 369 370 ret = drm_dev_register(drm, 0); 371 if (ret < 0) 372 goto err_deinit; 373 374 ret = drm_fbdev_generic_setup(drm, 32); 375 if (ret) 376 DRM_ERROR("Failed to initialize fbdev: %d\n", ret); 377 378 return 0; 379 380 err_deinit: 381 mtk_drm_kms_deinit(drm); 382 err_free: 383 drm_dev_put(drm); 384 return ret; 385 } 386 387 static void mtk_drm_unbind(struct device *dev) 388 { 389 struct mtk_drm_private *private = dev_get_drvdata(dev); 390 391 drm_dev_unregister(private->drm); 392 drm_dev_put(private->drm); 393 private->drm = NULL; 394 } 395 396 static const struct component_master_ops mtk_drm_ops = { 397 .bind = mtk_drm_bind, 398 .unbind = mtk_drm_unbind, 399 }; 400 401 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 402 { .compatible = "mediatek,mt2701-disp-ovl", 403 .data = (void *)MTK_DISP_OVL }, 404 { .compatible = "mediatek,mt8173-disp-ovl", 405 .data = (void *)MTK_DISP_OVL }, 406 { .compatible = "mediatek,mt2701-disp-rdma", 407 .data = (void *)MTK_DISP_RDMA }, 408 { .compatible = "mediatek,mt8173-disp-rdma", 409 .data = (void *)MTK_DISP_RDMA }, 410 { .compatible = "mediatek,mt8173-disp-wdma", 411 .data = (void *)MTK_DISP_WDMA }, 412 { .compatible = "mediatek,mt2701-disp-color", 413 .data = (void *)MTK_DISP_COLOR }, 414 { .compatible = "mediatek,mt8173-disp-color", 415 .data = (void *)MTK_DISP_COLOR }, 416 { .compatible = "mediatek,mt8173-disp-aal", 417 .data = (void *)MTK_DISP_AAL}, 418 { .compatible = "mediatek,mt8173-disp-gamma", 419 .data = (void *)MTK_DISP_GAMMA, }, 420 { .compatible = "mediatek,mt8173-disp-ufoe", 421 .data = (void *)MTK_DISP_UFOE }, 422 { .compatible = "mediatek,mt2701-dsi", 423 .data = (void *)MTK_DSI }, 424 { .compatible = "mediatek,mt8173-dsi", 425 .data = (void *)MTK_DSI }, 426 { .compatible = "mediatek,mt2701-dpi", 427 .data = (void *)MTK_DPI }, 428 { .compatible = "mediatek,mt8173-dpi", 429 .data = (void *)MTK_DPI }, 430 { .compatible = "mediatek,mt2701-disp-mutex", 431 .data = (void *)MTK_DISP_MUTEX }, 432 { .compatible = "mediatek,mt2712-disp-mutex", 433 .data = (void *)MTK_DISP_MUTEX }, 434 { .compatible = "mediatek,mt8173-disp-mutex", 435 .data = (void *)MTK_DISP_MUTEX }, 436 { .compatible = "mediatek,mt2701-disp-pwm", 437 .data = (void *)MTK_DISP_BLS }, 438 { .compatible = "mediatek,mt8173-disp-pwm", 439 .data = (void *)MTK_DISP_PWM }, 440 { .compatible = "mediatek,mt8173-disp-od", 441 .data = (void *)MTK_DISP_OD }, 442 { } 443 }; 444 445 static int mtk_drm_probe(struct platform_device *pdev) 446 { 447 struct device *dev = &pdev->dev; 448 struct mtk_drm_private *private; 449 struct resource *mem; 450 struct device_node *node; 451 struct component_match *match = NULL; 452 int ret; 453 int i; 454 455 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 456 if (!private) 457 return -ENOMEM; 458 459 mutex_init(&private->commit.lock); 460 INIT_WORK(&private->commit.work, mtk_atomic_work); 461 private->data = of_device_get_match_data(dev); 462 463 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 464 private->config_regs = devm_ioremap_resource(dev, mem); 465 if (IS_ERR(private->config_regs)) { 466 ret = PTR_ERR(private->config_regs); 467 dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", 468 ret); 469 return ret; 470 } 471 472 /* Iterate over sibling DISP function blocks */ 473 for_each_child_of_node(dev->of_node->parent, node) { 474 const struct of_device_id *of_id; 475 enum mtk_ddp_comp_type comp_type; 476 int comp_id; 477 478 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 479 if (!of_id) 480 continue; 481 482 if (!of_device_is_available(node)) { 483 dev_dbg(dev, "Skipping disabled component %pOF\n", 484 node); 485 continue; 486 } 487 488 comp_type = (enum mtk_ddp_comp_type)of_id->data; 489 490 if (comp_type == MTK_DISP_MUTEX) { 491 private->mutex_node = of_node_get(node); 492 continue; 493 } 494 495 comp_id = mtk_ddp_comp_get_id(node, comp_type); 496 if (comp_id < 0) { 497 dev_warn(dev, "Skipping unknown component %pOF\n", 498 node); 499 continue; 500 } 501 502 private->comp_node[comp_id] = of_node_get(node); 503 504 /* 505 * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have 506 * separate component platform drivers and initialize their own 507 * DDP component structure. The others are initialized here. 508 */ 509 if (comp_type == MTK_DISP_COLOR || 510 comp_type == MTK_DISP_OVL || 511 comp_type == MTK_DISP_RDMA || 512 comp_type == MTK_DSI || 513 comp_type == MTK_DPI) { 514 dev_info(dev, "Adding component match for %pOF\n", 515 node); 516 drm_of_component_match_add(dev, &match, compare_of, 517 node); 518 } else { 519 struct mtk_ddp_comp *comp; 520 521 comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); 522 if (!comp) { 523 ret = -ENOMEM; 524 goto err_node; 525 } 526 527 ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL); 528 if (ret) 529 goto err_node; 530 531 private->ddp_comp[comp_id] = comp; 532 } 533 } 534 535 if (!private->mutex_node) { 536 dev_err(dev, "Failed to find disp-mutex node\n"); 537 ret = -ENODEV; 538 goto err_node; 539 } 540 541 pm_runtime_enable(dev); 542 543 platform_set_drvdata(pdev, private); 544 545 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 546 if (ret) 547 goto err_pm; 548 549 return 0; 550 551 err_pm: 552 pm_runtime_disable(dev); 553 err_node: 554 of_node_put(private->mutex_node); 555 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 556 of_node_put(private->comp_node[i]); 557 return ret; 558 } 559 560 static int mtk_drm_remove(struct platform_device *pdev) 561 { 562 struct mtk_drm_private *private = platform_get_drvdata(pdev); 563 struct drm_device *drm = private->drm; 564 int i; 565 566 drm_dev_unregister(drm); 567 mtk_drm_kms_deinit(drm); 568 drm_dev_put(drm); 569 570 component_master_del(&pdev->dev, &mtk_drm_ops); 571 pm_runtime_disable(&pdev->dev); 572 of_node_put(private->mutex_node); 573 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 574 of_node_put(private->comp_node[i]); 575 576 return 0; 577 } 578 579 #ifdef CONFIG_PM_SLEEP 580 static int mtk_drm_sys_suspend(struct device *dev) 581 { 582 struct mtk_drm_private *private = dev_get_drvdata(dev); 583 struct drm_device *drm = private->drm; 584 int ret; 585 586 ret = drm_mode_config_helper_suspend(drm); 587 DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n"); 588 589 return ret; 590 } 591 592 static int mtk_drm_sys_resume(struct device *dev) 593 { 594 struct mtk_drm_private *private = dev_get_drvdata(dev); 595 struct drm_device *drm = private->drm; 596 int ret; 597 598 ret = drm_mode_config_helper_resume(drm); 599 DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n"); 600 601 return ret; 602 } 603 #endif 604 605 static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, 606 mtk_drm_sys_resume); 607 608 static const struct of_device_id mtk_drm_of_ids[] = { 609 { .compatible = "mediatek,mt2701-mmsys", 610 .data = &mt2701_mmsys_driver_data}, 611 { .compatible = "mediatek,mt2712-mmsys", 612 .data = &mt2712_mmsys_driver_data}, 613 { .compatible = "mediatek,mt8173-mmsys", 614 .data = &mt8173_mmsys_driver_data}, 615 { } 616 }; 617 618 static struct platform_driver mtk_drm_platform_driver = { 619 .probe = mtk_drm_probe, 620 .remove = mtk_drm_remove, 621 .driver = { 622 .name = "mediatek-drm", 623 .of_match_table = mtk_drm_of_ids, 624 .pm = &mtk_drm_pm_ops, 625 }, 626 }; 627 628 static struct platform_driver * const mtk_drm_drivers[] = { 629 &mtk_ddp_driver, 630 &mtk_disp_color_driver, 631 &mtk_disp_ovl_driver, 632 &mtk_disp_rdma_driver, 633 &mtk_dpi_driver, 634 &mtk_drm_platform_driver, 635 &mtk_dsi_driver, 636 &mtk_mipi_tx_driver, 637 }; 638 639 static int __init mtk_drm_init(void) 640 { 641 return platform_register_drivers(mtk_drm_drivers, 642 ARRAY_SIZE(mtk_drm_drivers)); 643 } 644 645 static void __exit mtk_drm_exit(void) 646 { 647 platform_unregister_drivers(mtk_drm_drivers, 648 ARRAY_SIZE(mtk_drm_drivers)); 649 } 650 651 module_init(mtk_drm_init); 652 module_exit(mtk_drm_exit); 653 654 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 655 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 656 MODULE_LICENSE("GPL v2"); 657