1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of_address.h> 11 #include <linux/of_platform.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_drv.h> 17 #include <drm/drm_fb_helper.h> 18 #include <drm/drm_gem.h> 19 #include <drm/drm_gem_cma_helper.h> 20 #include <drm/drm_of.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_vblank.h> 23 24 #include "mtk_drm_crtc.h" 25 #include "mtk_drm_ddp.h" 26 #include "mtk_drm_ddp.h" 27 #include "mtk_drm_ddp_comp.h" 28 #include "mtk_drm_drv.h" 29 #include "mtk_drm_fb.h" 30 #include "mtk_drm_gem.h" 31 32 #define DRIVER_NAME "mediatek" 33 #define DRIVER_DESC "Mediatek SoC DRM" 34 #define DRIVER_DATE "20150513" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 38 static void mtk_atomic_schedule(struct mtk_drm_private *private, 39 struct drm_atomic_state *state) 40 { 41 private->commit.state = state; 42 schedule_work(&private->commit.work); 43 } 44 45 static void mtk_atomic_complete(struct mtk_drm_private *private, 46 struct drm_atomic_state *state) 47 { 48 struct drm_device *drm = private->drm; 49 50 drm_atomic_helper_wait_for_fences(drm, state, false); 51 52 /* 53 * Mediatek drm supports runtime PM, so plane registers cannot be 54 * written when their crtc is disabled. 55 * 56 * The comment for drm_atomic_helper_commit states: 57 * For drivers supporting runtime PM the recommended sequence is 58 * 59 * drm_atomic_helper_commit_modeset_disables(dev, state); 60 * drm_atomic_helper_commit_modeset_enables(dev, state); 61 * drm_atomic_helper_commit_planes(dev, state, 62 * DRM_PLANE_COMMIT_ACTIVE_ONLY); 63 * 64 * See the kerneldoc entries for these three functions for more details. 65 */ 66 drm_atomic_helper_commit_modeset_disables(drm, state); 67 drm_atomic_helper_commit_modeset_enables(drm, state); 68 drm_atomic_helper_commit_planes(drm, state, 69 DRM_PLANE_COMMIT_ACTIVE_ONLY); 70 71 drm_atomic_helper_wait_for_vblanks(drm, state); 72 73 drm_atomic_helper_cleanup_planes(drm, state); 74 drm_atomic_state_put(state); 75 } 76 77 static void mtk_atomic_work(struct work_struct *work) 78 { 79 struct mtk_drm_private *private = container_of(work, 80 struct mtk_drm_private, commit.work); 81 82 mtk_atomic_complete(private, private->commit.state); 83 } 84 85 static int mtk_atomic_commit(struct drm_device *drm, 86 struct drm_atomic_state *state, 87 bool async) 88 { 89 struct mtk_drm_private *private = drm->dev_private; 90 int ret; 91 92 ret = drm_atomic_helper_prepare_planes(drm, state); 93 if (ret) 94 return ret; 95 96 mutex_lock(&private->commit.lock); 97 flush_work(&private->commit.work); 98 99 ret = drm_atomic_helper_swap_state(state, true); 100 if (ret) { 101 mutex_unlock(&private->commit.lock); 102 drm_atomic_helper_cleanup_planes(drm, state); 103 return ret; 104 } 105 106 drm_atomic_state_get(state); 107 if (async) 108 mtk_atomic_schedule(private, state); 109 else 110 mtk_atomic_complete(private, state); 111 112 mutex_unlock(&private->commit.lock); 113 114 return 0; 115 } 116 117 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 118 .fb_create = mtk_drm_mode_fb_create, 119 .atomic_check = drm_atomic_helper_check, 120 .atomic_commit = mtk_atomic_commit, 121 }; 122 123 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { 124 DDP_COMPONENT_OVL0, 125 DDP_COMPONENT_RDMA0, 126 DDP_COMPONENT_COLOR0, 127 DDP_COMPONENT_BLS, 128 DDP_COMPONENT_DSI0, 129 }; 130 131 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { 132 DDP_COMPONENT_RDMA1, 133 DDP_COMPONENT_DPI0, 134 }; 135 136 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { 137 DDP_COMPONENT_OVL0, 138 DDP_COMPONENT_COLOR0, 139 DDP_COMPONENT_AAL0, 140 DDP_COMPONENT_OD0, 141 DDP_COMPONENT_RDMA0, 142 DDP_COMPONENT_DPI0, 143 DDP_COMPONENT_PWM0, 144 }; 145 146 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 147 DDP_COMPONENT_OVL1, 148 DDP_COMPONENT_COLOR1, 149 DDP_COMPONENT_AAL1, 150 DDP_COMPONENT_OD1, 151 DDP_COMPONENT_RDMA1, 152 DDP_COMPONENT_DPI1, 153 DDP_COMPONENT_PWM1, 154 }; 155 156 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 157 DDP_COMPONENT_RDMA2, 158 DDP_COMPONENT_DSI3, 159 DDP_COMPONENT_PWM2, 160 }; 161 162 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 163 DDP_COMPONENT_OVL0, 164 DDP_COMPONENT_COLOR0, 165 DDP_COMPONENT_AAL0, 166 DDP_COMPONENT_OD0, 167 DDP_COMPONENT_RDMA0, 168 DDP_COMPONENT_UFOE, 169 DDP_COMPONENT_DSI0, 170 DDP_COMPONENT_PWM0, 171 }; 172 173 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 174 DDP_COMPONENT_OVL1, 175 DDP_COMPONENT_COLOR1, 176 DDP_COMPONENT_GAMMA, 177 DDP_COMPONENT_RDMA1, 178 DDP_COMPONENT_DPI0, 179 }; 180 181 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 182 .main_path = mt2701_mtk_ddp_main, 183 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 184 .ext_path = mt2701_mtk_ddp_ext, 185 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 186 .shadow_register = true, 187 }; 188 189 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 190 .main_path = mt2712_mtk_ddp_main, 191 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 192 .ext_path = mt2712_mtk_ddp_ext, 193 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 194 .third_path = mt2712_mtk_ddp_third, 195 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 196 }; 197 198 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 199 .main_path = mt8173_mtk_ddp_main, 200 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 201 .ext_path = mt8173_mtk_ddp_ext, 202 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 203 }; 204 205 static int mtk_drm_kms_init(struct drm_device *drm) 206 { 207 struct mtk_drm_private *private = drm->dev_private; 208 struct platform_device *pdev; 209 struct device_node *np; 210 int ret; 211 212 if (!iommu_present(&platform_bus_type)) 213 return -EPROBE_DEFER; 214 215 pdev = of_find_device_by_node(private->mutex_node); 216 if (!pdev) { 217 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", 218 private->mutex_node); 219 of_node_put(private->mutex_node); 220 return -EPROBE_DEFER; 221 } 222 private->mutex_dev = &pdev->dev; 223 224 drm_mode_config_init(drm); 225 226 drm->mode_config.min_width = 64; 227 drm->mode_config.min_height = 64; 228 229 /* 230 * set max width and height as default value(4096x4096). 231 * this value would be used to check framebuffer size limitation 232 * at drm_mode_addfb(). 233 */ 234 drm->mode_config.max_width = 4096; 235 drm->mode_config.max_height = 4096; 236 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 237 238 ret = component_bind_all(drm->dev, drm); 239 if (ret) 240 goto err_config_cleanup; 241 242 /* 243 * We currently support two fixed data streams, each optional, 244 * and each statically assigned to a crtc: 245 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 246 */ 247 ret = mtk_drm_crtc_create(drm, private->data->main_path, 248 private->data->main_len); 249 if (ret < 0) 250 goto err_component_unbind; 251 /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */ 252 ret = mtk_drm_crtc_create(drm, private->data->ext_path, 253 private->data->ext_len); 254 if (ret < 0) 255 goto err_component_unbind; 256 257 ret = mtk_drm_crtc_create(drm, private->data->third_path, 258 private->data->third_len); 259 if (ret < 0) 260 goto err_component_unbind; 261 262 /* Use OVL device for all DMA memory allocations */ 263 np = private->comp_node[private->data->main_path[0]] ?: 264 private->comp_node[private->data->ext_path[0]]; 265 pdev = of_find_device_by_node(np); 266 if (!pdev) { 267 ret = -ENODEV; 268 dev_err(drm->dev, "Need at least one OVL device\n"); 269 goto err_component_unbind; 270 } 271 272 private->dma_dev = &pdev->dev; 273 274 /* 275 * We don't use the drm_irq_install() helpers provided by the DRM 276 * core, so we need to set this manually in order to allow the 277 * DRM_IOCTL_WAIT_VBLANK to operate correctly. 278 */ 279 drm->irq_enabled = true; 280 ret = drm_vblank_init(drm, MAX_CRTC); 281 if (ret < 0) 282 goto err_component_unbind; 283 284 drm_kms_helper_poll_init(drm); 285 drm_mode_config_reset(drm); 286 287 return 0; 288 289 err_component_unbind: 290 component_unbind_all(drm->dev, drm); 291 err_config_cleanup: 292 drm_mode_config_cleanup(drm); 293 294 return ret; 295 } 296 297 static void mtk_drm_kms_deinit(struct drm_device *drm) 298 { 299 drm_kms_helper_poll_fini(drm); 300 drm_atomic_helper_shutdown(drm); 301 302 component_unbind_all(drm->dev, drm); 303 drm_mode_config_cleanup(drm); 304 } 305 306 static const struct file_operations mtk_drm_fops = { 307 .owner = THIS_MODULE, 308 .open = drm_open, 309 .release = drm_release, 310 .unlocked_ioctl = drm_ioctl, 311 .mmap = mtk_drm_gem_mmap, 312 .poll = drm_poll, 313 .read = drm_read, 314 .compat_ioctl = drm_compat_ioctl, 315 }; 316 317 static struct drm_driver mtk_drm_driver = { 318 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 319 320 .gem_free_object_unlocked = mtk_drm_gem_free_object, 321 .gem_vm_ops = &drm_gem_cma_vm_ops, 322 .dumb_create = mtk_drm_gem_dumb_create, 323 324 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 325 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 326 .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table, 327 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 328 .gem_prime_mmap = mtk_drm_gem_mmap_buf, 329 .gem_prime_vmap = mtk_drm_gem_prime_vmap, 330 .gem_prime_vunmap = mtk_drm_gem_prime_vunmap, 331 .fops = &mtk_drm_fops, 332 333 .name = DRIVER_NAME, 334 .desc = DRIVER_DESC, 335 .date = DRIVER_DATE, 336 .major = DRIVER_MAJOR, 337 .minor = DRIVER_MINOR, 338 }; 339 340 static int compare_of(struct device *dev, void *data) 341 { 342 return dev->of_node == data; 343 } 344 345 static int mtk_drm_bind(struct device *dev) 346 { 347 struct mtk_drm_private *private = dev_get_drvdata(dev); 348 struct drm_device *drm; 349 int ret; 350 351 drm = drm_dev_alloc(&mtk_drm_driver, dev); 352 if (IS_ERR(drm)) 353 return PTR_ERR(drm); 354 355 drm->dev_private = private; 356 private->drm = drm; 357 358 ret = mtk_drm_kms_init(drm); 359 if (ret < 0) 360 goto err_free; 361 362 ret = drm_dev_register(drm, 0); 363 if (ret < 0) 364 goto err_deinit; 365 366 ret = drm_fbdev_generic_setup(drm, 32); 367 if (ret) 368 DRM_ERROR("Failed to initialize fbdev: %d\n", ret); 369 370 return 0; 371 372 err_deinit: 373 mtk_drm_kms_deinit(drm); 374 err_free: 375 drm_dev_put(drm); 376 return ret; 377 } 378 379 static void mtk_drm_unbind(struct device *dev) 380 { 381 struct mtk_drm_private *private = dev_get_drvdata(dev); 382 383 drm_dev_unregister(private->drm); 384 mtk_drm_kms_deinit(private->drm); 385 drm_dev_put(private->drm); 386 private->num_pipes = 0; 387 private->drm = NULL; 388 } 389 390 static const struct component_master_ops mtk_drm_ops = { 391 .bind = mtk_drm_bind, 392 .unbind = mtk_drm_unbind, 393 }; 394 395 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 396 { .compatible = "mediatek,mt2701-disp-ovl", 397 .data = (void *)MTK_DISP_OVL }, 398 { .compatible = "mediatek,mt8173-disp-ovl", 399 .data = (void *)MTK_DISP_OVL }, 400 { .compatible = "mediatek,mt2701-disp-rdma", 401 .data = (void *)MTK_DISP_RDMA }, 402 { .compatible = "mediatek,mt8173-disp-rdma", 403 .data = (void *)MTK_DISP_RDMA }, 404 { .compatible = "mediatek,mt8173-disp-wdma", 405 .data = (void *)MTK_DISP_WDMA }, 406 { .compatible = "mediatek,mt2701-disp-color", 407 .data = (void *)MTK_DISP_COLOR }, 408 { .compatible = "mediatek,mt8173-disp-color", 409 .data = (void *)MTK_DISP_COLOR }, 410 { .compatible = "mediatek,mt8173-disp-aal", 411 .data = (void *)MTK_DISP_AAL}, 412 { .compatible = "mediatek,mt8173-disp-gamma", 413 .data = (void *)MTK_DISP_GAMMA, }, 414 { .compatible = "mediatek,mt8173-disp-ufoe", 415 .data = (void *)MTK_DISP_UFOE }, 416 { .compatible = "mediatek,mt2701-dsi", 417 .data = (void *)MTK_DSI }, 418 { .compatible = "mediatek,mt8173-dsi", 419 .data = (void *)MTK_DSI }, 420 { .compatible = "mediatek,mt2701-dpi", 421 .data = (void *)MTK_DPI }, 422 { .compatible = "mediatek,mt8173-dpi", 423 .data = (void *)MTK_DPI }, 424 { .compatible = "mediatek,mt2701-disp-mutex", 425 .data = (void *)MTK_DISP_MUTEX }, 426 { .compatible = "mediatek,mt2712-disp-mutex", 427 .data = (void *)MTK_DISP_MUTEX }, 428 { .compatible = "mediatek,mt8173-disp-mutex", 429 .data = (void *)MTK_DISP_MUTEX }, 430 { .compatible = "mediatek,mt2701-disp-pwm", 431 .data = (void *)MTK_DISP_BLS }, 432 { .compatible = "mediatek,mt8173-disp-pwm", 433 .data = (void *)MTK_DISP_PWM }, 434 { .compatible = "mediatek,mt8173-disp-od", 435 .data = (void *)MTK_DISP_OD }, 436 { } 437 }; 438 439 static int mtk_drm_probe(struct platform_device *pdev) 440 { 441 struct device *dev = &pdev->dev; 442 struct mtk_drm_private *private; 443 struct resource *mem; 444 struct device_node *node; 445 struct component_match *match = NULL; 446 int ret; 447 int i; 448 449 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 450 if (!private) 451 return -ENOMEM; 452 453 mutex_init(&private->commit.lock); 454 INIT_WORK(&private->commit.work, mtk_atomic_work); 455 private->data = of_device_get_match_data(dev); 456 457 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 458 private->config_regs = devm_ioremap_resource(dev, mem); 459 if (IS_ERR(private->config_regs)) { 460 ret = PTR_ERR(private->config_regs); 461 dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", 462 ret); 463 return ret; 464 } 465 466 /* Iterate over sibling DISP function blocks */ 467 for_each_child_of_node(dev->of_node->parent, node) { 468 const struct of_device_id *of_id; 469 enum mtk_ddp_comp_type comp_type; 470 int comp_id; 471 472 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 473 if (!of_id) 474 continue; 475 476 if (!of_device_is_available(node)) { 477 dev_dbg(dev, "Skipping disabled component %pOF\n", 478 node); 479 continue; 480 } 481 482 comp_type = (enum mtk_ddp_comp_type)of_id->data; 483 484 if (comp_type == MTK_DISP_MUTEX) { 485 private->mutex_node = of_node_get(node); 486 continue; 487 } 488 489 comp_id = mtk_ddp_comp_get_id(node, comp_type); 490 if (comp_id < 0) { 491 dev_warn(dev, "Skipping unknown component %pOF\n", 492 node); 493 continue; 494 } 495 496 private->comp_node[comp_id] = of_node_get(node); 497 498 /* 499 * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have 500 * separate component platform drivers and initialize their own 501 * DDP component structure. The others are initialized here. 502 */ 503 if (comp_type == MTK_DISP_COLOR || 504 comp_type == MTK_DISP_OVL || 505 comp_type == MTK_DISP_RDMA || 506 comp_type == MTK_DSI || 507 comp_type == MTK_DPI) { 508 dev_info(dev, "Adding component match for %pOF\n", 509 node); 510 drm_of_component_match_add(dev, &match, compare_of, 511 node); 512 } else { 513 struct mtk_ddp_comp *comp; 514 515 comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); 516 if (!comp) { 517 ret = -ENOMEM; 518 goto err_node; 519 } 520 521 ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL); 522 if (ret) 523 goto err_node; 524 525 private->ddp_comp[comp_id] = comp; 526 } 527 } 528 529 if (!private->mutex_node) { 530 dev_err(dev, "Failed to find disp-mutex node\n"); 531 ret = -ENODEV; 532 goto err_node; 533 } 534 535 pm_runtime_enable(dev); 536 537 platform_set_drvdata(pdev, private); 538 539 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 540 if (ret) 541 goto err_pm; 542 543 return 0; 544 545 err_pm: 546 pm_runtime_disable(dev); 547 err_node: 548 of_node_put(private->mutex_node); 549 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 550 of_node_put(private->comp_node[i]); 551 return ret; 552 } 553 554 static int mtk_drm_remove(struct platform_device *pdev) 555 { 556 struct mtk_drm_private *private = platform_get_drvdata(pdev); 557 int i; 558 559 component_master_del(&pdev->dev, &mtk_drm_ops); 560 pm_runtime_disable(&pdev->dev); 561 of_node_put(private->mutex_node); 562 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 563 of_node_put(private->comp_node[i]); 564 565 return 0; 566 } 567 568 #ifdef CONFIG_PM_SLEEP 569 static int mtk_drm_sys_suspend(struct device *dev) 570 { 571 struct mtk_drm_private *private = dev_get_drvdata(dev); 572 struct drm_device *drm = private->drm; 573 int ret; 574 575 ret = drm_mode_config_helper_suspend(drm); 576 DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n"); 577 578 return ret; 579 } 580 581 static int mtk_drm_sys_resume(struct device *dev) 582 { 583 struct mtk_drm_private *private = dev_get_drvdata(dev); 584 struct drm_device *drm = private->drm; 585 int ret; 586 587 ret = drm_mode_config_helper_resume(drm); 588 DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n"); 589 590 return ret; 591 } 592 #endif 593 594 static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, 595 mtk_drm_sys_resume); 596 597 static const struct of_device_id mtk_drm_of_ids[] = { 598 { .compatible = "mediatek,mt2701-mmsys", 599 .data = &mt2701_mmsys_driver_data}, 600 { .compatible = "mediatek,mt2712-mmsys", 601 .data = &mt2712_mmsys_driver_data}, 602 { .compatible = "mediatek,mt8173-mmsys", 603 .data = &mt8173_mmsys_driver_data}, 604 { } 605 }; 606 607 static struct platform_driver mtk_drm_platform_driver = { 608 .probe = mtk_drm_probe, 609 .remove = mtk_drm_remove, 610 .driver = { 611 .name = "mediatek-drm", 612 .of_match_table = mtk_drm_of_ids, 613 .pm = &mtk_drm_pm_ops, 614 }, 615 }; 616 617 static struct platform_driver * const mtk_drm_drivers[] = { 618 &mtk_ddp_driver, 619 &mtk_disp_color_driver, 620 &mtk_disp_ovl_driver, 621 &mtk_disp_rdma_driver, 622 &mtk_dpi_driver, 623 &mtk_drm_platform_driver, 624 &mtk_dsi_driver, 625 &mtk_mipi_tx_driver, 626 }; 627 628 static int __init mtk_drm_init(void) 629 { 630 return platform_register_drivers(mtk_drm_drivers, 631 ARRAY_SIZE(mtk_drm_drivers)); 632 } 633 634 static void __exit mtk_drm_exit(void) 635 { 636 platform_unregister_drivers(mtk_drm_drivers, 637 ARRAY_SIZE(mtk_drm_drivers)); 638 } 639 640 module_init(mtk_drm_init); 641 module_exit(mtk_drm_exit); 642 643 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 644 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 645 MODULE_LICENSE("GPL v2"); 646