1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  * Author: YT SHEN <yt.shen@mediatek.com>
5  */
6 
7 #include <linux/component.h>
8 #include <linux/iommu.h>
9 #include <linux/module.h>
10 #include <linux/of_address.h>
11 #include <linux/of_platform.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/dma-mapping.h>
14 
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_drv.h>
18 #include <drm/drm_fbdev_generic.h>
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_gem.h>
21 #include <drm/drm_gem_framebuffer_helper.h>
22 #include <drm/drm_ioctl.h>
23 #include <drm/drm_of.h>
24 #include <drm/drm_probe_helper.h>
25 #include <drm/drm_vblank.h>
26 
27 #include "mtk_drm_crtc.h"
28 #include "mtk_drm_ddp_comp.h"
29 #include "mtk_drm_drv.h"
30 #include "mtk_drm_gem.h"
31 
32 #define DRIVER_NAME "mediatek"
33 #define DRIVER_DESC "Mediatek SoC DRM"
34 #define DRIVER_DATE "20150513"
35 #define DRIVER_MAJOR 1
36 #define DRIVER_MINOR 0
37 
38 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
39 	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
40 };
41 
42 static struct drm_framebuffer *
43 mtk_drm_mode_fb_create(struct drm_device *dev,
44 		       struct drm_file *file,
45 		       const struct drm_mode_fb_cmd2 *cmd)
46 {
47 	const struct drm_format_info *info = drm_get_format_info(dev, cmd);
48 
49 	if (info->num_planes != 1)
50 		return ERR_PTR(-EINVAL);
51 
52 	return drm_gem_fb_create(dev, file, cmd);
53 }
54 
55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
56 	.fb_create = mtk_drm_mode_fb_create,
57 	.atomic_check = drm_atomic_helper_check,
58 	.atomic_commit = drm_atomic_helper_commit,
59 };
60 
61 static const unsigned int mt2701_mtk_ddp_main[] = {
62 	DDP_COMPONENT_OVL0,
63 	DDP_COMPONENT_RDMA0,
64 	DDP_COMPONENT_COLOR0,
65 	DDP_COMPONENT_BLS,
66 	DDP_COMPONENT_DSI0,
67 };
68 
69 static const unsigned int mt2701_mtk_ddp_ext[] = {
70 	DDP_COMPONENT_RDMA1,
71 	DDP_COMPONENT_DPI0,
72 };
73 
74 static const unsigned int mt7623_mtk_ddp_main[] = {
75 	DDP_COMPONENT_OVL0,
76 	DDP_COMPONENT_RDMA0,
77 	DDP_COMPONENT_COLOR0,
78 	DDP_COMPONENT_BLS,
79 	DDP_COMPONENT_DPI0,
80 };
81 
82 static const unsigned int mt7623_mtk_ddp_ext[] = {
83 	DDP_COMPONENT_RDMA1,
84 	DDP_COMPONENT_DSI0,
85 };
86 
87 static const unsigned int mt2712_mtk_ddp_main[] = {
88 	DDP_COMPONENT_OVL0,
89 	DDP_COMPONENT_COLOR0,
90 	DDP_COMPONENT_AAL0,
91 	DDP_COMPONENT_OD0,
92 	DDP_COMPONENT_RDMA0,
93 	DDP_COMPONENT_DPI0,
94 	DDP_COMPONENT_PWM0,
95 };
96 
97 static const unsigned int mt2712_mtk_ddp_ext[] = {
98 	DDP_COMPONENT_OVL1,
99 	DDP_COMPONENT_COLOR1,
100 	DDP_COMPONENT_AAL1,
101 	DDP_COMPONENT_OD1,
102 	DDP_COMPONENT_RDMA1,
103 	DDP_COMPONENT_DPI1,
104 	DDP_COMPONENT_PWM1,
105 };
106 
107 static const unsigned int mt2712_mtk_ddp_third[] = {
108 	DDP_COMPONENT_RDMA2,
109 	DDP_COMPONENT_DSI3,
110 	DDP_COMPONENT_PWM2,
111 };
112 
113 static unsigned int mt8167_mtk_ddp_main[] = {
114 	DDP_COMPONENT_OVL0,
115 	DDP_COMPONENT_COLOR0,
116 	DDP_COMPONENT_CCORR,
117 	DDP_COMPONENT_AAL0,
118 	DDP_COMPONENT_GAMMA,
119 	DDP_COMPONENT_DITHER0,
120 	DDP_COMPONENT_RDMA0,
121 	DDP_COMPONENT_DSI0,
122 };
123 
124 static const unsigned int mt8173_mtk_ddp_main[] = {
125 	DDP_COMPONENT_OVL0,
126 	DDP_COMPONENT_COLOR0,
127 	DDP_COMPONENT_AAL0,
128 	DDP_COMPONENT_OD0,
129 	DDP_COMPONENT_RDMA0,
130 	DDP_COMPONENT_UFOE,
131 	DDP_COMPONENT_DSI0,
132 	DDP_COMPONENT_PWM0,
133 };
134 
135 static const unsigned int mt8173_mtk_ddp_ext[] = {
136 	DDP_COMPONENT_OVL1,
137 	DDP_COMPONENT_COLOR1,
138 	DDP_COMPONENT_GAMMA,
139 	DDP_COMPONENT_RDMA1,
140 	DDP_COMPONENT_DPI0,
141 };
142 
143 static const unsigned int mt8183_mtk_ddp_main[] = {
144 	DDP_COMPONENT_OVL0,
145 	DDP_COMPONENT_OVL_2L0,
146 	DDP_COMPONENT_RDMA0,
147 	DDP_COMPONENT_COLOR0,
148 	DDP_COMPONENT_CCORR,
149 	DDP_COMPONENT_AAL0,
150 	DDP_COMPONENT_GAMMA,
151 	DDP_COMPONENT_DITHER0,
152 	DDP_COMPONENT_DSI0,
153 };
154 
155 static const unsigned int mt8183_mtk_ddp_ext[] = {
156 	DDP_COMPONENT_OVL_2L1,
157 	DDP_COMPONENT_RDMA1,
158 	DDP_COMPONENT_DPI0,
159 };
160 
161 static const unsigned int mt8186_mtk_ddp_main[] = {
162 	DDP_COMPONENT_OVL0,
163 	DDP_COMPONENT_RDMA0,
164 	DDP_COMPONENT_COLOR0,
165 	DDP_COMPONENT_CCORR,
166 	DDP_COMPONENT_AAL0,
167 	DDP_COMPONENT_GAMMA,
168 	DDP_COMPONENT_POSTMASK0,
169 	DDP_COMPONENT_DITHER0,
170 	DDP_COMPONENT_DSI0,
171 };
172 
173 static const unsigned int mt8186_mtk_ddp_ext[] = {
174 	DDP_COMPONENT_OVL_2L0,
175 	DDP_COMPONENT_RDMA1,
176 	DDP_COMPONENT_DPI0,
177 };
178 
179 static const unsigned int mt8188_mtk_ddp_main[] = {
180 	DDP_COMPONENT_OVL0,
181 	DDP_COMPONENT_RDMA0,
182 	DDP_COMPONENT_COLOR0,
183 	DDP_COMPONENT_CCORR,
184 	DDP_COMPONENT_AAL0,
185 	DDP_COMPONENT_GAMMA,
186 	DDP_COMPONENT_POSTMASK0,
187 	DDP_COMPONENT_DITHER0,
188 	DDP_COMPONENT_DP_INTF0,
189 };
190 
191 static const unsigned int mt8192_mtk_ddp_main[] = {
192 	DDP_COMPONENT_OVL0,
193 	DDP_COMPONENT_OVL_2L0,
194 	DDP_COMPONENT_RDMA0,
195 	DDP_COMPONENT_COLOR0,
196 	DDP_COMPONENT_CCORR,
197 	DDP_COMPONENT_AAL0,
198 	DDP_COMPONENT_GAMMA,
199 	DDP_COMPONENT_POSTMASK0,
200 	DDP_COMPONENT_DITHER0,
201 	DDP_COMPONENT_DSI0,
202 };
203 
204 static const unsigned int mt8192_mtk_ddp_ext[] = {
205 	DDP_COMPONENT_OVL_2L2,
206 	DDP_COMPONENT_RDMA4,
207 	DDP_COMPONENT_DPI0,
208 };
209 
210 static const unsigned int mt8195_mtk_ddp_main[] = {
211 	DDP_COMPONENT_OVL0,
212 	DDP_COMPONENT_RDMA0,
213 	DDP_COMPONENT_COLOR0,
214 	DDP_COMPONENT_CCORR,
215 	DDP_COMPONENT_AAL0,
216 	DDP_COMPONENT_GAMMA,
217 	DDP_COMPONENT_DITHER0,
218 	DDP_COMPONENT_DSC0,
219 	DDP_COMPONENT_MERGE0,
220 	DDP_COMPONENT_DP_INTF0,
221 };
222 
223 static const unsigned int mt8195_mtk_ddp_ext[] = {
224 	DDP_COMPONENT_DRM_OVL_ADAPTOR,
225 	DDP_COMPONENT_MERGE5,
226 	DDP_COMPONENT_DP_INTF1,
227 };
228 
229 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
230 	.main_path = mt2701_mtk_ddp_main,
231 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
232 	.ext_path = mt2701_mtk_ddp_ext,
233 	.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
234 	.shadow_register = true,
235 	.mmsys_dev_num = 1,
236 };
237 
238 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
239 	.main_path = mt7623_mtk_ddp_main,
240 	.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
241 	.ext_path = mt7623_mtk_ddp_ext,
242 	.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
243 	.shadow_register = true,
244 	.mmsys_dev_num = 1,
245 };
246 
247 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
248 	.main_path = mt2712_mtk_ddp_main,
249 	.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
250 	.ext_path = mt2712_mtk_ddp_ext,
251 	.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
252 	.third_path = mt2712_mtk_ddp_third,
253 	.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
254 	.mmsys_dev_num = 1,
255 };
256 
257 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
258 	.main_path = mt8167_mtk_ddp_main,
259 	.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
260 	.mmsys_dev_num = 1,
261 };
262 
263 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
264 	.main_path = mt8173_mtk_ddp_main,
265 	.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
266 	.ext_path = mt8173_mtk_ddp_ext,
267 	.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
268 	.mmsys_dev_num = 1,
269 };
270 
271 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
272 	.main_path = mt8183_mtk_ddp_main,
273 	.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
274 	.ext_path = mt8183_mtk_ddp_ext,
275 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
276 	.mmsys_dev_num = 1,
277 };
278 
279 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
280 	.main_path = mt8186_mtk_ddp_main,
281 	.main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
282 	.ext_path = mt8186_mtk_ddp_ext,
283 	.ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
284 	.mmsys_dev_num = 1,
285 };
286 
287 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
288 	.main_path = mt8188_mtk_ddp_main,
289 	.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
290 };
291 
292 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
293 	.main_path = mt8192_mtk_ddp_main,
294 	.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
295 	.ext_path = mt8192_mtk_ddp_ext,
296 	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
297 	.mmsys_dev_num = 1,
298 };
299 
300 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
301 	.main_path = mt8195_mtk_ddp_main,
302 	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
303 	.mmsys_dev_num = 2,
304 };
305 
306 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
307 	.ext_path = mt8195_mtk_ddp_ext,
308 	.ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
309 	.mmsys_id = 1,
310 	.mmsys_dev_num = 2,
311 };
312 
313 static const struct of_device_id mtk_drm_of_ids[] = {
314 	{ .compatible = "mediatek,mt2701-mmsys",
315 	  .data = &mt2701_mmsys_driver_data},
316 	{ .compatible = "mediatek,mt7623-mmsys",
317 	  .data = &mt7623_mmsys_driver_data},
318 	{ .compatible = "mediatek,mt2712-mmsys",
319 	  .data = &mt2712_mmsys_driver_data},
320 	{ .compatible = "mediatek,mt8167-mmsys",
321 	  .data = &mt8167_mmsys_driver_data},
322 	{ .compatible = "mediatek,mt8173-mmsys",
323 	  .data = &mt8173_mmsys_driver_data},
324 	{ .compatible = "mediatek,mt8183-mmsys",
325 	  .data = &mt8183_mmsys_driver_data},
326 	{ .compatible = "mediatek,mt8186-mmsys",
327 	  .data = &mt8186_mmsys_driver_data},
328 	{ .compatible = "mediatek,mt8188-vdosys0",
329 	  .data = &mt8188_vdosys0_driver_data},
330 	{ .compatible = "mediatek,mt8192-mmsys",
331 	  .data = &mt8192_mmsys_driver_data},
332 	{ .compatible = "mediatek,mt8195-mmsys",
333 	  .data = &mt8195_vdosys0_driver_data},
334 	{ .compatible = "mediatek,mt8195-vdosys0",
335 	  .data = &mt8195_vdosys0_driver_data},
336 	{ .compatible = "mediatek,mt8195-vdosys1",
337 	  .data = &mt8195_vdosys1_driver_data},
338 	{ }
339 };
340 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
341 
342 static int mtk_drm_match(struct device *dev, void *data)
343 {
344 	if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
345 		return true;
346 	return false;
347 }
348 
349 static bool mtk_drm_get_all_drm_priv(struct device *dev)
350 {
351 	struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
352 	struct mtk_drm_private *all_drm_priv[MAX_CRTC];
353 	struct device_node *phandle = dev->parent->of_node;
354 	const struct of_device_id *of_id;
355 	struct device_node *node;
356 	struct device *drm_dev;
357 	int cnt = 0;
358 	int i, j;
359 
360 	for_each_child_of_node(phandle->parent, node) {
361 		struct platform_device *pdev;
362 
363 		of_id = of_match_node(mtk_drm_of_ids, node);
364 		if (!of_id)
365 			continue;
366 
367 		pdev = of_find_device_by_node(node);
368 		if (!pdev)
369 			continue;
370 
371 		drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
372 		if (!drm_dev || !dev_get_drvdata(drm_dev))
373 			continue;
374 
375 		all_drm_priv[cnt] = dev_get_drvdata(drm_dev);
376 		if (all_drm_priv[cnt] && all_drm_priv[cnt]->mtk_drm_bound)
377 			cnt++;
378 	}
379 
380 	if (drm_priv->data->mmsys_dev_num == cnt) {
381 		for (i = 0; i < cnt; i++)
382 			for (j = 0; j < cnt; j++)
383 				all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
384 
385 		return true;
386 	}
387 
388 	return false;
389 }
390 
391 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
392 {
393 	const struct mtk_mmsys_driver_data *drv_data = private->data;
394 	int i;
395 
396 	if (drv_data->main_path)
397 		for (i = 0; i < drv_data->main_len; i++)
398 			if (drv_data->main_path[i] == comp_id)
399 				return true;
400 
401 	if (drv_data->ext_path)
402 		for (i = 0; i < drv_data->ext_len; i++)
403 			if (drv_data->ext_path[i] == comp_id)
404 				return true;
405 
406 	if (drv_data->third_path)
407 		for (i = 0; i < drv_data->third_len; i++)
408 			if (drv_data->third_path[i] == comp_id)
409 				return true;
410 
411 	return false;
412 }
413 
414 static int mtk_drm_kms_init(struct drm_device *drm)
415 {
416 	struct mtk_drm_private *private = drm->dev_private;
417 	struct mtk_drm_private *priv_n;
418 	struct device *dma_dev = NULL;
419 	int ret, i, j;
420 
421 	if (drm_firmware_drivers_only())
422 		return -ENODEV;
423 
424 	ret = drmm_mode_config_init(drm);
425 	if (ret)
426 		goto put_mutex_dev;
427 
428 	drm->mode_config.min_width = 64;
429 	drm->mode_config.min_height = 64;
430 
431 	/*
432 	 * set max width and height as default value(4096x4096).
433 	 * this value would be used to check framebuffer size limitation
434 	 * at drm_mode_addfb().
435 	 */
436 	drm->mode_config.max_width = 4096;
437 	drm->mode_config.max_height = 4096;
438 	drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
439 	drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
440 
441 	for (i = 0; i < private->data->mmsys_dev_num; i++) {
442 		drm->dev_private = private->all_drm_private[i];
443 		ret = component_bind_all(private->all_drm_private[i]->dev, drm);
444 		if (ret)
445 			goto put_mutex_dev;
446 	}
447 
448 	/*
449 	 * Ensure internal panels are at the top of the connector list before
450 	 * crtc creation.
451 	 */
452 	drm_helper_move_panel_connectors_to_head(drm);
453 
454 	/*
455 	 * 1. We currently support two fixed data streams, each optional,
456 	 *    and each statically assigned to a crtc:
457 	 *    OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
458 	 * 2. For multi mmsys architecture, crtc path data are located in
459 	 *    different drm private data structures. Loop through crtc index to
460 	 *    create crtc from the main path and then ext_path and finally the
461 	 *    third path.
462 	 */
463 	for (i = 0; i < MAX_CRTC; i++) {
464 		for (j = 0; j < private->data->mmsys_dev_num; j++) {
465 			priv_n = private->all_drm_private[j];
466 
467 			if (i == 0 && priv_n->data->main_len) {
468 				ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
469 							  priv_n->data->main_len, j);
470 				if (ret)
471 					goto err_component_unbind;
472 
473 				continue;
474 			} else if (i == 1 && priv_n->data->ext_len) {
475 				ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
476 							  priv_n->data->ext_len, j);
477 				if (ret)
478 					goto err_component_unbind;
479 
480 				continue;
481 			} else if (i == 2 && priv_n->data->third_len) {
482 				ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
483 							  priv_n->data->third_len, j);
484 				if (ret)
485 					goto err_component_unbind;
486 
487 				continue;
488 			}
489 		}
490 	}
491 
492 	/* Use OVL device for all DMA memory allocations */
493 	dma_dev = mtk_drm_crtc_dma_dev_get(drm_crtc_from_index(drm, 0));
494 	if (!dma_dev) {
495 		ret = -ENODEV;
496 		dev_err(drm->dev, "Need at least one OVL device\n");
497 		goto err_component_unbind;
498 	}
499 
500 	for (i = 0; i < private->data->mmsys_dev_num; i++)
501 		private->all_drm_private[i]->dma_dev = dma_dev;
502 
503 	/*
504 	 * Configure the DMA segment size to make sure we get contiguous IOVA
505 	 * when importing PRIME buffers.
506 	 */
507 	ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
508 	if (ret) {
509 		dev_err(dma_dev, "Failed to set DMA segment size\n");
510 		goto err_component_unbind;
511 	}
512 
513 	ret = drm_vblank_init(drm, MAX_CRTC);
514 	if (ret < 0)
515 		goto err_component_unbind;
516 
517 	drm_kms_helper_poll_init(drm);
518 	drm_mode_config_reset(drm);
519 
520 	return 0;
521 
522 err_component_unbind:
523 	for (i = 0; i < private->data->mmsys_dev_num; i++)
524 		component_unbind_all(private->all_drm_private[i]->dev, drm);
525 put_mutex_dev:
526 	for (i = 0; i < private->data->mmsys_dev_num; i++)
527 		put_device(private->all_drm_private[i]->mutex_dev);
528 
529 	return ret;
530 }
531 
532 static void mtk_drm_kms_deinit(struct drm_device *drm)
533 {
534 	drm_kms_helper_poll_fini(drm);
535 	drm_atomic_helper_shutdown(drm);
536 
537 	component_unbind_all(drm->dev, drm);
538 }
539 
540 DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
541 
542 /*
543  * We need to override this because the device used to import the memory is
544  * not dev->dev, as drm_gem_prime_import() expects.
545  */
546 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev,
547 						       struct dma_buf *dma_buf)
548 {
549 	struct mtk_drm_private *private = dev->dev_private;
550 
551 	return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
552 }
553 
554 static const struct drm_driver mtk_drm_driver = {
555 	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
556 
557 	.dumb_create = mtk_drm_gem_dumb_create,
558 
559 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
560 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
561 	.gem_prime_import = mtk_drm_gem_prime_import,
562 	.gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
563 	.gem_prime_mmap = drm_gem_prime_mmap,
564 	.fops = &mtk_drm_fops,
565 
566 	.name = DRIVER_NAME,
567 	.desc = DRIVER_DESC,
568 	.date = DRIVER_DATE,
569 	.major = DRIVER_MAJOR,
570 	.minor = DRIVER_MINOR,
571 };
572 
573 static int compare_dev(struct device *dev, void *data)
574 {
575 	return dev == (struct device *)data;
576 }
577 
578 static int mtk_drm_bind(struct device *dev)
579 {
580 	struct mtk_drm_private *private = dev_get_drvdata(dev);
581 	struct platform_device *pdev;
582 	struct drm_device *drm;
583 	int ret, i;
584 
585 	if (!iommu_present(&platform_bus_type))
586 		return -EPROBE_DEFER;
587 
588 	pdev = of_find_device_by_node(private->mutex_node);
589 	if (!pdev) {
590 		dev_err(dev, "Waiting for disp-mutex device %pOF\n",
591 			private->mutex_node);
592 		of_node_put(private->mutex_node);
593 		return -EPROBE_DEFER;
594 	}
595 
596 	private->mutex_dev = &pdev->dev;
597 	private->mtk_drm_bound = true;
598 	private->dev = dev;
599 
600 	if (!mtk_drm_get_all_drm_priv(dev))
601 		return 0;
602 
603 	drm = drm_dev_alloc(&mtk_drm_driver, dev);
604 	if (IS_ERR(drm))
605 		return PTR_ERR(drm);
606 
607 	private->drm_master = true;
608 	drm->dev_private = private;
609 	for (i = 0; i < private->data->mmsys_dev_num; i++)
610 		private->all_drm_private[i]->drm = drm;
611 
612 	ret = mtk_drm_kms_init(drm);
613 	if (ret < 0)
614 		goto err_free;
615 
616 	ret = drm_dev_register(drm, 0);
617 	if (ret < 0)
618 		goto err_deinit;
619 
620 	drm_fbdev_generic_setup(drm, 32);
621 
622 	return 0;
623 
624 err_deinit:
625 	mtk_drm_kms_deinit(drm);
626 err_free:
627 	private->drm = NULL;
628 	drm_dev_put(drm);
629 	return ret;
630 }
631 
632 static void mtk_drm_unbind(struct device *dev)
633 {
634 	struct mtk_drm_private *private = dev_get_drvdata(dev);
635 
636 	/* for multi mmsys dev, unregister drm dev in mmsys master */
637 	if (private->drm_master) {
638 		drm_dev_unregister(private->drm);
639 		mtk_drm_kms_deinit(private->drm);
640 		drm_dev_put(private->drm);
641 	}
642 	private->mtk_drm_bound = false;
643 	private->drm_master = false;
644 	private->drm = NULL;
645 }
646 
647 static const struct component_master_ops mtk_drm_ops = {
648 	.bind		= mtk_drm_bind,
649 	.unbind		= mtk_drm_unbind,
650 };
651 
652 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
653 	{ .compatible = "mediatek,mt8167-disp-aal",
654 	  .data = (void *)MTK_DISP_AAL},
655 	{ .compatible = "mediatek,mt8173-disp-aal",
656 	  .data = (void *)MTK_DISP_AAL},
657 	{ .compatible = "mediatek,mt8183-disp-aal",
658 	  .data = (void *)MTK_DISP_AAL},
659 	{ .compatible = "mediatek,mt8192-disp-aal",
660 	  .data = (void *)MTK_DISP_AAL},
661 	{ .compatible = "mediatek,mt8167-disp-ccorr",
662 	  .data = (void *)MTK_DISP_CCORR },
663 	{ .compatible = "mediatek,mt8183-disp-ccorr",
664 	  .data = (void *)MTK_DISP_CCORR },
665 	{ .compatible = "mediatek,mt8192-disp-ccorr",
666 	  .data = (void *)MTK_DISP_CCORR },
667 	{ .compatible = "mediatek,mt2701-disp-color",
668 	  .data = (void *)MTK_DISP_COLOR },
669 	{ .compatible = "mediatek,mt8167-disp-color",
670 	  .data = (void *)MTK_DISP_COLOR },
671 	{ .compatible = "mediatek,mt8173-disp-color",
672 	  .data = (void *)MTK_DISP_COLOR },
673 	{ .compatible = "mediatek,mt8167-disp-dither",
674 	  .data = (void *)MTK_DISP_DITHER },
675 	{ .compatible = "mediatek,mt8183-disp-dither",
676 	  .data = (void *)MTK_DISP_DITHER },
677 	{ .compatible = "mediatek,mt8195-disp-dsc",
678 	  .data = (void *)MTK_DISP_DSC },
679 	{ .compatible = "mediatek,mt8167-disp-gamma",
680 	  .data = (void *)MTK_DISP_GAMMA, },
681 	{ .compatible = "mediatek,mt8173-disp-gamma",
682 	  .data = (void *)MTK_DISP_GAMMA, },
683 	{ .compatible = "mediatek,mt8183-disp-gamma",
684 	  .data = (void *)MTK_DISP_GAMMA, },
685 	{ .compatible = "mediatek,mt8195-disp-merge",
686 	  .data = (void *)MTK_DISP_MERGE },
687 	{ .compatible = "mediatek,mt2701-disp-mutex",
688 	  .data = (void *)MTK_DISP_MUTEX },
689 	{ .compatible = "mediatek,mt2712-disp-mutex",
690 	  .data = (void *)MTK_DISP_MUTEX },
691 	{ .compatible = "mediatek,mt8167-disp-mutex",
692 	  .data = (void *)MTK_DISP_MUTEX },
693 	{ .compatible = "mediatek,mt8173-disp-mutex",
694 	  .data = (void *)MTK_DISP_MUTEX },
695 	{ .compatible = "mediatek,mt8183-disp-mutex",
696 	  .data = (void *)MTK_DISP_MUTEX },
697 	{ .compatible = "mediatek,mt8186-disp-mutex",
698 	  .data = (void *)MTK_DISP_MUTEX },
699 	{ .compatible = "mediatek,mt8188-disp-mutex",
700 	  .data = (void *)MTK_DISP_MUTEX },
701 	{ .compatible = "mediatek,mt8192-disp-mutex",
702 	  .data = (void *)MTK_DISP_MUTEX },
703 	{ .compatible = "mediatek,mt8195-disp-mutex",
704 	  .data = (void *)MTK_DISP_MUTEX },
705 	{ .compatible = "mediatek,mt8173-disp-od",
706 	  .data = (void *)MTK_DISP_OD },
707 	{ .compatible = "mediatek,mt2701-disp-ovl",
708 	  .data = (void *)MTK_DISP_OVL },
709 	{ .compatible = "mediatek,mt8167-disp-ovl",
710 	  .data = (void *)MTK_DISP_OVL },
711 	{ .compatible = "mediatek,mt8173-disp-ovl",
712 	  .data = (void *)MTK_DISP_OVL },
713 	{ .compatible = "mediatek,mt8183-disp-ovl",
714 	  .data = (void *)MTK_DISP_OVL },
715 	{ .compatible = "mediatek,mt8192-disp-ovl",
716 	  .data = (void *)MTK_DISP_OVL },
717 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
718 	  .data = (void *)MTK_DISP_OVL_2L },
719 	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
720 	  .data = (void *)MTK_DISP_OVL_2L },
721 	{ .compatible = "mediatek,mt8192-disp-postmask",
722 	  .data = (void *)MTK_DISP_POSTMASK },
723 	{ .compatible = "mediatek,mt2701-disp-pwm",
724 	  .data = (void *)MTK_DISP_BLS },
725 	{ .compatible = "mediatek,mt8167-disp-pwm",
726 	  .data = (void *)MTK_DISP_PWM },
727 	{ .compatible = "mediatek,mt8173-disp-pwm",
728 	  .data = (void *)MTK_DISP_PWM },
729 	{ .compatible = "mediatek,mt2701-disp-rdma",
730 	  .data = (void *)MTK_DISP_RDMA },
731 	{ .compatible = "mediatek,mt8167-disp-rdma",
732 	  .data = (void *)MTK_DISP_RDMA },
733 	{ .compatible = "mediatek,mt8173-disp-rdma",
734 	  .data = (void *)MTK_DISP_RDMA },
735 	{ .compatible = "mediatek,mt8183-disp-rdma",
736 	  .data = (void *)MTK_DISP_RDMA },
737 	{ .compatible = "mediatek,mt8195-disp-rdma",
738 	  .data = (void *)MTK_DISP_RDMA },
739 	{ .compatible = "mediatek,mt8173-disp-ufoe",
740 	  .data = (void *)MTK_DISP_UFOE },
741 	{ .compatible = "mediatek,mt8173-disp-wdma",
742 	  .data = (void *)MTK_DISP_WDMA },
743 	{ .compatible = "mediatek,mt2701-dpi",
744 	  .data = (void *)MTK_DPI },
745 	{ .compatible = "mediatek,mt8167-dsi",
746 	  .data = (void *)MTK_DSI },
747 	{ .compatible = "mediatek,mt8173-dpi",
748 	  .data = (void *)MTK_DPI },
749 	{ .compatible = "mediatek,mt8183-dpi",
750 	  .data = (void *)MTK_DPI },
751 	{ .compatible = "mediatek,mt8186-dpi",
752 	  .data = (void *)MTK_DPI },
753 	{ .compatible = "mediatek,mt8188-dp-intf",
754 	  .data = (void *)MTK_DP_INTF },
755 	{ .compatible = "mediatek,mt8192-dpi",
756 	  .data = (void *)MTK_DPI },
757 	{ .compatible = "mediatek,mt8195-dp-intf",
758 	  .data = (void *)MTK_DP_INTF },
759 	{ .compatible = "mediatek,mt2701-dsi",
760 	  .data = (void *)MTK_DSI },
761 	{ .compatible = "mediatek,mt8173-dsi",
762 	  .data = (void *)MTK_DSI },
763 	{ .compatible = "mediatek,mt8183-dsi",
764 	  .data = (void *)MTK_DSI },
765 	{ .compatible = "mediatek,mt8186-dsi",
766 	  .data = (void *)MTK_DSI },
767 	{ }
768 };
769 
770 static int mtk_drm_probe(struct platform_device *pdev)
771 {
772 	struct device *dev = &pdev->dev;
773 	struct device_node *phandle = dev->parent->of_node;
774 	const struct of_device_id *of_id;
775 	struct mtk_drm_private *private;
776 	struct device_node *node;
777 	struct component_match *match = NULL;
778 	struct platform_device *ovl_adaptor;
779 	int ret;
780 	int i;
781 
782 	private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
783 	if (!private)
784 		return -ENOMEM;
785 
786 	private->mmsys_dev = dev->parent;
787 	if (!private->mmsys_dev) {
788 		dev_err(dev, "Failed to get MMSYS device\n");
789 		return -ENODEV;
790 	}
791 
792 	of_id = of_match_node(mtk_drm_of_ids, phandle);
793 	if (!of_id)
794 		return -ENODEV;
795 
796 	private->data = of_id->data;
797 
798 	private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
799 						      sizeof(*private->all_drm_private),
800 						      GFP_KERNEL);
801 	if (!private->all_drm_private)
802 		return -ENOMEM;
803 
804 	/* Bringup ovl_adaptor */
805 	if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {
806 		ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
807 							    PLATFORM_DEVID_AUTO,
808 							    (void *)private->mmsys_dev,
809 							    sizeof(*private->mmsys_dev));
810 		private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
811 		mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
812 				  DDP_COMPONENT_DRM_OVL_ADAPTOR);
813 		component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
814 	}
815 
816 	/* Iterate over sibling DISP function blocks */
817 	for_each_child_of_node(phandle->parent, node) {
818 		const struct of_device_id *of_id;
819 		enum mtk_ddp_comp_type comp_type;
820 		int comp_id;
821 
822 		of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
823 		if (!of_id)
824 			continue;
825 
826 		if (!of_device_is_available(node)) {
827 			dev_dbg(dev, "Skipping disabled component %pOF\n",
828 				node);
829 			continue;
830 		}
831 
832 		comp_type = (enum mtk_ddp_comp_type)of_id->data;
833 
834 		if (comp_type == MTK_DISP_MUTEX) {
835 			int id;
836 
837 			id = of_alias_get_id(node, "mutex");
838 			if (id < 0 || id == private->data->mmsys_id) {
839 				private->mutex_node = of_node_get(node);
840 				dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id);
841 			}
842 			continue;
843 		}
844 
845 		comp_id = mtk_ddp_comp_get_id(node, comp_type);
846 		if (comp_id < 0) {
847 			dev_warn(dev, "Skipping unknown component %pOF\n",
848 				 node);
849 			continue;
850 		}
851 
852 		if (!mtk_drm_find_mmsys_comp(private, comp_id))
853 			continue;
854 
855 		private->comp_node[comp_id] = of_node_get(node);
856 
857 		/*
858 		 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
859 		 * blocks have separate component platform drivers and initialize their own
860 		 * DDP component structure. The others are initialized here.
861 		 */
862 		if (comp_type == MTK_DISP_AAL ||
863 		    comp_type == MTK_DISP_CCORR ||
864 		    comp_type == MTK_DISP_COLOR ||
865 		    comp_type == MTK_DISP_GAMMA ||
866 		    comp_type == MTK_DISP_MERGE ||
867 		    comp_type == MTK_DISP_OVL ||
868 		    comp_type == MTK_DISP_OVL_2L ||
869 		    comp_type == MTK_DISP_OVL_ADAPTOR ||
870 		    comp_type == MTK_DISP_RDMA ||
871 		    comp_type == MTK_DP_INTF ||
872 		    comp_type == MTK_DPI ||
873 		    comp_type == MTK_DSI) {
874 			dev_info(dev, "Adding component match for %pOF\n",
875 				 node);
876 			drm_of_component_match_add(dev, &match, component_compare_of,
877 						   node);
878 		}
879 
880 		ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
881 		if (ret) {
882 			of_node_put(node);
883 			goto err_node;
884 		}
885 	}
886 
887 	if (!private->mutex_node) {
888 		dev_err(dev, "Failed to find disp-mutex node\n");
889 		ret = -ENODEV;
890 		goto err_node;
891 	}
892 
893 	pm_runtime_enable(dev);
894 
895 	platform_set_drvdata(pdev, private);
896 
897 	ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
898 	if (ret)
899 		goto err_pm;
900 
901 	return 0;
902 
903 err_pm:
904 	pm_runtime_disable(dev);
905 err_node:
906 	of_node_put(private->mutex_node);
907 	for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
908 		of_node_put(private->comp_node[i]);
909 	return ret;
910 }
911 
912 static int mtk_drm_remove(struct platform_device *pdev)
913 {
914 	struct mtk_drm_private *private = platform_get_drvdata(pdev);
915 	int i;
916 
917 	component_master_del(&pdev->dev, &mtk_drm_ops);
918 	pm_runtime_disable(&pdev->dev);
919 	of_node_put(private->mutex_node);
920 	for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
921 		of_node_put(private->comp_node[i]);
922 
923 	return 0;
924 }
925 
926 static int mtk_drm_sys_prepare(struct device *dev)
927 {
928 	struct mtk_drm_private *private = dev_get_drvdata(dev);
929 	struct drm_device *drm = private->drm;
930 
931 	if (private->drm_master)
932 		return drm_mode_config_helper_suspend(drm);
933 	else
934 		return 0;
935 }
936 
937 static void mtk_drm_sys_complete(struct device *dev)
938 {
939 	struct mtk_drm_private *private = dev_get_drvdata(dev);
940 	struct drm_device *drm = private->drm;
941 	int ret = 0;
942 
943 	if (private->drm_master)
944 		ret = drm_mode_config_helper_resume(drm);
945 	if (ret)
946 		dev_err(dev, "Failed to resume\n");
947 }
948 
949 static const struct dev_pm_ops mtk_drm_pm_ops = {
950 	.prepare = mtk_drm_sys_prepare,
951 	.complete = mtk_drm_sys_complete,
952 };
953 
954 static struct platform_driver mtk_drm_platform_driver = {
955 	.probe	= mtk_drm_probe,
956 	.remove	= mtk_drm_remove,
957 	.driver	= {
958 		.name	= "mediatek-drm",
959 		.pm     = &mtk_drm_pm_ops,
960 	},
961 };
962 
963 static struct platform_driver * const mtk_drm_drivers[] = {
964 	&mtk_disp_aal_driver,
965 	&mtk_disp_ccorr_driver,
966 	&mtk_disp_color_driver,
967 	&mtk_disp_gamma_driver,
968 	&mtk_disp_merge_driver,
969 	&mtk_disp_ovl_adaptor_driver,
970 	&mtk_disp_ovl_driver,
971 	&mtk_disp_rdma_driver,
972 	&mtk_dpi_driver,
973 	&mtk_drm_platform_driver,
974 	&mtk_dsi_driver,
975 	&mtk_ethdr_driver,
976 	&mtk_mdp_rdma_driver,
977 };
978 
979 static int __init mtk_drm_init(void)
980 {
981 	return platform_register_drivers(mtk_drm_drivers,
982 					 ARRAY_SIZE(mtk_drm_drivers));
983 }
984 
985 static void __exit mtk_drm_exit(void)
986 {
987 	platform_unregister_drivers(mtk_drm_drivers,
988 				    ARRAY_SIZE(mtk_drm_drivers));
989 }
990 
991 module_init(mtk_drm_init);
992 module_exit(mtk_drm_exit);
993 
994 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
995 MODULE_DESCRIPTION("Mediatek SoC DRM driver");
996 MODULE_LICENSE("GPL v2");
997