1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  * Author: YT SHEN <yt.shen@mediatek.com>
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/component.h>
10 #include <linux/iommu.h>
11 #include <linux/module.h>
12 #include <linux/of_address.h>
13 #include <linux/of_platform.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/dma-mapping.h>
16 
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_drv.h>
20 #include <drm/drm_fb_helper.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_gem.h>
23 #include <drm/drm_gem_cma_helper.h>
24 #include <drm/drm_gem_framebuffer_helper.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_probe_helper.h>
27 #include <drm/drm_vblank.h>
28 
29 #include "mtk_drm_crtc.h"
30 #include "mtk_drm_ddp_comp.h"
31 #include "mtk_drm_drv.h"
32 #include "mtk_drm_gem.h"
33 
34 #define DRIVER_NAME "mediatek"
35 #define DRIVER_DESC "Mediatek SoC DRM"
36 #define DRIVER_DATE "20150513"
37 #define DRIVER_MAJOR 1
38 #define DRIVER_MINOR 0
39 
40 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
41 	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
42 };
43 
44 static struct drm_framebuffer *
45 mtk_drm_mode_fb_create(struct drm_device *dev,
46 		       struct drm_file *file,
47 		       const struct drm_mode_fb_cmd2 *cmd)
48 {
49 	const struct drm_format_info *info = drm_get_format_info(dev, cmd);
50 
51 	if (info->num_planes != 1)
52 		return ERR_PTR(-EINVAL);
53 
54 	return drm_gem_fb_create(dev, file, cmd);
55 }
56 
57 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
58 	.fb_create = mtk_drm_mode_fb_create,
59 	.atomic_check = drm_atomic_helper_check,
60 	.atomic_commit = drm_atomic_helper_commit,
61 };
62 
63 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
64 	DDP_COMPONENT_OVL0,
65 	DDP_COMPONENT_RDMA0,
66 	DDP_COMPONENT_COLOR0,
67 	DDP_COMPONENT_BLS,
68 	DDP_COMPONENT_DSI0,
69 };
70 
71 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
72 	DDP_COMPONENT_RDMA1,
73 	DDP_COMPONENT_DPI0,
74 };
75 
76 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = {
77 	DDP_COMPONENT_OVL0,
78 	DDP_COMPONENT_RDMA0,
79 	DDP_COMPONENT_COLOR0,
80 	DDP_COMPONENT_BLS,
81 	DDP_COMPONENT_DPI0,
82 };
83 
84 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = {
85 	DDP_COMPONENT_RDMA1,
86 	DDP_COMPONENT_DSI0,
87 };
88 
89 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
90 	DDP_COMPONENT_OVL0,
91 	DDP_COMPONENT_COLOR0,
92 	DDP_COMPONENT_AAL0,
93 	DDP_COMPONENT_OD0,
94 	DDP_COMPONENT_RDMA0,
95 	DDP_COMPONENT_DPI0,
96 	DDP_COMPONENT_PWM0,
97 };
98 
99 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
100 	DDP_COMPONENT_OVL1,
101 	DDP_COMPONENT_COLOR1,
102 	DDP_COMPONENT_AAL1,
103 	DDP_COMPONENT_OD1,
104 	DDP_COMPONENT_RDMA1,
105 	DDP_COMPONENT_DPI1,
106 	DDP_COMPONENT_PWM1,
107 };
108 
109 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
110 	DDP_COMPONENT_RDMA2,
111 	DDP_COMPONENT_DSI3,
112 	DDP_COMPONENT_PWM2,
113 };
114 
115 static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
116 	DDP_COMPONENT_OVL0,
117 	DDP_COMPONENT_COLOR0,
118 	DDP_COMPONENT_CCORR,
119 	DDP_COMPONENT_AAL0,
120 	DDP_COMPONENT_GAMMA,
121 	DDP_COMPONENT_DITHER0,
122 	DDP_COMPONENT_RDMA0,
123 	DDP_COMPONENT_DSI0,
124 };
125 
126 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
127 	DDP_COMPONENT_OVL0,
128 	DDP_COMPONENT_COLOR0,
129 	DDP_COMPONENT_AAL0,
130 	DDP_COMPONENT_OD0,
131 	DDP_COMPONENT_RDMA0,
132 	DDP_COMPONENT_UFOE,
133 	DDP_COMPONENT_DSI0,
134 	DDP_COMPONENT_PWM0,
135 };
136 
137 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
138 	DDP_COMPONENT_OVL1,
139 	DDP_COMPONENT_COLOR1,
140 	DDP_COMPONENT_GAMMA,
141 	DDP_COMPONENT_RDMA1,
142 	DDP_COMPONENT_DPI0,
143 };
144 
145 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
146 	DDP_COMPONENT_OVL0,
147 	DDP_COMPONENT_OVL_2L0,
148 	DDP_COMPONENT_RDMA0,
149 	DDP_COMPONENT_COLOR0,
150 	DDP_COMPONENT_CCORR,
151 	DDP_COMPONENT_AAL0,
152 	DDP_COMPONENT_GAMMA,
153 	DDP_COMPONENT_DITHER0,
154 	DDP_COMPONENT_DSI0,
155 };
156 
157 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
158 	DDP_COMPONENT_OVL_2L1,
159 	DDP_COMPONENT_RDMA1,
160 	DDP_COMPONENT_DPI0,
161 };
162 
163 static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] = {
164 	DDP_COMPONENT_OVL0,
165 	DDP_COMPONENT_RDMA0,
166 	DDP_COMPONENT_COLOR0,
167 	DDP_COMPONENT_CCORR,
168 	DDP_COMPONENT_AAL0,
169 	DDP_COMPONENT_GAMMA,
170 	DDP_COMPONENT_POSTMASK0,
171 	DDP_COMPONENT_DITHER0,
172 	DDP_COMPONENT_DSI0,
173 };
174 
175 static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] = {
176 	DDP_COMPONENT_OVL_2L0,
177 	DDP_COMPONENT_RDMA1,
178 	DDP_COMPONENT_DPI0,
179 };
180 
181 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
182 	DDP_COMPONENT_OVL0,
183 	DDP_COMPONENT_OVL_2L0,
184 	DDP_COMPONENT_RDMA0,
185 	DDP_COMPONENT_COLOR0,
186 	DDP_COMPONENT_CCORR,
187 	DDP_COMPONENT_AAL0,
188 	DDP_COMPONENT_GAMMA,
189 	DDP_COMPONENT_POSTMASK0,
190 	DDP_COMPONENT_DITHER0,
191 	DDP_COMPONENT_DSI0,
192 };
193 
194 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
195 	DDP_COMPONENT_OVL_2L2,
196 	DDP_COMPONENT_RDMA4,
197 	DDP_COMPONENT_DPI0,
198 };
199 
200 static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
201 	DDP_COMPONENT_OVL0,
202 	DDP_COMPONENT_RDMA0,
203 	DDP_COMPONENT_COLOR0,
204 	DDP_COMPONENT_CCORR,
205 	DDP_COMPONENT_AAL0,
206 	DDP_COMPONENT_GAMMA,
207 	DDP_COMPONENT_DITHER0,
208 	DDP_COMPONENT_DSC0,
209 	DDP_COMPONENT_MERGE0,
210 	DDP_COMPONENT_DP_INTF0,
211 };
212 
213 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
214 	.main_path = mt2701_mtk_ddp_main,
215 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
216 	.ext_path = mt2701_mtk_ddp_ext,
217 	.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
218 	.shadow_register = true,
219 };
220 
221 static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
222 	.num_drv_data = 1,
223 	.drv_data = {
224 		&mt2701_mmsys_driver_data,
225 	},
226 };
227 
228 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
229 	.main_path = mt7623_mtk_ddp_main,
230 	.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
231 	.ext_path = mt7623_mtk_ddp_ext,
232 	.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
233 	.shadow_register = true,
234 };
235 
236 static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
237 	.num_drv_data = 1,
238 	.drv_data = {
239 		&mt7623_mmsys_driver_data,
240 	},
241 };
242 
243 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
244 	.main_path = mt2712_mtk_ddp_main,
245 	.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
246 	.ext_path = mt2712_mtk_ddp_ext,
247 	.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
248 	.third_path = mt2712_mtk_ddp_third,
249 	.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
250 };
251 
252 static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
253 	.num_drv_data = 1,
254 	.drv_data = {
255 		&mt2712_mmsys_driver_data,
256 	},
257 };
258 
259 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
260 	.main_path = mt8167_mtk_ddp_main,
261 	.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
262 };
263 
264 static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
265 	.num_drv_data = 1,
266 	.drv_data = {
267 		&mt8167_mmsys_driver_data,
268 	},
269 };
270 
271 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
272 	.main_path = mt8173_mtk_ddp_main,
273 	.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
274 	.ext_path = mt8173_mtk_ddp_ext,
275 	.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
276 };
277 
278 static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
279 	.num_drv_data = 1,
280 	.drv_data = {
281 		&mt8173_mmsys_driver_data,
282 	},
283 };
284 
285 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
286 	.main_path = mt8183_mtk_ddp_main,
287 	.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
288 	.ext_path = mt8183_mtk_ddp_ext,
289 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
290 };
291 
292 static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
293 	.num_drv_data = 1,
294 	.drv_data = {
295 		&mt8183_mmsys_driver_data,
296 	},
297 };
298 
299 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
300 	.main_path = mt8186_mtk_ddp_main,
301 	.main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
302 	.ext_path = mt8186_mtk_ddp_ext,
303 	.ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
304 };
305 
306 static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
307 	.num_drv_data = 1,
308 	.drv_data = {
309 		&mt8186_mmsys_driver_data,
310 	},
311 };
312 
313 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
314 	.main_path = mt8192_mtk_ddp_main,
315 	.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
316 	.ext_path = mt8192_mtk_ddp_ext,
317 	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
318 };
319 
320 static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
321 	.num_drv_data = 1,
322 	.drv_data = {
323 		&mt8192_mmsys_driver_data,
324 	},
325 };
326 
327 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
328 	.io_start = 0x1c01a000,
329 	.main_path = mt8195_mtk_ddp_main,
330 	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
331 };
332 
333 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
334 	.io_start = 0x1c100000,
335 };
336 
337 static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
338 	.num_drv_data = 1,
339 	.drv_data = {
340 		&mt8195_vdosys0_driver_data,
341 		&mt8195_vdosys1_driver_data,
342 	},
343 };
344 
345 static int mtk_drm_kms_init(struct drm_device *drm)
346 {
347 	struct mtk_drm_private *private = drm->dev_private;
348 	struct platform_device *pdev;
349 	struct device_node *np;
350 	struct device *dma_dev;
351 	int ret;
352 
353 	if (drm_firmware_drivers_only())
354 		return -ENODEV;
355 
356 	if (!iommu_present(&platform_bus_type))
357 		return -EPROBE_DEFER;
358 
359 	pdev = of_find_device_by_node(private->mutex_node);
360 	if (!pdev) {
361 		dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
362 			private->mutex_node);
363 		of_node_put(private->mutex_node);
364 		return -EPROBE_DEFER;
365 	}
366 	private->mutex_dev = &pdev->dev;
367 
368 	ret = drmm_mode_config_init(drm);
369 	if (ret)
370 		goto put_mutex_dev;
371 
372 	drm->mode_config.min_width = 64;
373 	drm->mode_config.min_height = 64;
374 
375 	/*
376 	 * set max width and height as default value(4096x4096).
377 	 * this value would be used to check framebuffer size limitation
378 	 * at drm_mode_addfb().
379 	 */
380 	drm->mode_config.max_width = 4096;
381 	drm->mode_config.max_height = 4096;
382 	drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
383 	drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
384 
385 	ret = component_bind_all(drm->dev, drm);
386 	if (ret)
387 		goto put_mutex_dev;
388 
389 	/*
390 	 * We currently support two fixed data streams, each optional,
391 	 * and each statically assigned to a crtc:
392 	 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
393 	 */
394 	ret = mtk_drm_crtc_create(drm, private->data->main_path,
395 				  private->data->main_len);
396 	if (ret < 0)
397 		goto err_component_unbind;
398 	/* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
399 	ret = mtk_drm_crtc_create(drm, private->data->ext_path,
400 				  private->data->ext_len);
401 	if (ret < 0)
402 		goto err_component_unbind;
403 
404 	ret = mtk_drm_crtc_create(drm, private->data->third_path,
405 				  private->data->third_len);
406 	if (ret < 0)
407 		goto err_component_unbind;
408 
409 	/* Use OVL device for all DMA memory allocations */
410 	np = private->comp_node[private->data->main_path[0]] ?:
411 	     private->comp_node[private->data->ext_path[0]];
412 	pdev = of_find_device_by_node(np);
413 	if (!pdev) {
414 		ret = -ENODEV;
415 		dev_err(drm->dev, "Need at least one OVL device\n");
416 		goto err_component_unbind;
417 	}
418 
419 	dma_dev = &pdev->dev;
420 	private->dma_dev = dma_dev;
421 
422 	/*
423 	 * Configure the DMA segment size to make sure we get contiguous IOVA
424 	 * when importing PRIME buffers.
425 	 */
426 	ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
427 	if (ret) {
428 		dev_err(dma_dev, "Failed to set DMA segment size\n");
429 		goto err_component_unbind;
430 	}
431 
432 	ret = drm_vblank_init(drm, MAX_CRTC);
433 	if (ret < 0)
434 		goto err_component_unbind;
435 
436 	drm_kms_helper_poll_init(drm);
437 	drm_mode_config_reset(drm);
438 
439 	return 0;
440 
441 err_component_unbind:
442 	component_unbind_all(drm->dev, drm);
443 put_mutex_dev:
444 	put_device(private->mutex_dev);
445 	return ret;
446 }
447 
448 static void mtk_drm_kms_deinit(struct drm_device *drm)
449 {
450 	drm_kms_helper_poll_fini(drm);
451 	drm_atomic_helper_shutdown(drm);
452 
453 	component_unbind_all(drm->dev, drm);
454 }
455 
456 DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
457 
458 /*
459  * We need to override this because the device used to import the memory is
460  * not dev->dev, as drm_gem_prime_import() expects.
461  */
462 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev,
463 						       struct dma_buf *dma_buf)
464 {
465 	struct mtk_drm_private *private = dev->dev_private;
466 
467 	return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
468 }
469 
470 static const struct drm_driver mtk_drm_driver = {
471 	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
472 
473 	.dumb_create = mtk_drm_gem_dumb_create,
474 
475 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
476 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
477 	.gem_prime_import = mtk_drm_gem_prime_import,
478 	.gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
479 	.gem_prime_mmap = drm_gem_prime_mmap,
480 	.fops = &mtk_drm_fops,
481 
482 	.name = DRIVER_NAME,
483 	.desc = DRIVER_DESC,
484 	.date = DRIVER_DATE,
485 	.major = DRIVER_MAJOR,
486 	.minor = DRIVER_MINOR,
487 };
488 
489 static int mtk_drm_bind(struct device *dev)
490 {
491 	struct mtk_drm_private *private = dev_get_drvdata(dev);
492 	struct drm_device *drm;
493 	int ret;
494 
495 	drm = drm_dev_alloc(&mtk_drm_driver, dev);
496 	if (IS_ERR(drm))
497 		return PTR_ERR(drm);
498 
499 	drm->dev_private = private;
500 	private->drm = drm;
501 
502 	ret = mtk_drm_kms_init(drm);
503 	if (ret < 0)
504 		goto err_free;
505 
506 	ret = drm_dev_register(drm, 0);
507 	if (ret < 0)
508 		goto err_deinit;
509 
510 	drm_fbdev_generic_setup(drm, 32);
511 
512 	return 0;
513 
514 err_deinit:
515 	mtk_drm_kms_deinit(drm);
516 err_free:
517 	drm_dev_put(drm);
518 	return ret;
519 }
520 
521 static void mtk_drm_unbind(struct device *dev)
522 {
523 	struct mtk_drm_private *private = dev_get_drvdata(dev);
524 
525 	drm_dev_unregister(private->drm);
526 	mtk_drm_kms_deinit(private->drm);
527 	drm_dev_put(private->drm);
528 	private->num_pipes = 0;
529 	private->drm = NULL;
530 }
531 
532 static const struct component_master_ops mtk_drm_ops = {
533 	.bind		= mtk_drm_bind,
534 	.unbind		= mtk_drm_unbind,
535 };
536 
537 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
538 	{ .compatible = "mediatek,mt8167-disp-aal",
539 	  .data = (void *)MTK_DISP_AAL},
540 	{ .compatible = "mediatek,mt8173-disp-aal",
541 	  .data = (void *)MTK_DISP_AAL},
542 	{ .compatible = "mediatek,mt8183-disp-aal",
543 	  .data = (void *)MTK_DISP_AAL},
544 	{ .compatible = "mediatek,mt8192-disp-aal",
545 	  .data = (void *)MTK_DISP_AAL},
546 	{ .compatible = "mediatek,mt8167-disp-ccorr",
547 	  .data = (void *)MTK_DISP_CCORR },
548 	{ .compatible = "mediatek,mt8183-disp-ccorr",
549 	  .data = (void *)MTK_DISP_CCORR },
550 	{ .compatible = "mediatek,mt8192-disp-ccorr",
551 	  .data = (void *)MTK_DISP_CCORR },
552 	{ .compatible = "mediatek,mt2701-disp-color",
553 	  .data = (void *)MTK_DISP_COLOR },
554 	{ .compatible = "mediatek,mt8167-disp-color",
555 	  .data = (void *)MTK_DISP_COLOR },
556 	{ .compatible = "mediatek,mt8173-disp-color",
557 	  .data = (void *)MTK_DISP_COLOR },
558 	{ .compatible = "mediatek,mt8167-disp-dither",
559 	  .data = (void *)MTK_DISP_DITHER },
560 	{ .compatible = "mediatek,mt8183-disp-dither",
561 	  .data = (void *)MTK_DISP_DITHER },
562 	{ .compatible = "mediatek,mt8195-disp-dsc",
563 	  .data = (void *)MTK_DISP_DSC },
564 	{ .compatible = "mediatek,mt8167-disp-gamma",
565 	  .data = (void *)MTK_DISP_GAMMA, },
566 	{ .compatible = "mediatek,mt8173-disp-gamma",
567 	  .data = (void *)MTK_DISP_GAMMA, },
568 	{ .compatible = "mediatek,mt8183-disp-gamma",
569 	  .data = (void *)MTK_DISP_GAMMA, },
570 	{ .compatible = "mediatek,mt8195-disp-merge",
571 	  .data = (void *)MTK_DISP_MERGE },
572 	{ .compatible = "mediatek,mt2701-disp-mutex",
573 	  .data = (void *)MTK_DISP_MUTEX },
574 	{ .compatible = "mediatek,mt2712-disp-mutex",
575 	  .data = (void *)MTK_DISP_MUTEX },
576 	{ .compatible = "mediatek,mt8167-disp-mutex",
577 	  .data = (void *)MTK_DISP_MUTEX },
578 	{ .compatible = "mediatek,mt8173-disp-mutex",
579 	  .data = (void *)MTK_DISP_MUTEX },
580 	{ .compatible = "mediatek,mt8183-disp-mutex",
581 	  .data = (void *)MTK_DISP_MUTEX },
582 	{ .compatible = "mediatek,mt8186-disp-mutex",
583 	  .data = (void *)MTK_DISP_MUTEX },
584 	{ .compatible = "mediatek,mt8192-disp-mutex",
585 	  .data = (void *)MTK_DISP_MUTEX },
586 	{ .compatible = "mediatek,mt8195-disp-mutex",
587 	  .data = (void *)MTK_DISP_MUTEX },
588 	{ .compatible = "mediatek,mt8173-disp-od",
589 	  .data = (void *)MTK_DISP_OD },
590 	{ .compatible = "mediatek,mt2701-disp-ovl",
591 	  .data = (void *)MTK_DISP_OVL },
592 	{ .compatible = "mediatek,mt8167-disp-ovl",
593 	  .data = (void *)MTK_DISP_OVL },
594 	{ .compatible = "mediatek,mt8173-disp-ovl",
595 	  .data = (void *)MTK_DISP_OVL },
596 	{ .compatible = "mediatek,mt8183-disp-ovl",
597 	  .data = (void *)MTK_DISP_OVL },
598 	{ .compatible = "mediatek,mt8192-disp-ovl",
599 	  .data = (void *)MTK_DISP_OVL },
600 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
601 	  .data = (void *)MTK_DISP_OVL_2L },
602 	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
603 	  .data = (void *)MTK_DISP_OVL_2L },
604 	{ .compatible = "mediatek,mt8192-disp-postmask",
605 	  .data = (void *)MTK_DISP_POSTMASK },
606 	{ .compatible = "mediatek,mt2701-disp-pwm",
607 	  .data = (void *)MTK_DISP_BLS },
608 	{ .compatible = "mediatek,mt8167-disp-pwm",
609 	  .data = (void *)MTK_DISP_PWM },
610 	{ .compatible = "mediatek,mt8173-disp-pwm",
611 	  .data = (void *)MTK_DISP_PWM },
612 	{ .compatible = "mediatek,mt2701-disp-rdma",
613 	  .data = (void *)MTK_DISP_RDMA },
614 	{ .compatible = "mediatek,mt8167-disp-rdma",
615 	  .data = (void *)MTK_DISP_RDMA },
616 	{ .compatible = "mediatek,mt8173-disp-rdma",
617 	  .data = (void *)MTK_DISP_RDMA },
618 	{ .compatible = "mediatek,mt8183-disp-rdma",
619 	  .data = (void *)MTK_DISP_RDMA },
620 	{ .compatible = "mediatek,mt8195-disp-rdma",
621 	  .data = (void *)MTK_DISP_RDMA },
622 	{ .compatible = "mediatek,mt8173-disp-ufoe",
623 	  .data = (void *)MTK_DISP_UFOE },
624 	{ .compatible = "mediatek,mt8173-disp-wdma",
625 	  .data = (void *)MTK_DISP_WDMA },
626 	{ .compatible = "mediatek,mt2701-dpi",
627 	  .data = (void *)MTK_DPI },
628 	{ .compatible = "mediatek,mt8167-dsi",
629 	  .data = (void *)MTK_DSI },
630 	{ .compatible = "mediatek,mt8173-dpi",
631 	  .data = (void *)MTK_DPI },
632 	{ .compatible = "mediatek,mt8183-dpi",
633 	  .data = (void *)MTK_DPI },
634 	{ .compatible = "mediatek,mt8192-dpi",
635 	  .data = (void *)MTK_DPI },
636 	{ .compatible = "mediatek,mt8195-dp-intf",
637 	  .data = (void *)MTK_DP_INTF },
638 	{ .compatible = "mediatek,mt2701-dsi",
639 	  .data = (void *)MTK_DSI },
640 	{ .compatible = "mediatek,mt8173-dsi",
641 	  .data = (void *)MTK_DSI },
642 	{ .compatible = "mediatek,mt8183-dsi",
643 	  .data = (void *)MTK_DSI },
644 	{ .compatible = "mediatek,mt8186-dsi",
645 	  .data = (void *)MTK_DSI },
646 	{ }
647 };
648 
649 static const struct of_device_id mtk_drm_of_ids[] = {
650 	{ .compatible = "mediatek,mt2701-mmsys",
651 	  .data = &mt2701_mmsys_match_data},
652 	{ .compatible = "mediatek,mt7623-mmsys",
653 	  .data = &mt7623_mmsys_match_data},
654 	{ .compatible = "mediatek,mt2712-mmsys",
655 	  .data = &mt2712_mmsys_match_data},
656 	{ .compatible = "mediatek,mt8167-mmsys",
657 	  .data = &mt8167_mmsys_match_data},
658 	{ .compatible = "mediatek,mt8173-mmsys",
659 	  .data = &mt8173_mmsys_match_data},
660 	{ .compatible = "mediatek,mt8183-mmsys",
661 	  .data = &mt8183_mmsys_match_data},
662 	{ .compatible = "mediatek,mt8186-mmsys",
663 	  .data = &mt8186_mmsys_match_data},
664 	{ .compatible = "mediatek,mt8192-mmsys",
665 	  .data = &mt8192_mmsys_match_data},
666 	{ .compatible = "mediatek,mt8195-mmsys",
667 	  .data = &mt8195_mmsys_match_data},
668 	{ }
669 };
670 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
671 
672 static int mtk_drm_find_match_data(struct device *dev,
673 				   const struct mtk_mmsys_match_data *match_data)
674 {
675 	int i;
676 	struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
677 	struct resource *res;
678 
679 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
680 	if (!res) {
681 		dev_err(dev, "failed to get parent resource\n");
682 		return -EINVAL;
683 	}
684 
685 	for (i = 0; i < match_data->num_drv_data; i++)
686 		if (match_data->drv_data[i]->io_start == res->start)
687 			return i;
688 
689 	return -EINVAL;
690 }
691 
692 static int mtk_drm_probe(struct platform_device *pdev)
693 {
694 	struct device *dev = &pdev->dev;
695 	struct device_node *phandle = dev->parent->of_node;
696 	const struct of_device_id *of_id;
697 	const struct mtk_mmsys_match_data *match_data;
698 	struct mtk_drm_private *private;
699 	struct device_node *node;
700 	struct component_match *match = NULL;
701 	int ret;
702 	int i;
703 
704 	private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
705 	if (!private)
706 		return -ENOMEM;
707 
708 	private->mmsys_dev = dev->parent;
709 	if (!private->mmsys_dev) {
710 		dev_err(dev, "Failed to get MMSYS device\n");
711 		return -ENODEV;
712 	}
713 
714 	of_id = of_match_node(mtk_drm_of_ids, phandle);
715 	if (!of_id)
716 		return -ENODEV;
717 
718 	match_data = of_id->data;
719 	if (match_data->num_drv_data > 1) {
720 		/* This SoC has multiple mmsys channels */
721 		ret = mtk_drm_find_match_data(dev, match_data);
722 		if (ret < 0) {
723 			dev_err(dev, "Couldn't get match driver data\n");
724 			return ret;
725 		}
726 		private->data = match_data->drv_data[ret];
727 	} else {
728 		dev_dbg(dev, "Using single mmsys channel\n");
729 		private->data = match_data->drv_data[0];
730 	}
731 
732 	/* Iterate over sibling DISP function blocks */
733 	for_each_child_of_node(phandle->parent, node) {
734 		const struct of_device_id *of_id;
735 		enum mtk_ddp_comp_type comp_type;
736 		int comp_id;
737 
738 		of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
739 		if (!of_id)
740 			continue;
741 
742 		if (!of_device_is_available(node)) {
743 			dev_dbg(dev, "Skipping disabled component %pOF\n",
744 				node);
745 			continue;
746 		}
747 
748 		comp_type = (enum mtk_ddp_comp_type)of_id->data;
749 
750 		if (comp_type == MTK_DISP_MUTEX) {
751 			private->mutex_node = of_node_get(node);
752 			continue;
753 		}
754 
755 		comp_id = mtk_ddp_comp_get_id(node, comp_type);
756 		if (comp_id < 0) {
757 			dev_warn(dev, "Skipping unknown component %pOF\n",
758 				 node);
759 			continue;
760 		}
761 
762 		private->comp_node[comp_id] = of_node_get(node);
763 
764 		/*
765 		 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
766 		 * blocks have separate component platform drivers and initialize their own
767 		 * DDP component structure. The others are initialized here.
768 		 */
769 		if (comp_type == MTK_DISP_AAL ||
770 		    comp_type == MTK_DISP_CCORR ||
771 		    comp_type == MTK_DISP_COLOR ||
772 		    comp_type == MTK_DISP_GAMMA ||
773 		    comp_type == MTK_DISP_MERGE ||
774 		    comp_type == MTK_DISP_OVL ||
775 		    comp_type == MTK_DISP_OVL_2L ||
776 		    comp_type == MTK_DISP_RDMA ||
777 		    comp_type == MTK_DP_INTF ||
778 		    comp_type == MTK_DPI ||
779 		    comp_type == MTK_DSI) {
780 			dev_info(dev, "Adding component match for %pOF\n",
781 				 node);
782 			drm_of_component_match_add(dev, &match, component_compare_of,
783 						   node);
784 		}
785 
786 		ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
787 		if (ret) {
788 			of_node_put(node);
789 			goto err_node;
790 		}
791 	}
792 
793 	if (!private->mutex_node) {
794 		dev_err(dev, "Failed to find disp-mutex node\n");
795 		ret = -ENODEV;
796 		goto err_node;
797 	}
798 
799 	pm_runtime_enable(dev);
800 
801 	platform_set_drvdata(pdev, private);
802 
803 	ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
804 	if (ret)
805 		goto err_pm;
806 
807 	return 0;
808 
809 err_pm:
810 	pm_runtime_disable(dev);
811 err_node:
812 	of_node_put(private->mutex_node);
813 	for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
814 		of_node_put(private->comp_node[i]);
815 	return ret;
816 }
817 
818 static int mtk_drm_remove(struct platform_device *pdev)
819 {
820 	struct mtk_drm_private *private = platform_get_drvdata(pdev);
821 	int i;
822 
823 	component_master_del(&pdev->dev, &mtk_drm_ops);
824 	pm_runtime_disable(&pdev->dev);
825 	of_node_put(private->mutex_node);
826 	for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
827 		of_node_put(private->comp_node[i]);
828 
829 	return 0;
830 }
831 
832 static int mtk_drm_sys_prepare(struct device *dev)
833 {
834 	struct mtk_drm_private *private = dev_get_drvdata(dev);
835 	struct drm_device *drm = private->drm;
836 	int ret;
837 
838 	ret = drm_mode_config_helper_suspend(drm);
839 
840 	return ret;
841 }
842 
843 static void mtk_drm_sys_complete(struct device *dev)
844 {
845 	struct mtk_drm_private *private = dev_get_drvdata(dev);
846 	struct drm_device *drm = private->drm;
847 	int ret;
848 
849 	ret = drm_mode_config_helper_resume(drm);
850 	if (ret)
851 		dev_err(dev, "Failed to resume\n");
852 }
853 
854 static const struct dev_pm_ops mtk_drm_pm_ops = {
855 	.prepare = mtk_drm_sys_prepare,
856 	.complete = mtk_drm_sys_complete,
857 };
858 
859 static struct platform_driver mtk_drm_platform_driver = {
860 	.probe	= mtk_drm_probe,
861 	.remove	= mtk_drm_remove,
862 	.driver	= {
863 		.name	= "mediatek-drm",
864 		.pm     = &mtk_drm_pm_ops,
865 	},
866 };
867 
868 static struct platform_driver * const mtk_drm_drivers[] = {
869 	&mtk_disp_aal_driver,
870 	&mtk_disp_ccorr_driver,
871 	&mtk_disp_color_driver,
872 	&mtk_disp_gamma_driver,
873 	&mtk_disp_merge_driver,
874 	&mtk_disp_ovl_driver,
875 	&mtk_disp_rdma_driver,
876 	&mtk_dpi_driver,
877 	&mtk_drm_platform_driver,
878 	&mtk_dsi_driver,
879 	&mtk_mdp_rdma_driver,
880 };
881 
882 static int __init mtk_drm_init(void)
883 {
884 	return platform_register_drivers(mtk_drm_drivers,
885 					 ARRAY_SIZE(mtk_drm_drivers));
886 }
887 
888 static void __exit mtk_drm_exit(void)
889 {
890 	platform_unregister_drivers(mtk_drm_drivers,
891 				    ARRAY_SIZE(mtk_drm_drivers));
892 }
893 
894 module_init(mtk_drm_init);
895 module_exit(mtk_drm_exit);
896 
897 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
898 MODULE_DESCRIPTION("Mediatek SoC DRM driver");
899 MODULE_LICENSE("GPL v2");
900