1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of_address.h> 11 #include <linux/of_platform.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_fb_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 27 #include "mtk_drm_crtc.h" 28 #include "mtk_drm_ddp_comp.h" 29 #include "mtk_drm_drv.h" 30 #include "mtk_drm_gem.h" 31 32 #define DRIVER_NAME "mediatek" 33 #define DRIVER_DESC "Mediatek SoC DRM" 34 #define DRIVER_DATE "20150513" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 38 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 39 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 40 }; 41 42 static struct drm_framebuffer * 43 mtk_drm_mode_fb_create(struct drm_device *dev, 44 struct drm_file *file, 45 const struct drm_mode_fb_cmd2 *cmd) 46 { 47 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 48 49 if (info->num_planes != 1) 50 return ERR_PTR(-EINVAL); 51 52 return drm_gem_fb_create(dev, file, cmd); 53 } 54 55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 56 .fb_create = mtk_drm_mode_fb_create, 57 .atomic_check = drm_atomic_helper_check, 58 .atomic_commit = drm_atomic_helper_commit, 59 }; 60 61 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { 62 DDP_COMPONENT_OVL0, 63 DDP_COMPONENT_RDMA0, 64 DDP_COMPONENT_COLOR0, 65 DDP_COMPONENT_BLS, 66 DDP_COMPONENT_DSI0, 67 }; 68 69 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { 70 DDP_COMPONENT_RDMA1, 71 DDP_COMPONENT_DPI0, 72 }; 73 74 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = { 75 DDP_COMPONENT_OVL0, 76 DDP_COMPONENT_RDMA0, 77 DDP_COMPONENT_COLOR0, 78 DDP_COMPONENT_BLS, 79 DDP_COMPONENT_DPI0, 80 }; 81 82 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = { 83 DDP_COMPONENT_RDMA1, 84 DDP_COMPONENT_DSI0, 85 }; 86 87 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { 88 DDP_COMPONENT_OVL0, 89 DDP_COMPONENT_COLOR0, 90 DDP_COMPONENT_AAL0, 91 DDP_COMPONENT_OD0, 92 DDP_COMPONENT_RDMA0, 93 DDP_COMPONENT_DPI0, 94 DDP_COMPONENT_PWM0, 95 }; 96 97 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 98 DDP_COMPONENT_OVL1, 99 DDP_COMPONENT_COLOR1, 100 DDP_COMPONENT_AAL1, 101 DDP_COMPONENT_OD1, 102 DDP_COMPONENT_RDMA1, 103 DDP_COMPONENT_DPI1, 104 DDP_COMPONENT_PWM1, 105 }; 106 107 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 108 DDP_COMPONENT_RDMA2, 109 DDP_COMPONENT_DSI3, 110 DDP_COMPONENT_PWM2, 111 }; 112 113 static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = { 114 DDP_COMPONENT_OVL0, 115 DDP_COMPONENT_COLOR0, 116 DDP_COMPONENT_CCORR, 117 DDP_COMPONENT_AAL0, 118 DDP_COMPONENT_GAMMA, 119 DDP_COMPONENT_DITHER, 120 DDP_COMPONENT_RDMA0, 121 DDP_COMPONENT_DSI0, 122 }; 123 124 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 125 DDP_COMPONENT_OVL0, 126 DDP_COMPONENT_COLOR0, 127 DDP_COMPONENT_AAL0, 128 DDP_COMPONENT_OD0, 129 DDP_COMPONENT_RDMA0, 130 DDP_COMPONENT_UFOE, 131 DDP_COMPONENT_DSI0, 132 DDP_COMPONENT_PWM0, 133 }; 134 135 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 136 DDP_COMPONENT_OVL1, 137 DDP_COMPONENT_COLOR1, 138 DDP_COMPONENT_GAMMA, 139 DDP_COMPONENT_RDMA1, 140 DDP_COMPONENT_DPI0, 141 }; 142 143 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { 144 DDP_COMPONENT_OVL0, 145 DDP_COMPONENT_OVL_2L0, 146 DDP_COMPONENT_RDMA0, 147 DDP_COMPONENT_COLOR0, 148 DDP_COMPONENT_CCORR, 149 DDP_COMPONENT_AAL0, 150 DDP_COMPONENT_GAMMA, 151 DDP_COMPONENT_DITHER, 152 DDP_COMPONENT_DSI0, 153 }; 154 155 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { 156 DDP_COMPONENT_OVL_2L1, 157 DDP_COMPONENT_RDMA1, 158 DDP_COMPONENT_DPI0, 159 }; 160 161 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { 162 DDP_COMPONENT_OVL0, 163 DDP_COMPONENT_OVL_2L0, 164 DDP_COMPONENT_RDMA0, 165 DDP_COMPONENT_COLOR0, 166 DDP_COMPONENT_CCORR, 167 DDP_COMPONENT_AAL0, 168 DDP_COMPONENT_GAMMA, 169 DDP_COMPONENT_POSTMASK0, 170 DDP_COMPONENT_DITHER, 171 DDP_COMPONENT_DSI0, 172 }; 173 174 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { 175 DDP_COMPONENT_OVL_2L2, 176 DDP_COMPONENT_RDMA4, 177 DDP_COMPONENT_DPI0, 178 }; 179 180 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 181 .main_path = mt2701_mtk_ddp_main, 182 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 183 .ext_path = mt2701_mtk_ddp_ext, 184 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 185 .shadow_register = true, 186 }; 187 188 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 189 .main_path = mt7623_mtk_ddp_main, 190 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 191 .ext_path = mt7623_mtk_ddp_ext, 192 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 193 .shadow_register = true, 194 }; 195 196 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 197 .main_path = mt2712_mtk_ddp_main, 198 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 199 .ext_path = mt2712_mtk_ddp_ext, 200 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 201 .third_path = mt2712_mtk_ddp_third, 202 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 203 }; 204 205 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 206 .main_path = mt8167_mtk_ddp_main, 207 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 208 }; 209 210 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 211 .main_path = mt8173_mtk_ddp_main, 212 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 213 .ext_path = mt8173_mtk_ddp_ext, 214 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 215 }; 216 217 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 218 .main_path = mt8183_mtk_ddp_main, 219 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 220 .ext_path = mt8183_mtk_ddp_ext, 221 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 222 }; 223 224 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 225 .main_path = mt8192_mtk_ddp_main, 226 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 227 .ext_path = mt8192_mtk_ddp_ext, 228 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 229 }; 230 231 static int mtk_drm_kms_init(struct drm_device *drm) 232 { 233 struct mtk_drm_private *private = drm->dev_private; 234 struct platform_device *pdev; 235 struct device_node *np; 236 struct device *dma_dev; 237 int ret; 238 239 if (!iommu_present(&platform_bus_type)) 240 return -EPROBE_DEFER; 241 242 pdev = of_find_device_by_node(private->mutex_node); 243 if (!pdev) { 244 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", 245 private->mutex_node); 246 of_node_put(private->mutex_node); 247 return -EPROBE_DEFER; 248 } 249 private->mutex_dev = &pdev->dev; 250 251 ret = drmm_mode_config_init(drm); 252 if (ret) 253 goto put_mutex_dev; 254 255 drm->mode_config.min_width = 64; 256 drm->mode_config.min_height = 64; 257 258 /* 259 * set max width and height as default value(4096x4096). 260 * this value would be used to check framebuffer size limitation 261 * at drm_mode_addfb(). 262 */ 263 drm->mode_config.max_width = 4096; 264 drm->mode_config.max_height = 4096; 265 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 266 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 267 268 ret = component_bind_all(drm->dev, drm); 269 if (ret) 270 goto put_mutex_dev; 271 272 /* 273 * We currently support two fixed data streams, each optional, 274 * and each statically assigned to a crtc: 275 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 276 */ 277 ret = mtk_drm_crtc_create(drm, private->data->main_path, 278 private->data->main_len); 279 if (ret < 0) 280 goto err_component_unbind; 281 /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */ 282 ret = mtk_drm_crtc_create(drm, private->data->ext_path, 283 private->data->ext_len); 284 if (ret < 0) 285 goto err_component_unbind; 286 287 ret = mtk_drm_crtc_create(drm, private->data->third_path, 288 private->data->third_len); 289 if (ret < 0) 290 goto err_component_unbind; 291 292 /* Use OVL device for all DMA memory allocations */ 293 np = private->comp_node[private->data->main_path[0]] ?: 294 private->comp_node[private->data->ext_path[0]]; 295 pdev = of_find_device_by_node(np); 296 if (!pdev) { 297 ret = -ENODEV; 298 dev_err(drm->dev, "Need at least one OVL device\n"); 299 goto err_component_unbind; 300 } 301 302 dma_dev = &pdev->dev; 303 private->dma_dev = dma_dev; 304 305 /* 306 * Configure the DMA segment size to make sure we get contiguous IOVA 307 * when importing PRIME buffers. 308 */ 309 ret = dma_set_max_seg_size(dma_dev, UINT_MAX); 310 if (ret) { 311 dev_err(dma_dev, "Failed to set DMA segment size\n"); 312 goto err_component_unbind; 313 } 314 315 ret = drm_vblank_init(drm, MAX_CRTC); 316 if (ret < 0) 317 goto err_component_unbind; 318 319 drm_kms_helper_poll_init(drm); 320 drm_mode_config_reset(drm); 321 322 return 0; 323 324 err_component_unbind: 325 component_unbind_all(drm->dev, drm); 326 put_mutex_dev: 327 put_device(private->mutex_dev); 328 return ret; 329 } 330 331 static void mtk_drm_kms_deinit(struct drm_device *drm) 332 { 333 drm_kms_helper_poll_fini(drm); 334 drm_atomic_helper_shutdown(drm); 335 336 component_unbind_all(drm->dev, drm); 337 } 338 339 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 340 341 /* 342 * We need to override this because the device used to import the memory is 343 * not dev->dev, as drm_gem_prime_import() expects. 344 */ 345 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev, 346 struct dma_buf *dma_buf) 347 { 348 struct mtk_drm_private *private = dev->dev_private; 349 350 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 351 } 352 353 static const struct drm_driver mtk_drm_driver = { 354 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 355 356 .dumb_create = mtk_drm_gem_dumb_create, 357 358 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 359 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 360 .gem_prime_import = mtk_drm_gem_prime_import, 361 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 362 .gem_prime_mmap = drm_gem_prime_mmap, 363 .fops = &mtk_drm_fops, 364 365 .name = DRIVER_NAME, 366 .desc = DRIVER_DESC, 367 .date = DRIVER_DATE, 368 .major = DRIVER_MAJOR, 369 .minor = DRIVER_MINOR, 370 }; 371 372 static int compare_of(struct device *dev, void *data) 373 { 374 return dev->of_node == data; 375 } 376 377 static int mtk_drm_bind(struct device *dev) 378 { 379 struct mtk_drm_private *private = dev_get_drvdata(dev); 380 struct drm_device *drm; 381 int ret; 382 383 drm = drm_dev_alloc(&mtk_drm_driver, dev); 384 if (IS_ERR(drm)) 385 return PTR_ERR(drm); 386 387 drm->dev_private = private; 388 private->drm = drm; 389 390 ret = mtk_drm_kms_init(drm); 391 if (ret < 0) 392 goto err_free; 393 394 ret = drm_dev_register(drm, 0); 395 if (ret < 0) 396 goto err_deinit; 397 398 drm_fbdev_generic_setup(drm, 32); 399 400 return 0; 401 402 err_deinit: 403 mtk_drm_kms_deinit(drm); 404 err_free: 405 drm_dev_put(drm); 406 return ret; 407 } 408 409 static void mtk_drm_unbind(struct device *dev) 410 { 411 struct mtk_drm_private *private = dev_get_drvdata(dev); 412 413 drm_dev_unregister(private->drm); 414 mtk_drm_kms_deinit(private->drm); 415 drm_dev_put(private->drm); 416 private->num_pipes = 0; 417 private->drm = NULL; 418 } 419 420 static const struct component_master_ops mtk_drm_ops = { 421 .bind = mtk_drm_bind, 422 .unbind = mtk_drm_unbind, 423 }; 424 425 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 426 { .compatible = "mediatek,mt8167-disp-aal", 427 .data = (void *)MTK_DISP_AAL}, 428 { .compatible = "mediatek,mt8173-disp-aal", 429 .data = (void *)MTK_DISP_AAL}, 430 { .compatible = "mediatek,mt8183-disp-aal", 431 .data = (void *)MTK_DISP_AAL}, 432 { .compatible = "mediatek,mt8192-disp-aal", 433 .data = (void *)MTK_DISP_AAL}, 434 { .compatible = "mediatek,mt8167-disp-ccorr", 435 .data = (void *)MTK_DISP_CCORR }, 436 { .compatible = "mediatek,mt8183-disp-ccorr", 437 .data = (void *)MTK_DISP_CCORR }, 438 { .compatible = "mediatek,mt8192-disp-ccorr", 439 .data = (void *)MTK_DISP_CCORR }, 440 { .compatible = "mediatek,mt2701-disp-color", 441 .data = (void *)MTK_DISP_COLOR }, 442 { .compatible = "mediatek,mt8167-disp-color", 443 .data = (void *)MTK_DISP_COLOR }, 444 { .compatible = "mediatek,mt8173-disp-color", 445 .data = (void *)MTK_DISP_COLOR }, 446 { .compatible = "mediatek,mt8167-disp-dither", 447 .data = (void *)MTK_DISP_DITHER }, 448 { .compatible = "mediatek,mt8183-disp-dither", 449 .data = (void *)MTK_DISP_DITHER }, 450 { .compatible = "mediatek,mt8167-disp-gamma", 451 .data = (void *)MTK_DISP_GAMMA, }, 452 { .compatible = "mediatek,mt8173-disp-gamma", 453 .data = (void *)MTK_DISP_GAMMA, }, 454 { .compatible = "mediatek,mt8183-disp-gamma", 455 .data = (void *)MTK_DISP_GAMMA, }, 456 { .compatible = "mediatek,mt2701-disp-mutex", 457 .data = (void *)MTK_DISP_MUTEX }, 458 { .compatible = "mediatek,mt2712-disp-mutex", 459 .data = (void *)MTK_DISP_MUTEX }, 460 { .compatible = "mediatek,mt8167-disp-mutex", 461 .data = (void *)MTK_DISP_MUTEX }, 462 { .compatible = "mediatek,mt8173-disp-mutex", 463 .data = (void *)MTK_DISP_MUTEX }, 464 { .compatible = "mediatek,mt8183-disp-mutex", 465 .data = (void *)MTK_DISP_MUTEX }, 466 { .compatible = "mediatek,mt8192-disp-mutex", 467 .data = (void *)MTK_DISP_MUTEX }, 468 { .compatible = "mediatek,mt8173-disp-od", 469 .data = (void *)MTK_DISP_OD }, 470 { .compatible = "mediatek,mt2701-disp-ovl", 471 .data = (void *)MTK_DISP_OVL }, 472 { .compatible = "mediatek,mt8167-disp-ovl", 473 .data = (void *)MTK_DISP_OVL }, 474 { .compatible = "mediatek,mt8173-disp-ovl", 475 .data = (void *)MTK_DISP_OVL }, 476 { .compatible = "mediatek,mt8183-disp-ovl", 477 .data = (void *)MTK_DISP_OVL }, 478 { .compatible = "mediatek,mt8192-disp-ovl", 479 .data = (void *)MTK_DISP_OVL }, 480 { .compatible = "mediatek,mt8183-disp-ovl-2l", 481 .data = (void *)MTK_DISP_OVL_2L }, 482 { .compatible = "mediatek,mt8192-disp-ovl-2l", 483 .data = (void *)MTK_DISP_OVL_2L }, 484 { .compatible = "mediatek,mt8192-disp-postmask", 485 .data = (void *)MTK_DISP_POSTMASK }, 486 { .compatible = "mediatek,mt2701-disp-pwm", 487 .data = (void *)MTK_DISP_BLS }, 488 { .compatible = "mediatek,mt8167-disp-pwm", 489 .data = (void *)MTK_DISP_PWM }, 490 { .compatible = "mediatek,mt8173-disp-pwm", 491 .data = (void *)MTK_DISP_PWM }, 492 { .compatible = "mediatek,mt2701-disp-rdma", 493 .data = (void *)MTK_DISP_RDMA }, 494 { .compatible = "mediatek,mt8167-disp-rdma", 495 .data = (void *)MTK_DISP_RDMA }, 496 { .compatible = "mediatek,mt8173-disp-rdma", 497 .data = (void *)MTK_DISP_RDMA }, 498 { .compatible = "mediatek,mt8183-disp-rdma", 499 .data = (void *)MTK_DISP_RDMA }, 500 { .compatible = "mediatek,mt8192-disp-rdma", 501 .data = (void *)MTK_DISP_RDMA }, 502 { .compatible = "mediatek,mt8173-disp-ufoe", 503 .data = (void *)MTK_DISP_UFOE }, 504 { .compatible = "mediatek,mt8173-disp-wdma", 505 .data = (void *)MTK_DISP_WDMA }, 506 { .compatible = "mediatek,mt2701-dpi", 507 .data = (void *)MTK_DPI }, 508 { .compatible = "mediatek,mt8167-dsi", 509 .data = (void *)MTK_DSI }, 510 { .compatible = "mediatek,mt8173-dpi", 511 .data = (void *)MTK_DPI }, 512 { .compatible = "mediatek,mt8183-dpi", 513 .data = (void *)MTK_DPI }, 514 { .compatible = "mediatek,mt2701-dsi", 515 .data = (void *)MTK_DSI }, 516 { .compatible = "mediatek,mt8173-dsi", 517 .data = (void *)MTK_DSI }, 518 { .compatible = "mediatek,mt8183-dsi", 519 .data = (void *)MTK_DSI }, 520 { } 521 }; 522 523 static const struct of_device_id mtk_drm_of_ids[] = { 524 { .compatible = "mediatek,mt2701-mmsys", 525 .data = &mt2701_mmsys_driver_data}, 526 { .compatible = "mediatek,mt7623-mmsys", 527 .data = &mt7623_mmsys_driver_data}, 528 { .compatible = "mediatek,mt2712-mmsys", 529 .data = &mt2712_mmsys_driver_data}, 530 { .compatible = "mediatek,mt8167-mmsys", 531 .data = &mt8167_mmsys_driver_data}, 532 { .compatible = "mediatek,mt8173-mmsys", 533 .data = &mt8173_mmsys_driver_data}, 534 { .compatible = "mediatek,mt8183-mmsys", 535 .data = &mt8183_mmsys_driver_data}, 536 { .compatible = "mediatek,mt8192-mmsys", 537 .data = &mt8192_mmsys_driver_data}, 538 { } 539 }; 540 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 541 542 static int mtk_drm_probe(struct platform_device *pdev) 543 { 544 struct device *dev = &pdev->dev; 545 struct device_node *phandle = dev->parent->of_node; 546 const struct of_device_id *of_id; 547 struct mtk_drm_private *private; 548 struct device_node *node; 549 struct component_match *match = NULL; 550 int ret; 551 int i; 552 553 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 554 if (!private) 555 return -ENOMEM; 556 557 private->mmsys_dev = dev->parent; 558 if (!private->mmsys_dev) { 559 dev_err(dev, "Failed to get MMSYS device\n"); 560 return -ENODEV; 561 } 562 563 of_id = of_match_node(mtk_drm_of_ids, phandle); 564 if (!of_id) 565 return -ENODEV; 566 567 private->data = of_id->data; 568 569 /* Iterate over sibling DISP function blocks */ 570 for_each_child_of_node(phandle->parent, node) { 571 const struct of_device_id *of_id; 572 enum mtk_ddp_comp_type comp_type; 573 int comp_id; 574 575 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 576 if (!of_id) 577 continue; 578 579 if (!of_device_is_available(node)) { 580 dev_dbg(dev, "Skipping disabled component %pOF\n", 581 node); 582 continue; 583 } 584 585 comp_type = (enum mtk_ddp_comp_type)of_id->data; 586 587 if (comp_type == MTK_DISP_MUTEX) { 588 private->mutex_node = of_node_get(node); 589 continue; 590 } 591 592 comp_id = mtk_ddp_comp_get_id(node, comp_type); 593 if (comp_id < 0) { 594 dev_warn(dev, "Skipping unknown component %pOF\n", 595 node); 596 continue; 597 } 598 599 private->comp_node[comp_id] = of_node_get(node); 600 601 /* 602 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI 603 * blocks have separate component platform drivers and initialize their own 604 * DDP component structure. The others are initialized here. 605 */ 606 if (comp_type == MTK_DISP_AAL || 607 comp_type == MTK_DISP_CCORR || 608 comp_type == MTK_DISP_COLOR || 609 comp_type == MTK_DISP_GAMMA || 610 comp_type == MTK_DISP_OVL || 611 comp_type == MTK_DISP_OVL_2L || 612 comp_type == MTK_DISP_RDMA || 613 comp_type == MTK_DPI || 614 comp_type == MTK_DSI) { 615 dev_info(dev, "Adding component match for %pOF\n", 616 node); 617 drm_of_component_match_add(dev, &match, compare_of, 618 node); 619 } 620 621 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 622 if (ret) { 623 of_node_put(node); 624 goto err_node; 625 } 626 } 627 628 if (!private->mutex_node) { 629 dev_err(dev, "Failed to find disp-mutex node\n"); 630 ret = -ENODEV; 631 goto err_node; 632 } 633 634 pm_runtime_enable(dev); 635 636 platform_set_drvdata(pdev, private); 637 638 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 639 if (ret) 640 goto err_pm; 641 642 return 0; 643 644 err_pm: 645 pm_runtime_disable(dev); 646 err_node: 647 of_node_put(private->mutex_node); 648 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 649 of_node_put(private->comp_node[i]); 650 return ret; 651 } 652 653 static int mtk_drm_remove(struct platform_device *pdev) 654 { 655 struct mtk_drm_private *private = platform_get_drvdata(pdev); 656 int i; 657 658 component_master_del(&pdev->dev, &mtk_drm_ops); 659 pm_runtime_disable(&pdev->dev); 660 of_node_put(private->mutex_node); 661 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 662 of_node_put(private->comp_node[i]); 663 664 return 0; 665 } 666 667 #ifdef CONFIG_PM_SLEEP 668 static int mtk_drm_sys_suspend(struct device *dev) 669 { 670 struct mtk_drm_private *private = dev_get_drvdata(dev); 671 struct drm_device *drm = private->drm; 672 int ret; 673 674 ret = drm_mode_config_helper_suspend(drm); 675 676 return ret; 677 } 678 679 static int mtk_drm_sys_resume(struct device *dev) 680 { 681 struct mtk_drm_private *private = dev_get_drvdata(dev); 682 struct drm_device *drm = private->drm; 683 int ret; 684 685 ret = drm_mode_config_helper_resume(drm); 686 687 return ret; 688 } 689 #endif 690 691 static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, 692 mtk_drm_sys_resume); 693 694 static struct platform_driver mtk_drm_platform_driver = { 695 .probe = mtk_drm_probe, 696 .remove = mtk_drm_remove, 697 .driver = { 698 .name = "mediatek-drm", 699 .pm = &mtk_drm_pm_ops, 700 }, 701 }; 702 703 static struct platform_driver * const mtk_drm_drivers[] = { 704 &mtk_disp_aal_driver, 705 &mtk_disp_ccorr_driver, 706 &mtk_disp_color_driver, 707 &mtk_disp_gamma_driver, 708 &mtk_disp_ovl_driver, 709 &mtk_disp_rdma_driver, 710 &mtk_dpi_driver, 711 &mtk_drm_platform_driver, 712 &mtk_dsi_driver, 713 }; 714 715 static int __init mtk_drm_init(void) 716 { 717 return platform_register_drivers(mtk_drm_drivers, 718 ARRAY_SIZE(mtk_drm_drivers)); 719 } 720 721 static void __exit mtk_drm_exit(void) 722 { 723 platform_unregister_drivers(mtk_drm_drivers, 724 ARRAY_SIZE(mtk_drm_drivers)); 725 } 726 727 module_init(mtk_drm_init); 728 module_exit(mtk_drm_exit); 729 730 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 731 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 732 MODULE_LICENSE("GPL v2"); 733