1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/dma-mapping.h> 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fbdev_generic.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_ioctl.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 28 #include "mtk_drm_crtc.h" 29 #include "mtk_drm_ddp_comp.h" 30 #include "mtk_drm_drv.h" 31 #include "mtk_drm_gem.h" 32 33 #define DRIVER_NAME "mediatek" 34 #define DRIVER_DESC "Mediatek SoC DRM" 35 #define DRIVER_DATE "20150513" 36 #define DRIVER_MAJOR 1 37 #define DRIVER_MINOR 0 38 39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 41 }; 42 43 static struct drm_framebuffer * 44 mtk_drm_mode_fb_create(struct drm_device *dev, 45 struct drm_file *file, 46 const struct drm_mode_fb_cmd2 *cmd) 47 { 48 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 49 50 if (info->num_planes != 1) 51 return ERR_PTR(-EINVAL); 52 53 return drm_gem_fb_create(dev, file, cmd); 54 } 55 56 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 57 .fb_create = mtk_drm_mode_fb_create, 58 .atomic_check = drm_atomic_helper_check, 59 .atomic_commit = drm_atomic_helper_commit, 60 }; 61 62 static const unsigned int mt2701_mtk_ddp_main[] = { 63 DDP_COMPONENT_OVL0, 64 DDP_COMPONENT_RDMA0, 65 DDP_COMPONENT_COLOR0, 66 DDP_COMPONENT_BLS, 67 DDP_COMPONENT_DSI0, 68 }; 69 70 static const unsigned int mt2701_mtk_ddp_ext[] = { 71 DDP_COMPONENT_RDMA1, 72 DDP_COMPONENT_DPI0, 73 }; 74 75 static const unsigned int mt7623_mtk_ddp_main[] = { 76 DDP_COMPONENT_OVL0, 77 DDP_COMPONENT_RDMA0, 78 DDP_COMPONENT_COLOR0, 79 DDP_COMPONENT_BLS, 80 DDP_COMPONENT_DPI0, 81 }; 82 83 static const unsigned int mt7623_mtk_ddp_ext[] = { 84 DDP_COMPONENT_RDMA1, 85 DDP_COMPONENT_DSI0, 86 }; 87 88 static const unsigned int mt2712_mtk_ddp_main[] = { 89 DDP_COMPONENT_OVL0, 90 DDP_COMPONENT_COLOR0, 91 DDP_COMPONENT_AAL0, 92 DDP_COMPONENT_OD0, 93 DDP_COMPONENT_RDMA0, 94 DDP_COMPONENT_DPI0, 95 DDP_COMPONENT_PWM0, 96 }; 97 98 static const unsigned int mt2712_mtk_ddp_ext[] = { 99 DDP_COMPONENT_OVL1, 100 DDP_COMPONENT_COLOR1, 101 DDP_COMPONENT_AAL1, 102 DDP_COMPONENT_OD1, 103 DDP_COMPONENT_RDMA1, 104 DDP_COMPONENT_DPI1, 105 DDP_COMPONENT_PWM1, 106 }; 107 108 static const unsigned int mt2712_mtk_ddp_third[] = { 109 DDP_COMPONENT_RDMA2, 110 DDP_COMPONENT_DSI3, 111 DDP_COMPONENT_PWM2, 112 }; 113 114 static unsigned int mt8167_mtk_ddp_main[] = { 115 DDP_COMPONENT_OVL0, 116 DDP_COMPONENT_COLOR0, 117 DDP_COMPONENT_CCORR, 118 DDP_COMPONENT_AAL0, 119 DDP_COMPONENT_GAMMA, 120 DDP_COMPONENT_DITHER0, 121 DDP_COMPONENT_RDMA0, 122 DDP_COMPONENT_DSI0, 123 }; 124 125 static const unsigned int mt8173_mtk_ddp_main[] = { 126 DDP_COMPONENT_OVL0, 127 DDP_COMPONENT_COLOR0, 128 DDP_COMPONENT_AAL0, 129 DDP_COMPONENT_OD0, 130 DDP_COMPONENT_RDMA0, 131 DDP_COMPONENT_UFOE, 132 DDP_COMPONENT_DSI0, 133 DDP_COMPONENT_PWM0, 134 }; 135 136 static const unsigned int mt8173_mtk_ddp_ext[] = { 137 DDP_COMPONENT_OVL1, 138 DDP_COMPONENT_COLOR1, 139 DDP_COMPONENT_GAMMA, 140 DDP_COMPONENT_RDMA1, 141 DDP_COMPONENT_DPI0, 142 }; 143 144 static const unsigned int mt8183_mtk_ddp_main[] = { 145 DDP_COMPONENT_OVL0, 146 DDP_COMPONENT_OVL_2L0, 147 DDP_COMPONENT_RDMA0, 148 DDP_COMPONENT_COLOR0, 149 DDP_COMPONENT_CCORR, 150 DDP_COMPONENT_AAL0, 151 DDP_COMPONENT_GAMMA, 152 DDP_COMPONENT_DITHER0, 153 DDP_COMPONENT_DSI0, 154 }; 155 156 static const unsigned int mt8183_mtk_ddp_ext[] = { 157 DDP_COMPONENT_OVL_2L1, 158 DDP_COMPONENT_RDMA1, 159 DDP_COMPONENT_DPI0, 160 }; 161 162 static const unsigned int mt8186_mtk_ddp_main[] = { 163 DDP_COMPONENT_OVL0, 164 DDP_COMPONENT_RDMA0, 165 DDP_COMPONENT_COLOR0, 166 DDP_COMPONENT_CCORR, 167 DDP_COMPONENT_AAL0, 168 DDP_COMPONENT_GAMMA, 169 DDP_COMPONENT_POSTMASK0, 170 DDP_COMPONENT_DITHER0, 171 DDP_COMPONENT_DSI0, 172 }; 173 174 static const unsigned int mt8186_mtk_ddp_ext[] = { 175 DDP_COMPONENT_OVL_2L0, 176 DDP_COMPONENT_RDMA1, 177 DDP_COMPONENT_DPI0, 178 }; 179 180 static const unsigned int mt8188_mtk_ddp_main[] = { 181 DDP_COMPONENT_OVL0, 182 DDP_COMPONENT_RDMA0, 183 DDP_COMPONENT_COLOR0, 184 DDP_COMPONENT_CCORR, 185 DDP_COMPONENT_AAL0, 186 DDP_COMPONENT_GAMMA, 187 DDP_COMPONENT_POSTMASK0, 188 DDP_COMPONENT_DITHER0, 189 DDP_COMPONENT_DP_INTF0, 190 }; 191 192 static const unsigned int mt8192_mtk_ddp_main[] = { 193 DDP_COMPONENT_OVL0, 194 DDP_COMPONENT_OVL_2L0, 195 DDP_COMPONENT_RDMA0, 196 DDP_COMPONENT_COLOR0, 197 DDP_COMPONENT_CCORR, 198 DDP_COMPONENT_AAL0, 199 DDP_COMPONENT_GAMMA, 200 DDP_COMPONENT_POSTMASK0, 201 DDP_COMPONENT_DITHER0, 202 DDP_COMPONENT_DSI0, 203 }; 204 205 static const unsigned int mt8192_mtk_ddp_ext[] = { 206 DDP_COMPONENT_OVL_2L2, 207 DDP_COMPONENT_RDMA4, 208 DDP_COMPONENT_DPI0, 209 }; 210 211 static const unsigned int mt8195_mtk_ddp_main[] = { 212 DDP_COMPONENT_OVL0, 213 DDP_COMPONENT_RDMA0, 214 DDP_COMPONENT_COLOR0, 215 DDP_COMPONENT_CCORR, 216 DDP_COMPONENT_AAL0, 217 DDP_COMPONENT_GAMMA, 218 DDP_COMPONENT_DITHER0, 219 DDP_COMPONENT_DSC0, 220 DDP_COMPONENT_MERGE0, 221 DDP_COMPONENT_DP_INTF0, 222 }; 223 224 static const unsigned int mt8195_mtk_ddp_ext[] = { 225 DDP_COMPONENT_DRM_OVL_ADAPTOR, 226 DDP_COMPONENT_MERGE5, 227 DDP_COMPONENT_DP_INTF1, 228 }; 229 230 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 231 .main_path = mt2701_mtk_ddp_main, 232 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 233 .ext_path = mt2701_mtk_ddp_ext, 234 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 235 .shadow_register = true, 236 .mmsys_dev_num = 1, 237 }; 238 239 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 240 .main_path = mt7623_mtk_ddp_main, 241 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 242 .ext_path = mt7623_mtk_ddp_ext, 243 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 244 .shadow_register = true, 245 .mmsys_dev_num = 1, 246 }; 247 248 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 249 .main_path = mt2712_mtk_ddp_main, 250 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 251 .ext_path = mt2712_mtk_ddp_ext, 252 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 253 .third_path = mt2712_mtk_ddp_third, 254 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 255 .mmsys_dev_num = 1, 256 }; 257 258 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 259 .main_path = mt8167_mtk_ddp_main, 260 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 261 .mmsys_dev_num = 1, 262 }; 263 264 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 265 .main_path = mt8173_mtk_ddp_main, 266 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 267 .ext_path = mt8173_mtk_ddp_ext, 268 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 269 .mmsys_dev_num = 1, 270 }; 271 272 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 273 .main_path = mt8183_mtk_ddp_main, 274 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 275 .ext_path = mt8183_mtk_ddp_ext, 276 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 277 .mmsys_dev_num = 1, 278 }; 279 280 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 281 .main_path = mt8186_mtk_ddp_main, 282 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 283 .ext_path = mt8186_mtk_ddp_ext, 284 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 285 .mmsys_dev_num = 1, 286 }; 287 288 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 289 .main_path = mt8188_mtk_ddp_main, 290 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 291 .mmsys_dev_num = 1, 292 }; 293 294 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 295 .main_path = mt8192_mtk_ddp_main, 296 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 297 .ext_path = mt8192_mtk_ddp_ext, 298 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 299 .mmsys_dev_num = 1, 300 }; 301 302 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 303 .main_path = mt8195_mtk_ddp_main, 304 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 305 .mmsys_dev_num = 2, 306 }; 307 308 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 309 .ext_path = mt8195_mtk_ddp_ext, 310 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 311 .mmsys_id = 1, 312 .mmsys_dev_num = 2, 313 }; 314 315 static const struct of_device_id mtk_drm_of_ids[] = { 316 { .compatible = "mediatek,mt2701-mmsys", 317 .data = &mt2701_mmsys_driver_data}, 318 { .compatible = "mediatek,mt7623-mmsys", 319 .data = &mt7623_mmsys_driver_data}, 320 { .compatible = "mediatek,mt2712-mmsys", 321 .data = &mt2712_mmsys_driver_data}, 322 { .compatible = "mediatek,mt8167-mmsys", 323 .data = &mt8167_mmsys_driver_data}, 324 { .compatible = "mediatek,mt8173-mmsys", 325 .data = &mt8173_mmsys_driver_data}, 326 { .compatible = "mediatek,mt8183-mmsys", 327 .data = &mt8183_mmsys_driver_data}, 328 { .compatible = "mediatek,mt8186-mmsys", 329 .data = &mt8186_mmsys_driver_data}, 330 { .compatible = "mediatek,mt8188-vdosys0", 331 .data = &mt8188_vdosys0_driver_data}, 332 { .compatible = "mediatek,mt8192-mmsys", 333 .data = &mt8192_mmsys_driver_data}, 334 { .compatible = "mediatek,mt8195-mmsys", 335 .data = &mt8195_vdosys0_driver_data}, 336 { .compatible = "mediatek,mt8195-vdosys0", 337 .data = &mt8195_vdosys0_driver_data}, 338 { .compatible = "mediatek,mt8195-vdosys1", 339 .data = &mt8195_vdosys1_driver_data}, 340 { } 341 }; 342 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 343 344 static int mtk_drm_match(struct device *dev, void *data) 345 { 346 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 347 return true; 348 return false; 349 } 350 351 static bool mtk_drm_get_all_drm_priv(struct device *dev) 352 { 353 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 354 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 355 struct device_node *phandle = dev->parent->of_node; 356 const struct of_device_id *of_id; 357 struct device_node *node; 358 struct device *drm_dev; 359 unsigned int cnt = 0; 360 int i, j; 361 362 for_each_child_of_node(phandle->parent, node) { 363 struct platform_device *pdev; 364 365 of_id = of_match_node(mtk_drm_of_ids, node); 366 if (!of_id) 367 continue; 368 369 pdev = of_find_device_by_node(node); 370 if (!pdev) 371 continue; 372 373 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 374 if (!drm_dev || !dev_get_drvdata(drm_dev)) 375 continue; 376 377 all_drm_priv[cnt] = dev_get_drvdata(drm_dev); 378 if (all_drm_priv[cnt] && all_drm_priv[cnt]->mtk_drm_bound) 379 cnt++; 380 381 if (cnt == MAX_CRTC) 382 break; 383 } 384 385 if (drm_priv->data->mmsys_dev_num == cnt) { 386 for (i = 0; i < cnt; i++) 387 for (j = 0; j < cnt; j++) 388 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 389 390 return true; 391 } 392 393 return false; 394 } 395 396 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 397 { 398 const struct mtk_mmsys_driver_data *drv_data = private->data; 399 int i; 400 401 if (drv_data->main_path) 402 for (i = 0; i < drv_data->main_len; i++) 403 if (drv_data->main_path[i] == comp_id) 404 return true; 405 406 if (drv_data->ext_path) 407 for (i = 0; i < drv_data->ext_len; i++) 408 if (drv_data->ext_path[i] == comp_id) 409 return true; 410 411 if (drv_data->third_path) 412 for (i = 0; i < drv_data->third_len; i++) 413 if (drv_data->third_path[i] == comp_id) 414 return true; 415 416 return false; 417 } 418 419 static int mtk_drm_kms_init(struct drm_device *drm) 420 { 421 struct mtk_drm_private *private = drm->dev_private; 422 struct mtk_drm_private *priv_n; 423 struct device *dma_dev = NULL; 424 int ret, i, j; 425 426 if (drm_firmware_drivers_only()) 427 return -ENODEV; 428 429 ret = drmm_mode_config_init(drm); 430 if (ret) 431 goto put_mutex_dev; 432 433 drm->mode_config.min_width = 64; 434 drm->mode_config.min_height = 64; 435 436 /* 437 * set max width and height as default value(4096x4096). 438 * this value would be used to check framebuffer size limitation 439 * at drm_mode_addfb(). 440 */ 441 drm->mode_config.max_width = 4096; 442 drm->mode_config.max_height = 4096; 443 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 444 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 445 446 for (i = 0; i < private->data->mmsys_dev_num; i++) { 447 drm->dev_private = private->all_drm_private[i]; 448 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 449 if (ret) 450 goto put_mutex_dev; 451 } 452 453 /* 454 * Ensure internal panels are at the top of the connector list before 455 * crtc creation. 456 */ 457 drm_helper_move_panel_connectors_to_head(drm); 458 459 /* 460 * 1. We currently support two fixed data streams, each optional, 461 * and each statically assigned to a crtc: 462 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 463 * 2. For multi mmsys architecture, crtc path data are located in 464 * different drm private data structures. Loop through crtc index to 465 * create crtc from the main path and then ext_path and finally the 466 * third path. 467 */ 468 for (i = 0; i < MAX_CRTC; i++) { 469 for (j = 0; j < private->data->mmsys_dev_num; j++) { 470 priv_n = private->all_drm_private[j]; 471 472 if (i == 0 && priv_n->data->main_len) { 473 ret = mtk_drm_crtc_create(drm, priv_n->data->main_path, 474 priv_n->data->main_len, j); 475 if (ret) 476 goto err_component_unbind; 477 478 continue; 479 } else if (i == 1 && priv_n->data->ext_len) { 480 ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path, 481 priv_n->data->ext_len, j); 482 if (ret) 483 goto err_component_unbind; 484 485 continue; 486 } else if (i == 2 && priv_n->data->third_len) { 487 ret = mtk_drm_crtc_create(drm, priv_n->data->third_path, 488 priv_n->data->third_len, j); 489 if (ret) 490 goto err_component_unbind; 491 492 continue; 493 } 494 } 495 } 496 497 /* Use OVL device for all DMA memory allocations */ 498 dma_dev = mtk_drm_crtc_dma_dev_get(drm_crtc_from_index(drm, 0)); 499 if (!dma_dev) { 500 ret = -ENODEV; 501 dev_err(drm->dev, "Need at least one OVL device\n"); 502 goto err_component_unbind; 503 } 504 505 for (i = 0; i < private->data->mmsys_dev_num; i++) 506 private->all_drm_private[i]->dma_dev = dma_dev; 507 508 /* 509 * Configure the DMA segment size to make sure we get contiguous IOVA 510 * when importing PRIME buffers. 511 */ 512 ret = dma_set_max_seg_size(dma_dev, UINT_MAX); 513 if (ret) { 514 dev_err(dma_dev, "Failed to set DMA segment size\n"); 515 goto err_component_unbind; 516 } 517 518 ret = drm_vblank_init(drm, MAX_CRTC); 519 if (ret < 0) 520 goto err_component_unbind; 521 522 drm_kms_helper_poll_init(drm); 523 drm_mode_config_reset(drm); 524 525 return 0; 526 527 err_component_unbind: 528 for (i = 0; i < private->data->mmsys_dev_num; i++) 529 component_unbind_all(private->all_drm_private[i]->dev, drm); 530 put_mutex_dev: 531 for (i = 0; i < private->data->mmsys_dev_num; i++) 532 put_device(private->all_drm_private[i]->mutex_dev); 533 534 return ret; 535 } 536 537 static void mtk_drm_kms_deinit(struct drm_device *drm) 538 { 539 drm_kms_helper_poll_fini(drm); 540 drm_atomic_helper_shutdown(drm); 541 542 component_unbind_all(drm->dev, drm); 543 } 544 545 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 546 547 /* 548 * We need to override this because the device used to import the memory is 549 * not dev->dev, as drm_gem_prime_import() expects. 550 */ 551 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev, 552 struct dma_buf *dma_buf) 553 { 554 struct mtk_drm_private *private = dev->dev_private; 555 556 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 557 } 558 559 static const struct drm_driver mtk_drm_driver = { 560 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 561 562 .dumb_create = mtk_drm_gem_dumb_create, 563 564 .gem_prime_import = mtk_drm_gem_prime_import, 565 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 566 .fops = &mtk_drm_fops, 567 568 .name = DRIVER_NAME, 569 .desc = DRIVER_DESC, 570 .date = DRIVER_DATE, 571 .major = DRIVER_MAJOR, 572 .minor = DRIVER_MINOR, 573 }; 574 575 static int compare_dev(struct device *dev, void *data) 576 { 577 return dev == (struct device *)data; 578 } 579 580 static int mtk_drm_bind(struct device *dev) 581 { 582 struct mtk_drm_private *private = dev_get_drvdata(dev); 583 struct platform_device *pdev; 584 struct drm_device *drm; 585 int ret, i; 586 587 if (!iommu_present(&platform_bus_type)) 588 return -EPROBE_DEFER; 589 590 pdev = of_find_device_by_node(private->mutex_node); 591 if (!pdev) { 592 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 593 private->mutex_node); 594 of_node_put(private->mutex_node); 595 return -EPROBE_DEFER; 596 } 597 598 private->mutex_dev = &pdev->dev; 599 private->mtk_drm_bound = true; 600 private->dev = dev; 601 602 if (!mtk_drm_get_all_drm_priv(dev)) 603 return 0; 604 605 drm = drm_dev_alloc(&mtk_drm_driver, dev); 606 if (IS_ERR(drm)) 607 return PTR_ERR(drm); 608 609 private->drm_master = true; 610 drm->dev_private = private; 611 for (i = 0; i < private->data->mmsys_dev_num; i++) 612 private->all_drm_private[i]->drm = drm; 613 614 ret = mtk_drm_kms_init(drm); 615 if (ret < 0) 616 goto err_free; 617 618 ret = drm_dev_register(drm, 0); 619 if (ret < 0) 620 goto err_deinit; 621 622 drm_fbdev_generic_setup(drm, 32); 623 624 return 0; 625 626 err_deinit: 627 mtk_drm_kms_deinit(drm); 628 err_free: 629 private->drm = NULL; 630 drm_dev_put(drm); 631 return ret; 632 } 633 634 static void mtk_drm_unbind(struct device *dev) 635 { 636 struct mtk_drm_private *private = dev_get_drvdata(dev); 637 638 /* for multi mmsys dev, unregister drm dev in mmsys master */ 639 if (private->drm_master) { 640 drm_dev_unregister(private->drm); 641 mtk_drm_kms_deinit(private->drm); 642 drm_dev_put(private->drm); 643 } 644 private->mtk_drm_bound = false; 645 private->drm_master = false; 646 private->drm = NULL; 647 } 648 649 static const struct component_master_ops mtk_drm_ops = { 650 .bind = mtk_drm_bind, 651 .unbind = mtk_drm_unbind, 652 }; 653 654 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 655 { .compatible = "mediatek,mt8167-disp-aal", 656 .data = (void *)MTK_DISP_AAL}, 657 { .compatible = "mediatek,mt8173-disp-aal", 658 .data = (void *)MTK_DISP_AAL}, 659 { .compatible = "mediatek,mt8183-disp-aal", 660 .data = (void *)MTK_DISP_AAL}, 661 { .compatible = "mediatek,mt8192-disp-aal", 662 .data = (void *)MTK_DISP_AAL}, 663 { .compatible = "mediatek,mt8167-disp-ccorr", 664 .data = (void *)MTK_DISP_CCORR }, 665 { .compatible = "mediatek,mt8183-disp-ccorr", 666 .data = (void *)MTK_DISP_CCORR }, 667 { .compatible = "mediatek,mt8192-disp-ccorr", 668 .data = (void *)MTK_DISP_CCORR }, 669 { .compatible = "mediatek,mt2701-disp-color", 670 .data = (void *)MTK_DISP_COLOR }, 671 { .compatible = "mediatek,mt8167-disp-color", 672 .data = (void *)MTK_DISP_COLOR }, 673 { .compatible = "mediatek,mt8173-disp-color", 674 .data = (void *)MTK_DISP_COLOR }, 675 { .compatible = "mediatek,mt8167-disp-dither", 676 .data = (void *)MTK_DISP_DITHER }, 677 { .compatible = "mediatek,mt8183-disp-dither", 678 .data = (void *)MTK_DISP_DITHER }, 679 { .compatible = "mediatek,mt8195-disp-dsc", 680 .data = (void *)MTK_DISP_DSC }, 681 { .compatible = "mediatek,mt8167-disp-gamma", 682 .data = (void *)MTK_DISP_GAMMA, }, 683 { .compatible = "mediatek,mt8173-disp-gamma", 684 .data = (void *)MTK_DISP_GAMMA, }, 685 { .compatible = "mediatek,mt8183-disp-gamma", 686 .data = (void *)MTK_DISP_GAMMA, }, 687 { .compatible = "mediatek,mt8195-disp-merge", 688 .data = (void *)MTK_DISP_MERGE }, 689 { .compatible = "mediatek,mt2701-disp-mutex", 690 .data = (void *)MTK_DISP_MUTEX }, 691 { .compatible = "mediatek,mt2712-disp-mutex", 692 .data = (void *)MTK_DISP_MUTEX }, 693 { .compatible = "mediatek,mt8167-disp-mutex", 694 .data = (void *)MTK_DISP_MUTEX }, 695 { .compatible = "mediatek,mt8173-disp-mutex", 696 .data = (void *)MTK_DISP_MUTEX }, 697 { .compatible = "mediatek,mt8183-disp-mutex", 698 .data = (void *)MTK_DISP_MUTEX }, 699 { .compatible = "mediatek,mt8186-disp-mutex", 700 .data = (void *)MTK_DISP_MUTEX }, 701 { .compatible = "mediatek,mt8188-disp-mutex", 702 .data = (void *)MTK_DISP_MUTEX }, 703 { .compatible = "mediatek,mt8192-disp-mutex", 704 .data = (void *)MTK_DISP_MUTEX }, 705 { .compatible = "mediatek,mt8195-disp-mutex", 706 .data = (void *)MTK_DISP_MUTEX }, 707 { .compatible = "mediatek,mt8173-disp-od", 708 .data = (void *)MTK_DISP_OD }, 709 { .compatible = "mediatek,mt2701-disp-ovl", 710 .data = (void *)MTK_DISP_OVL }, 711 { .compatible = "mediatek,mt8167-disp-ovl", 712 .data = (void *)MTK_DISP_OVL }, 713 { .compatible = "mediatek,mt8173-disp-ovl", 714 .data = (void *)MTK_DISP_OVL }, 715 { .compatible = "mediatek,mt8183-disp-ovl", 716 .data = (void *)MTK_DISP_OVL }, 717 { .compatible = "mediatek,mt8192-disp-ovl", 718 .data = (void *)MTK_DISP_OVL }, 719 { .compatible = "mediatek,mt8183-disp-ovl-2l", 720 .data = (void *)MTK_DISP_OVL_2L }, 721 { .compatible = "mediatek,mt8192-disp-ovl-2l", 722 .data = (void *)MTK_DISP_OVL_2L }, 723 { .compatible = "mediatek,mt8192-disp-postmask", 724 .data = (void *)MTK_DISP_POSTMASK }, 725 { .compatible = "mediatek,mt2701-disp-pwm", 726 .data = (void *)MTK_DISP_BLS }, 727 { .compatible = "mediatek,mt8167-disp-pwm", 728 .data = (void *)MTK_DISP_PWM }, 729 { .compatible = "mediatek,mt8173-disp-pwm", 730 .data = (void *)MTK_DISP_PWM }, 731 { .compatible = "mediatek,mt2701-disp-rdma", 732 .data = (void *)MTK_DISP_RDMA }, 733 { .compatible = "mediatek,mt8167-disp-rdma", 734 .data = (void *)MTK_DISP_RDMA }, 735 { .compatible = "mediatek,mt8173-disp-rdma", 736 .data = (void *)MTK_DISP_RDMA }, 737 { .compatible = "mediatek,mt8183-disp-rdma", 738 .data = (void *)MTK_DISP_RDMA }, 739 { .compatible = "mediatek,mt8195-disp-rdma", 740 .data = (void *)MTK_DISP_RDMA }, 741 { .compatible = "mediatek,mt8173-disp-ufoe", 742 .data = (void *)MTK_DISP_UFOE }, 743 { .compatible = "mediatek,mt8173-disp-wdma", 744 .data = (void *)MTK_DISP_WDMA }, 745 { .compatible = "mediatek,mt2701-dpi", 746 .data = (void *)MTK_DPI }, 747 { .compatible = "mediatek,mt8167-dsi", 748 .data = (void *)MTK_DSI }, 749 { .compatible = "mediatek,mt8173-dpi", 750 .data = (void *)MTK_DPI }, 751 { .compatible = "mediatek,mt8183-dpi", 752 .data = (void *)MTK_DPI }, 753 { .compatible = "mediatek,mt8186-dpi", 754 .data = (void *)MTK_DPI }, 755 { .compatible = "mediatek,mt8188-dp-intf", 756 .data = (void *)MTK_DP_INTF }, 757 { .compatible = "mediatek,mt8192-dpi", 758 .data = (void *)MTK_DPI }, 759 { .compatible = "mediatek,mt8195-dp-intf", 760 .data = (void *)MTK_DP_INTF }, 761 { .compatible = "mediatek,mt2701-dsi", 762 .data = (void *)MTK_DSI }, 763 { .compatible = "mediatek,mt8173-dsi", 764 .data = (void *)MTK_DSI }, 765 { .compatible = "mediatek,mt8183-dsi", 766 .data = (void *)MTK_DSI }, 767 { .compatible = "mediatek,mt8186-dsi", 768 .data = (void *)MTK_DSI }, 769 { } 770 }; 771 772 static int mtk_drm_probe(struct platform_device *pdev) 773 { 774 struct device *dev = &pdev->dev; 775 struct device_node *phandle = dev->parent->of_node; 776 const struct of_device_id *of_id; 777 struct mtk_drm_private *private; 778 struct device_node *node; 779 struct component_match *match = NULL; 780 struct platform_device *ovl_adaptor; 781 int ret; 782 int i; 783 784 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 785 if (!private) 786 return -ENOMEM; 787 788 private->mmsys_dev = dev->parent; 789 if (!private->mmsys_dev) { 790 dev_err(dev, "Failed to get MMSYS device\n"); 791 return -ENODEV; 792 } 793 794 of_id = of_match_node(mtk_drm_of_ids, phandle); 795 if (!of_id) 796 return -ENODEV; 797 798 private->data = of_id->data; 799 800 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 801 sizeof(*private->all_drm_private), 802 GFP_KERNEL); 803 if (!private->all_drm_private) 804 return -ENOMEM; 805 806 /* Bringup ovl_adaptor */ 807 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 808 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 809 PLATFORM_DEVID_AUTO, 810 (void *)private->mmsys_dev, 811 sizeof(*private->mmsys_dev)); 812 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 813 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 814 DDP_COMPONENT_DRM_OVL_ADAPTOR); 815 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 816 } 817 818 /* Iterate over sibling DISP function blocks */ 819 for_each_child_of_node(phandle->parent, node) { 820 const struct of_device_id *of_id; 821 enum mtk_ddp_comp_type comp_type; 822 int comp_id; 823 824 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 825 if (!of_id) 826 continue; 827 828 if (!of_device_is_available(node)) { 829 dev_dbg(dev, "Skipping disabled component %pOF\n", 830 node); 831 continue; 832 } 833 834 comp_type = (enum mtk_ddp_comp_type)(uintptr_t)of_id->data; 835 836 if (comp_type == MTK_DISP_MUTEX) { 837 int id; 838 839 id = of_alias_get_id(node, "mutex"); 840 if (id < 0 || id == private->data->mmsys_id) { 841 private->mutex_node = of_node_get(node); 842 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 843 } 844 continue; 845 } 846 847 comp_id = mtk_ddp_comp_get_id(node, comp_type); 848 if (comp_id < 0) { 849 dev_warn(dev, "Skipping unknown component %pOF\n", 850 node); 851 continue; 852 } 853 854 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 855 continue; 856 857 private->comp_node[comp_id] = of_node_get(node); 858 859 /* 860 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 861 * blocks have separate component platform drivers and initialize their own 862 * DDP component structure. The others are initialized here. 863 */ 864 if (comp_type == MTK_DISP_AAL || 865 comp_type == MTK_DISP_CCORR || 866 comp_type == MTK_DISP_COLOR || 867 comp_type == MTK_DISP_GAMMA || 868 comp_type == MTK_DISP_MERGE || 869 comp_type == MTK_DISP_OVL || 870 comp_type == MTK_DISP_OVL_2L || 871 comp_type == MTK_DISP_OVL_ADAPTOR || 872 comp_type == MTK_DISP_RDMA || 873 comp_type == MTK_DP_INTF || 874 comp_type == MTK_DPI || 875 comp_type == MTK_DSI) { 876 dev_info(dev, "Adding component match for %pOF\n", 877 node); 878 drm_of_component_match_add(dev, &match, component_compare_of, 879 node); 880 } 881 882 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 883 if (ret) { 884 of_node_put(node); 885 goto err_node; 886 } 887 } 888 889 if (!private->mutex_node) { 890 dev_err(dev, "Failed to find disp-mutex node\n"); 891 ret = -ENODEV; 892 goto err_node; 893 } 894 895 pm_runtime_enable(dev); 896 897 platform_set_drvdata(pdev, private); 898 899 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 900 if (ret) 901 goto err_pm; 902 903 return 0; 904 905 err_pm: 906 pm_runtime_disable(dev); 907 err_node: 908 of_node_put(private->mutex_node); 909 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 910 of_node_put(private->comp_node[i]); 911 return ret; 912 } 913 914 static void mtk_drm_remove(struct platform_device *pdev) 915 { 916 struct mtk_drm_private *private = platform_get_drvdata(pdev); 917 int i; 918 919 component_master_del(&pdev->dev, &mtk_drm_ops); 920 pm_runtime_disable(&pdev->dev); 921 of_node_put(private->mutex_node); 922 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 923 of_node_put(private->comp_node[i]); 924 } 925 926 static int mtk_drm_sys_prepare(struct device *dev) 927 { 928 struct mtk_drm_private *private = dev_get_drvdata(dev); 929 struct drm_device *drm = private->drm; 930 931 if (private->drm_master) 932 return drm_mode_config_helper_suspend(drm); 933 else 934 return 0; 935 } 936 937 static void mtk_drm_sys_complete(struct device *dev) 938 { 939 struct mtk_drm_private *private = dev_get_drvdata(dev); 940 struct drm_device *drm = private->drm; 941 int ret = 0; 942 943 if (private->drm_master) 944 ret = drm_mode_config_helper_resume(drm); 945 if (ret) 946 dev_err(dev, "Failed to resume\n"); 947 } 948 949 static const struct dev_pm_ops mtk_drm_pm_ops = { 950 .prepare = mtk_drm_sys_prepare, 951 .complete = mtk_drm_sys_complete, 952 }; 953 954 static struct platform_driver mtk_drm_platform_driver = { 955 .probe = mtk_drm_probe, 956 .remove_new = mtk_drm_remove, 957 .driver = { 958 .name = "mediatek-drm", 959 .pm = &mtk_drm_pm_ops, 960 }, 961 }; 962 963 static struct platform_driver * const mtk_drm_drivers[] = { 964 &mtk_disp_aal_driver, 965 &mtk_disp_ccorr_driver, 966 &mtk_disp_color_driver, 967 &mtk_disp_gamma_driver, 968 &mtk_disp_merge_driver, 969 &mtk_disp_ovl_adaptor_driver, 970 &mtk_disp_ovl_driver, 971 &mtk_disp_rdma_driver, 972 &mtk_dpi_driver, 973 &mtk_drm_platform_driver, 974 &mtk_dsi_driver, 975 &mtk_ethdr_driver, 976 &mtk_mdp_rdma_driver, 977 }; 978 979 static int __init mtk_drm_init(void) 980 { 981 return platform_register_drivers(mtk_drm_drivers, 982 ARRAY_SIZE(mtk_drm_drivers)); 983 } 984 985 static void __exit mtk_drm_exit(void) 986 { 987 platform_unregister_drivers(mtk_drm_drivers, 988 ARRAY_SIZE(mtk_drm_drivers)); 989 } 990 991 module_init(mtk_drm_init); 992 module_exit(mtk_drm_exit); 993 994 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 995 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 996 MODULE_LICENSE("GPL v2"); 997