1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/dma-mapping.h> 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fbdev_generic.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_ioctl.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 28 #include "mtk_drm_crtc.h" 29 #include "mtk_drm_ddp_comp.h" 30 #include "mtk_drm_drv.h" 31 #include "mtk_drm_gem.h" 32 33 #define DRIVER_NAME "mediatek" 34 #define DRIVER_DESC "Mediatek SoC DRM" 35 #define DRIVER_DATE "20150513" 36 #define DRIVER_MAJOR 1 37 #define DRIVER_MINOR 0 38 39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 41 }; 42 43 static struct drm_framebuffer * 44 mtk_drm_mode_fb_create(struct drm_device *dev, 45 struct drm_file *file, 46 const struct drm_mode_fb_cmd2 *cmd) 47 { 48 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 49 50 if (info->num_planes != 1) 51 return ERR_PTR(-EINVAL); 52 53 return drm_gem_fb_create(dev, file, cmd); 54 } 55 56 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 57 .fb_create = mtk_drm_mode_fb_create, 58 .atomic_check = drm_atomic_helper_check, 59 .atomic_commit = drm_atomic_helper_commit, 60 }; 61 62 static const unsigned int mt2701_mtk_ddp_main[] = { 63 DDP_COMPONENT_OVL0, 64 DDP_COMPONENT_RDMA0, 65 DDP_COMPONENT_COLOR0, 66 DDP_COMPONENT_BLS, 67 DDP_COMPONENT_DSI0, 68 }; 69 70 static const unsigned int mt2701_mtk_ddp_ext[] = { 71 DDP_COMPONENT_RDMA1, 72 DDP_COMPONENT_DPI0, 73 }; 74 75 static const unsigned int mt7623_mtk_ddp_main[] = { 76 DDP_COMPONENT_OVL0, 77 DDP_COMPONENT_RDMA0, 78 DDP_COMPONENT_COLOR0, 79 DDP_COMPONENT_BLS, 80 DDP_COMPONENT_DPI0, 81 }; 82 83 static const unsigned int mt7623_mtk_ddp_ext[] = { 84 DDP_COMPONENT_RDMA1, 85 DDP_COMPONENT_DSI0, 86 }; 87 88 static const unsigned int mt2712_mtk_ddp_main[] = { 89 DDP_COMPONENT_OVL0, 90 DDP_COMPONENT_COLOR0, 91 DDP_COMPONENT_AAL0, 92 DDP_COMPONENT_OD0, 93 DDP_COMPONENT_RDMA0, 94 DDP_COMPONENT_DPI0, 95 DDP_COMPONENT_PWM0, 96 }; 97 98 static const unsigned int mt2712_mtk_ddp_ext[] = { 99 DDP_COMPONENT_OVL1, 100 DDP_COMPONENT_COLOR1, 101 DDP_COMPONENT_AAL1, 102 DDP_COMPONENT_OD1, 103 DDP_COMPONENT_RDMA1, 104 DDP_COMPONENT_DPI1, 105 DDP_COMPONENT_PWM1, 106 }; 107 108 static const unsigned int mt2712_mtk_ddp_third[] = { 109 DDP_COMPONENT_RDMA2, 110 DDP_COMPONENT_DSI3, 111 DDP_COMPONENT_PWM2, 112 }; 113 114 static unsigned int mt8167_mtk_ddp_main[] = { 115 DDP_COMPONENT_OVL0, 116 DDP_COMPONENT_COLOR0, 117 DDP_COMPONENT_CCORR, 118 DDP_COMPONENT_AAL0, 119 DDP_COMPONENT_GAMMA, 120 DDP_COMPONENT_DITHER0, 121 DDP_COMPONENT_RDMA0, 122 DDP_COMPONENT_DSI0, 123 }; 124 125 static const unsigned int mt8173_mtk_ddp_main[] = { 126 DDP_COMPONENT_OVL0, 127 DDP_COMPONENT_COLOR0, 128 DDP_COMPONENT_AAL0, 129 DDP_COMPONENT_OD0, 130 DDP_COMPONENT_RDMA0, 131 DDP_COMPONENT_UFOE, 132 DDP_COMPONENT_DSI0, 133 DDP_COMPONENT_PWM0, 134 }; 135 136 static const unsigned int mt8173_mtk_ddp_ext[] = { 137 DDP_COMPONENT_OVL1, 138 DDP_COMPONENT_COLOR1, 139 DDP_COMPONENT_GAMMA, 140 DDP_COMPONENT_RDMA1, 141 DDP_COMPONENT_DPI0, 142 }; 143 144 static const unsigned int mt8183_mtk_ddp_main[] = { 145 DDP_COMPONENT_OVL0, 146 DDP_COMPONENT_OVL_2L0, 147 DDP_COMPONENT_RDMA0, 148 DDP_COMPONENT_COLOR0, 149 DDP_COMPONENT_CCORR, 150 DDP_COMPONENT_AAL0, 151 DDP_COMPONENT_GAMMA, 152 DDP_COMPONENT_DITHER0, 153 DDP_COMPONENT_DSI0, 154 }; 155 156 static const unsigned int mt8183_mtk_ddp_ext[] = { 157 DDP_COMPONENT_OVL_2L1, 158 DDP_COMPONENT_RDMA1, 159 DDP_COMPONENT_DPI0, 160 }; 161 162 static const unsigned int mt8186_mtk_ddp_main[] = { 163 DDP_COMPONENT_OVL0, 164 DDP_COMPONENT_RDMA0, 165 DDP_COMPONENT_COLOR0, 166 DDP_COMPONENT_CCORR, 167 DDP_COMPONENT_AAL0, 168 DDP_COMPONENT_GAMMA, 169 DDP_COMPONENT_POSTMASK0, 170 DDP_COMPONENT_DITHER0, 171 DDP_COMPONENT_DSI0, 172 }; 173 174 static const unsigned int mt8186_mtk_ddp_ext[] = { 175 DDP_COMPONENT_OVL_2L0, 176 DDP_COMPONENT_RDMA1, 177 DDP_COMPONENT_DPI0, 178 }; 179 180 static const unsigned int mt8188_mtk_ddp_main[] = { 181 DDP_COMPONENT_OVL0, 182 DDP_COMPONENT_RDMA0, 183 DDP_COMPONENT_COLOR0, 184 DDP_COMPONENT_CCORR, 185 DDP_COMPONENT_AAL0, 186 DDP_COMPONENT_GAMMA, 187 DDP_COMPONENT_POSTMASK0, 188 DDP_COMPONENT_DITHER0, 189 DDP_COMPONENT_DP_INTF0, 190 }; 191 192 static const unsigned int mt8192_mtk_ddp_main[] = { 193 DDP_COMPONENT_OVL0, 194 DDP_COMPONENT_OVL_2L0, 195 DDP_COMPONENT_RDMA0, 196 DDP_COMPONENT_COLOR0, 197 DDP_COMPONENT_CCORR, 198 DDP_COMPONENT_AAL0, 199 DDP_COMPONENT_GAMMA, 200 DDP_COMPONENT_POSTMASK0, 201 DDP_COMPONENT_DITHER0, 202 DDP_COMPONENT_DSI0, 203 }; 204 205 static const unsigned int mt8192_mtk_ddp_ext[] = { 206 DDP_COMPONENT_OVL_2L2, 207 DDP_COMPONENT_RDMA4, 208 DDP_COMPONENT_DPI0, 209 }; 210 211 static const unsigned int mt8195_mtk_ddp_main[] = { 212 DDP_COMPONENT_OVL0, 213 DDP_COMPONENT_RDMA0, 214 DDP_COMPONENT_COLOR0, 215 DDP_COMPONENT_CCORR, 216 DDP_COMPONENT_AAL0, 217 DDP_COMPONENT_GAMMA, 218 DDP_COMPONENT_DITHER0, 219 DDP_COMPONENT_DSC0, 220 DDP_COMPONENT_MERGE0, 221 DDP_COMPONENT_DP_INTF0, 222 }; 223 224 static const unsigned int mt8195_mtk_ddp_ext[] = { 225 DDP_COMPONENT_DRM_OVL_ADAPTOR, 226 DDP_COMPONENT_MERGE5, 227 DDP_COMPONENT_DP_INTF1, 228 }; 229 230 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 231 .main_path = mt2701_mtk_ddp_main, 232 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 233 .ext_path = mt2701_mtk_ddp_ext, 234 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 235 .shadow_register = true, 236 .mmsys_dev_num = 1, 237 }; 238 239 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 240 .main_path = mt7623_mtk_ddp_main, 241 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 242 .ext_path = mt7623_mtk_ddp_ext, 243 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 244 .shadow_register = true, 245 .mmsys_dev_num = 1, 246 }; 247 248 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 249 .main_path = mt2712_mtk_ddp_main, 250 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 251 .ext_path = mt2712_mtk_ddp_ext, 252 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 253 .third_path = mt2712_mtk_ddp_third, 254 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 255 .mmsys_dev_num = 1, 256 }; 257 258 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 259 .main_path = mt8167_mtk_ddp_main, 260 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 261 .mmsys_dev_num = 1, 262 }; 263 264 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 265 .main_path = mt8173_mtk_ddp_main, 266 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 267 .ext_path = mt8173_mtk_ddp_ext, 268 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 269 .mmsys_dev_num = 1, 270 }; 271 272 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 273 .main_path = mt8183_mtk_ddp_main, 274 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 275 .ext_path = mt8183_mtk_ddp_ext, 276 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 277 .mmsys_dev_num = 1, 278 }; 279 280 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 281 .main_path = mt8186_mtk_ddp_main, 282 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 283 .ext_path = mt8186_mtk_ddp_ext, 284 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 285 .mmsys_dev_num = 1, 286 }; 287 288 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 289 .main_path = mt8188_mtk_ddp_main, 290 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 291 }; 292 293 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 294 .main_path = mt8192_mtk_ddp_main, 295 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 296 .ext_path = mt8192_mtk_ddp_ext, 297 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 298 .mmsys_dev_num = 1, 299 }; 300 301 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 302 .main_path = mt8195_mtk_ddp_main, 303 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 304 .mmsys_dev_num = 2, 305 }; 306 307 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 308 .ext_path = mt8195_mtk_ddp_ext, 309 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 310 .mmsys_id = 1, 311 .mmsys_dev_num = 2, 312 }; 313 314 static const struct of_device_id mtk_drm_of_ids[] = { 315 { .compatible = "mediatek,mt2701-mmsys", 316 .data = &mt2701_mmsys_driver_data}, 317 { .compatible = "mediatek,mt7623-mmsys", 318 .data = &mt7623_mmsys_driver_data}, 319 { .compatible = "mediatek,mt2712-mmsys", 320 .data = &mt2712_mmsys_driver_data}, 321 { .compatible = "mediatek,mt8167-mmsys", 322 .data = &mt8167_mmsys_driver_data}, 323 { .compatible = "mediatek,mt8173-mmsys", 324 .data = &mt8173_mmsys_driver_data}, 325 { .compatible = "mediatek,mt8183-mmsys", 326 .data = &mt8183_mmsys_driver_data}, 327 { .compatible = "mediatek,mt8186-mmsys", 328 .data = &mt8186_mmsys_driver_data}, 329 { .compatible = "mediatek,mt8188-vdosys0", 330 .data = &mt8188_vdosys0_driver_data}, 331 { .compatible = "mediatek,mt8192-mmsys", 332 .data = &mt8192_mmsys_driver_data}, 333 { .compatible = "mediatek,mt8195-mmsys", 334 .data = &mt8195_vdosys0_driver_data}, 335 { .compatible = "mediatek,mt8195-vdosys0", 336 .data = &mt8195_vdosys0_driver_data}, 337 { .compatible = "mediatek,mt8195-vdosys1", 338 .data = &mt8195_vdosys1_driver_data}, 339 { } 340 }; 341 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 342 343 static int mtk_drm_match(struct device *dev, void *data) 344 { 345 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 346 return true; 347 return false; 348 } 349 350 static bool mtk_drm_get_all_drm_priv(struct device *dev) 351 { 352 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 353 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 354 struct device_node *phandle = dev->parent->of_node; 355 const struct of_device_id *of_id; 356 struct device_node *node; 357 struct device *drm_dev; 358 int cnt = 0; 359 int i, j; 360 361 for_each_child_of_node(phandle->parent, node) { 362 struct platform_device *pdev; 363 364 of_id = of_match_node(mtk_drm_of_ids, node); 365 if (!of_id) 366 continue; 367 368 pdev = of_find_device_by_node(node); 369 if (!pdev) 370 continue; 371 372 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 373 if (!drm_dev || !dev_get_drvdata(drm_dev)) 374 continue; 375 376 all_drm_priv[cnt] = dev_get_drvdata(drm_dev); 377 if (all_drm_priv[cnt] && all_drm_priv[cnt]->mtk_drm_bound) 378 cnt++; 379 } 380 381 if (drm_priv->data->mmsys_dev_num == cnt) { 382 for (i = 0; i < cnt; i++) 383 for (j = 0; j < cnt; j++) 384 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 385 386 return true; 387 } 388 389 return false; 390 } 391 392 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 393 { 394 const struct mtk_mmsys_driver_data *drv_data = private->data; 395 int i; 396 397 if (drv_data->main_path) 398 for (i = 0; i < drv_data->main_len; i++) 399 if (drv_data->main_path[i] == comp_id) 400 return true; 401 402 if (drv_data->ext_path) 403 for (i = 0; i < drv_data->ext_len; i++) 404 if (drv_data->ext_path[i] == comp_id) 405 return true; 406 407 if (drv_data->third_path) 408 for (i = 0; i < drv_data->third_len; i++) 409 if (drv_data->third_path[i] == comp_id) 410 return true; 411 412 return false; 413 } 414 415 static int mtk_drm_kms_init(struct drm_device *drm) 416 { 417 struct mtk_drm_private *private = drm->dev_private; 418 struct mtk_drm_private *priv_n; 419 struct device *dma_dev = NULL; 420 int ret, i, j; 421 422 if (drm_firmware_drivers_only()) 423 return -ENODEV; 424 425 ret = drmm_mode_config_init(drm); 426 if (ret) 427 goto put_mutex_dev; 428 429 drm->mode_config.min_width = 64; 430 drm->mode_config.min_height = 64; 431 432 /* 433 * set max width and height as default value(4096x4096). 434 * this value would be used to check framebuffer size limitation 435 * at drm_mode_addfb(). 436 */ 437 drm->mode_config.max_width = 4096; 438 drm->mode_config.max_height = 4096; 439 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 440 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 441 442 for (i = 0; i < private->data->mmsys_dev_num; i++) { 443 drm->dev_private = private->all_drm_private[i]; 444 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 445 if (ret) 446 goto put_mutex_dev; 447 } 448 449 /* 450 * Ensure internal panels are at the top of the connector list before 451 * crtc creation. 452 */ 453 drm_helper_move_panel_connectors_to_head(drm); 454 455 /* 456 * 1. We currently support two fixed data streams, each optional, 457 * and each statically assigned to a crtc: 458 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 459 * 2. For multi mmsys architecture, crtc path data are located in 460 * different drm private data structures. Loop through crtc index to 461 * create crtc from the main path and then ext_path and finally the 462 * third path. 463 */ 464 for (i = 0; i < MAX_CRTC; i++) { 465 for (j = 0; j < private->data->mmsys_dev_num; j++) { 466 priv_n = private->all_drm_private[j]; 467 468 if (i == 0 && priv_n->data->main_len) { 469 ret = mtk_drm_crtc_create(drm, priv_n->data->main_path, 470 priv_n->data->main_len, j); 471 if (ret) 472 goto err_component_unbind; 473 474 continue; 475 } else if (i == 1 && priv_n->data->ext_len) { 476 ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path, 477 priv_n->data->ext_len, j); 478 if (ret) 479 goto err_component_unbind; 480 481 continue; 482 } else if (i == 2 && priv_n->data->third_len) { 483 ret = mtk_drm_crtc_create(drm, priv_n->data->third_path, 484 priv_n->data->third_len, j); 485 if (ret) 486 goto err_component_unbind; 487 488 continue; 489 } 490 } 491 } 492 493 /* Use OVL device for all DMA memory allocations */ 494 dma_dev = mtk_drm_crtc_dma_dev_get(drm_crtc_from_index(drm, 0)); 495 if (!dma_dev) { 496 ret = -ENODEV; 497 dev_err(drm->dev, "Need at least one OVL device\n"); 498 goto err_component_unbind; 499 } 500 501 for (i = 0; i < private->data->mmsys_dev_num; i++) 502 private->all_drm_private[i]->dma_dev = dma_dev; 503 504 /* 505 * Configure the DMA segment size to make sure we get contiguous IOVA 506 * when importing PRIME buffers. 507 */ 508 ret = dma_set_max_seg_size(dma_dev, UINT_MAX); 509 if (ret) { 510 dev_err(dma_dev, "Failed to set DMA segment size\n"); 511 goto err_component_unbind; 512 } 513 514 ret = drm_vblank_init(drm, MAX_CRTC); 515 if (ret < 0) 516 goto err_component_unbind; 517 518 drm_kms_helper_poll_init(drm); 519 drm_mode_config_reset(drm); 520 521 return 0; 522 523 err_component_unbind: 524 for (i = 0; i < private->data->mmsys_dev_num; i++) 525 component_unbind_all(private->all_drm_private[i]->dev, drm); 526 put_mutex_dev: 527 for (i = 0; i < private->data->mmsys_dev_num; i++) 528 put_device(private->all_drm_private[i]->mutex_dev); 529 530 return ret; 531 } 532 533 static void mtk_drm_kms_deinit(struct drm_device *drm) 534 { 535 drm_kms_helper_poll_fini(drm); 536 drm_atomic_helper_shutdown(drm); 537 538 component_unbind_all(drm->dev, drm); 539 } 540 541 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 542 543 /* 544 * We need to override this because the device used to import the memory is 545 * not dev->dev, as drm_gem_prime_import() expects. 546 */ 547 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev, 548 struct dma_buf *dma_buf) 549 { 550 struct mtk_drm_private *private = dev->dev_private; 551 552 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 553 } 554 555 static const struct drm_driver mtk_drm_driver = { 556 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 557 558 .dumb_create = mtk_drm_gem_dumb_create, 559 560 .gem_prime_import = mtk_drm_gem_prime_import, 561 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 562 .fops = &mtk_drm_fops, 563 564 .name = DRIVER_NAME, 565 .desc = DRIVER_DESC, 566 .date = DRIVER_DATE, 567 .major = DRIVER_MAJOR, 568 .minor = DRIVER_MINOR, 569 }; 570 571 static int compare_dev(struct device *dev, void *data) 572 { 573 return dev == (struct device *)data; 574 } 575 576 static int mtk_drm_bind(struct device *dev) 577 { 578 struct mtk_drm_private *private = dev_get_drvdata(dev); 579 struct platform_device *pdev; 580 struct drm_device *drm; 581 int ret, i; 582 583 if (!iommu_present(&platform_bus_type)) 584 return -EPROBE_DEFER; 585 586 pdev = of_find_device_by_node(private->mutex_node); 587 if (!pdev) { 588 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 589 private->mutex_node); 590 of_node_put(private->mutex_node); 591 return -EPROBE_DEFER; 592 } 593 594 private->mutex_dev = &pdev->dev; 595 private->mtk_drm_bound = true; 596 private->dev = dev; 597 598 if (!mtk_drm_get_all_drm_priv(dev)) 599 return 0; 600 601 drm = drm_dev_alloc(&mtk_drm_driver, dev); 602 if (IS_ERR(drm)) 603 return PTR_ERR(drm); 604 605 private->drm_master = true; 606 drm->dev_private = private; 607 for (i = 0; i < private->data->mmsys_dev_num; i++) 608 private->all_drm_private[i]->drm = drm; 609 610 ret = mtk_drm_kms_init(drm); 611 if (ret < 0) 612 goto err_free; 613 614 ret = drm_dev_register(drm, 0); 615 if (ret < 0) 616 goto err_deinit; 617 618 drm_fbdev_generic_setup(drm, 32); 619 620 return 0; 621 622 err_deinit: 623 mtk_drm_kms_deinit(drm); 624 err_free: 625 private->drm = NULL; 626 drm_dev_put(drm); 627 return ret; 628 } 629 630 static void mtk_drm_unbind(struct device *dev) 631 { 632 struct mtk_drm_private *private = dev_get_drvdata(dev); 633 634 /* for multi mmsys dev, unregister drm dev in mmsys master */ 635 if (private->drm_master) { 636 drm_dev_unregister(private->drm); 637 mtk_drm_kms_deinit(private->drm); 638 drm_dev_put(private->drm); 639 } 640 private->mtk_drm_bound = false; 641 private->drm_master = false; 642 private->drm = NULL; 643 } 644 645 static const struct component_master_ops mtk_drm_ops = { 646 .bind = mtk_drm_bind, 647 .unbind = mtk_drm_unbind, 648 }; 649 650 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 651 { .compatible = "mediatek,mt8167-disp-aal", 652 .data = (void *)MTK_DISP_AAL}, 653 { .compatible = "mediatek,mt8173-disp-aal", 654 .data = (void *)MTK_DISP_AAL}, 655 { .compatible = "mediatek,mt8183-disp-aal", 656 .data = (void *)MTK_DISP_AAL}, 657 { .compatible = "mediatek,mt8192-disp-aal", 658 .data = (void *)MTK_DISP_AAL}, 659 { .compatible = "mediatek,mt8167-disp-ccorr", 660 .data = (void *)MTK_DISP_CCORR }, 661 { .compatible = "mediatek,mt8183-disp-ccorr", 662 .data = (void *)MTK_DISP_CCORR }, 663 { .compatible = "mediatek,mt8192-disp-ccorr", 664 .data = (void *)MTK_DISP_CCORR }, 665 { .compatible = "mediatek,mt2701-disp-color", 666 .data = (void *)MTK_DISP_COLOR }, 667 { .compatible = "mediatek,mt8167-disp-color", 668 .data = (void *)MTK_DISP_COLOR }, 669 { .compatible = "mediatek,mt8173-disp-color", 670 .data = (void *)MTK_DISP_COLOR }, 671 { .compatible = "mediatek,mt8167-disp-dither", 672 .data = (void *)MTK_DISP_DITHER }, 673 { .compatible = "mediatek,mt8183-disp-dither", 674 .data = (void *)MTK_DISP_DITHER }, 675 { .compatible = "mediatek,mt8195-disp-dsc", 676 .data = (void *)MTK_DISP_DSC }, 677 { .compatible = "mediatek,mt8167-disp-gamma", 678 .data = (void *)MTK_DISP_GAMMA, }, 679 { .compatible = "mediatek,mt8173-disp-gamma", 680 .data = (void *)MTK_DISP_GAMMA, }, 681 { .compatible = "mediatek,mt8183-disp-gamma", 682 .data = (void *)MTK_DISP_GAMMA, }, 683 { .compatible = "mediatek,mt8195-disp-merge", 684 .data = (void *)MTK_DISP_MERGE }, 685 { .compatible = "mediatek,mt2701-disp-mutex", 686 .data = (void *)MTK_DISP_MUTEX }, 687 { .compatible = "mediatek,mt2712-disp-mutex", 688 .data = (void *)MTK_DISP_MUTEX }, 689 { .compatible = "mediatek,mt8167-disp-mutex", 690 .data = (void *)MTK_DISP_MUTEX }, 691 { .compatible = "mediatek,mt8173-disp-mutex", 692 .data = (void *)MTK_DISP_MUTEX }, 693 { .compatible = "mediatek,mt8183-disp-mutex", 694 .data = (void *)MTK_DISP_MUTEX }, 695 { .compatible = "mediatek,mt8186-disp-mutex", 696 .data = (void *)MTK_DISP_MUTEX }, 697 { .compatible = "mediatek,mt8188-disp-mutex", 698 .data = (void *)MTK_DISP_MUTEX }, 699 { .compatible = "mediatek,mt8192-disp-mutex", 700 .data = (void *)MTK_DISP_MUTEX }, 701 { .compatible = "mediatek,mt8195-disp-mutex", 702 .data = (void *)MTK_DISP_MUTEX }, 703 { .compatible = "mediatek,mt8173-disp-od", 704 .data = (void *)MTK_DISP_OD }, 705 { .compatible = "mediatek,mt2701-disp-ovl", 706 .data = (void *)MTK_DISP_OVL }, 707 { .compatible = "mediatek,mt8167-disp-ovl", 708 .data = (void *)MTK_DISP_OVL }, 709 { .compatible = "mediatek,mt8173-disp-ovl", 710 .data = (void *)MTK_DISP_OVL }, 711 { .compatible = "mediatek,mt8183-disp-ovl", 712 .data = (void *)MTK_DISP_OVL }, 713 { .compatible = "mediatek,mt8192-disp-ovl", 714 .data = (void *)MTK_DISP_OVL }, 715 { .compatible = "mediatek,mt8183-disp-ovl-2l", 716 .data = (void *)MTK_DISP_OVL_2L }, 717 { .compatible = "mediatek,mt8192-disp-ovl-2l", 718 .data = (void *)MTK_DISP_OVL_2L }, 719 { .compatible = "mediatek,mt8192-disp-postmask", 720 .data = (void *)MTK_DISP_POSTMASK }, 721 { .compatible = "mediatek,mt2701-disp-pwm", 722 .data = (void *)MTK_DISP_BLS }, 723 { .compatible = "mediatek,mt8167-disp-pwm", 724 .data = (void *)MTK_DISP_PWM }, 725 { .compatible = "mediatek,mt8173-disp-pwm", 726 .data = (void *)MTK_DISP_PWM }, 727 { .compatible = "mediatek,mt2701-disp-rdma", 728 .data = (void *)MTK_DISP_RDMA }, 729 { .compatible = "mediatek,mt8167-disp-rdma", 730 .data = (void *)MTK_DISP_RDMA }, 731 { .compatible = "mediatek,mt8173-disp-rdma", 732 .data = (void *)MTK_DISP_RDMA }, 733 { .compatible = "mediatek,mt8183-disp-rdma", 734 .data = (void *)MTK_DISP_RDMA }, 735 { .compatible = "mediatek,mt8195-disp-rdma", 736 .data = (void *)MTK_DISP_RDMA }, 737 { .compatible = "mediatek,mt8173-disp-ufoe", 738 .data = (void *)MTK_DISP_UFOE }, 739 { .compatible = "mediatek,mt8173-disp-wdma", 740 .data = (void *)MTK_DISP_WDMA }, 741 { .compatible = "mediatek,mt2701-dpi", 742 .data = (void *)MTK_DPI }, 743 { .compatible = "mediatek,mt8167-dsi", 744 .data = (void *)MTK_DSI }, 745 { .compatible = "mediatek,mt8173-dpi", 746 .data = (void *)MTK_DPI }, 747 { .compatible = "mediatek,mt8183-dpi", 748 .data = (void *)MTK_DPI }, 749 { .compatible = "mediatek,mt8186-dpi", 750 .data = (void *)MTK_DPI }, 751 { .compatible = "mediatek,mt8188-dp-intf", 752 .data = (void *)MTK_DP_INTF }, 753 { .compatible = "mediatek,mt8192-dpi", 754 .data = (void *)MTK_DPI }, 755 { .compatible = "mediatek,mt8195-dp-intf", 756 .data = (void *)MTK_DP_INTF }, 757 { .compatible = "mediatek,mt2701-dsi", 758 .data = (void *)MTK_DSI }, 759 { .compatible = "mediatek,mt8173-dsi", 760 .data = (void *)MTK_DSI }, 761 { .compatible = "mediatek,mt8183-dsi", 762 .data = (void *)MTK_DSI }, 763 { .compatible = "mediatek,mt8186-dsi", 764 .data = (void *)MTK_DSI }, 765 { } 766 }; 767 768 static int mtk_drm_probe(struct platform_device *pdev) 769 { 770 struct device *dev = &pdev->dev; 771 struct device_node *phandle = dev->parent->of_node; 772 const struct of_device_id *of_id; 773 struct mtk_drm_private *private; 774 struct device_node *node; 775 struct component_match *match = NULL; 776 struct platform_device *ovl_adaptor; 777 int ret; 778 int i; 779 780 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 781 if (!private) 782 return -ENOMEM; 783 784 private->mmsys_dev = dev->parent; 785 if (!private->mmsys_dev) { 786 dev_err(dev, "Failed to get MMSYS device\n"); 787 return -ENODEV; 788 } 789 790 of_id = of_match_node(mtk_drm_of_ids, phandle); 791 if (!of_id) 792 return -ENODEV; 793 794 private->data = of_id->data; 795 796 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 797 sizeof(*private->all_drm_private), 798 GFP_KERNEL); 799 if (!private->all_drm_private) 800 return -ENOMEM; 801 802 /* Bringup ovl_adaptor */ 803 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 804 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 805 PLATFORM_DEVID_AUTO, 806 (void *)private->mmsys_dev, 807 sizeof(*private->mmsys_dev)); 808 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 809 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 810 DDP_COMPONENT_DRM_OVL_ADAPTOR); 811 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 812 } 813 814 /* Iterate over sibling DISP function blocks */ 815 for_each_child_of_node(phandle->parent, node) { 816 const struct of_device_id *of_id; 817 enum mtk_ddp_comp_type comp_type; 818 int comp_id; 819 820 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 821 if (!of_id) 822 continue; 823 824 if (!of_device_is_available(node)) { 825 dev_dbg(dev, "Skipping disabled component %pOF\n", 826 node); 827 continue; 828 } 829 830 comp_type = (enum mtk_ddp_comp_type)of_id->data; 831 832 if (comp_type == MTK_DISP_MUTEX) { 833 int id; 834 835 id = of_alias_get_id(node, "mutex"); 836 if (id < 0 || id == private->data->mmsys_id) { 837 private->mutex_node = of_node_get(node); 838 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 839 } 840 continue; 841 } 842 843 comp_id = mtk_ddp_comp_get_id(node, comp_type); 844 if (comp_id < 0) { 845 dev_warn(dev, "Skipping unknown component %pOF\n", 846 node); 847 continue; 848 } 849 850 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 851 continue; 852 853 private->comp_node[comp_id] = of_node_get(node); 854 855 /* 856 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 857 * blocks have separate component platform drivers and initialize their own 858 * DDP component structure. The others are initialized here. 859 */ 860 if (comp_type == MTK_DISP_AAL || 861 comp_type == MTK_DISP_CCORR || 862 comp_type == MTK_DISP_COLOR || 863 comp_type == MTK_DISP_GAMMA || 864 comp_type == MTK_DISP_MERGE || 865 comp_type == MTK_DISP_OVL || 866 comp_type == MTK_DISP_OVL_2L || 867 comp_type == MTK_DISP_OVL_ADAPTOR || 868 comp_type == MTK_DISP_RDMA || 869 comp_type == MTK_DP_INTF || 870 comp_type == MTK_DPI || 871 comp_type == MTK_DSI) { 872 dev_info(dev, "Adding component match for %pOF\n", 873 node); 874 drm_of_component_match_add(dev, &match, component_compare_of, 875 node); 876 } 877 878 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 879 if (ret) { 880 of_node_put(node); 881 goto err_node; 882 } 883 } 884 885 if (!private->mutex_node) { 886 dev_err(dev, "Failed to find disp-mutex node\n"); 887 ret = -ENODEV; 888 goto err_node; 889 } 890 891 pm_runtime_enable(dev); 892 893 platform_set_drvdata(pdev, private); 894 895 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 896 if (ret) 897 goto err_pm; 898 899 return 0; 900 901 err_pm: 902 pm_runtime_disable(dev); 903 err_node: 904 of_node_put(private->mutex_node); 905 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 906 of_node_put(private->comp_node[i]); 907 return ret; 908 } 909 910 static int mtk_drm_remove(struct platform_device *pdev) 911 { 912 struct mtk_drm_private *private = platform_get_drvdata(pdev); 913 int i; 914 915 component_master_del(&pdev->dev, &mtk_drm_ops); 916 pm_runtime_disable(&pdev->dev); 917 of_node_put(private->mutex_node); 918 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 919 of_node_put(private->comp_node[i]); 920 921 return 0; 922 } 923 924 static int mtk_drm_sys_prepare(struct device *dev) 925 { 926 struct mtk_drm_private *private = dev_get_drvdata(dev); 927 struct drm_device *drm = private->drm; 928 929 if (private->drm_master) 930 return drm_mode_config_helper_suspend(drm); 931 else 932 return 0; 933 } 934 935 static void mtk_drm_sys_complete(struct device *dev) 936 { 937 struct mtk_drm_private *private = dev_get_drvdata(dev); 938 struct drm_device *drm = private->drm; 939 int ret = 0; 940 941 if (private->drm_master) 942 ret = drm_mode_config_helper_resume(drm); 943 if (ret) 944 dev_err(dev, "Failed to resume\n"); 945 } 946 947 static const struct dev_pm_ops mtk_drm_pm_ops = { 948 .prepare = mtk_drm_sys_prepare, 949 .complete = mtk_drm_sys_complete, 950 }; 951 952 static struct platform_driver mtk_drm_platform_driver = { 953 .probe = mtk_drm_probe, 954 .remove = mtk_drm_remove, 955 .driver = { 956 .name = "mediatek-drm", 957 .pm = &mtk_drm_pm_ops, 958 }, 959 }; 960 961 static struct platform_driver * const mtk_drm_drivers[] = { 962 &mtk_disp_aal_driver, 963 &mtk_disp_ccorr_driver, 964 &mtk_disp_color_driver, 965 &mtk_disp_gamma_driver, 966 &mtk_disp_merge_driver, 967 &mtk_disp_ovl_adaptor_driver, 968 &mtk_disp_ovl_driver, 969 &mtk_disp_rdma_driver, 970 &mtk_dpi_driver, 971 &mtk_drm_platform_driver, 972 &mtk_dsi_driver, 973 &mtk_ethdr_driver, 974 &mtk_mdp_rdma_driver, 975 }; 976 977 static int __init mtk_drm_init(void) 978 { 979 return platform_register_drivers(mtk_drm_drivers, 980 ARRAY_SIZE(mtk_drm_drivers)); 981 } 982 983 static void __exit mtk_drm_exit(void) 984 { 985 platform_unregister_drivers(mtk_drm_drivers, 986 ARRAY_SIZE(mtk_drm_drivers)); 987 } 988 989 module_init(mtk_drm_init); 990 module_exit(mtk_drm_exit); 991 992 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 993 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 994 MODULE_LICENSE("GPL v2"); 995