1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Authors: 5 * YT Shen <yt.shen@mediatek.com> 6 * CK Hu <ck.hu@mediatek.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_irq.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 16 #include "mtk_drm_drv.h" 17 #include "mtk_drm_plane.h" 18 #include "mtk_drm_ddp_comp.h" 19 #include "mtk_drm_crtc.h" 20 21 #define DISP_OD_EN 0x0000 22 #define DISP_OD_INTEN 0x0008 23 #define DISP_OD_INTSTA 0x000c 24 #define DISP_OD_CFG 0x0020 25 #define DISP_OD_SIZE 0x0030 26 #define DISP_DITHER_5 0x0114 27 #define DISP_DITHER_7 0x011c 28 #define DISP_DITHER_15 0x013c 29 #define DISP_DITHER_16 0x0140 30 31 #define DISP_REG_UFO_START 0x0000 32 33 #define DISP_AAL_EN 0x0000 34 #define DISP_AAL_SIZE 0x0030 35 36 #define DISP_CCORR_EN 0x0000 37 #define CCORR_EN BIT(0) 38 #define DISP_CCORR_CFG 0x0020 39 #define CCORR_RELAY_MODE BIT(0) 40 #define DISP_CCORR_SIZE 0x0030 41 42 #define DISP_DITHER_EN 0x0000 43 #define DITHER_EN BIT(0) 44 #define DISP_DITHER_CFG 0x0020 45 #define DITHER_RELAY_MODE BIT(0) 46 #define DISP_DITHER_SIZE 0x0030 47 48 #define DISP_GAMMA_EN 0x0000 49 #define DISP_GAMMA_CFG 0x0020 50 #define DISP_GAMMA_SIZE 0x0030 51 #define DISP_GAMMA_LUT 0x0700 52 53 #define LUT_10BIT_MASK 0x03ff 54 55 #define OD_RELAYMODE BIT(0) 56 57 #define UFO_BYPASS BIT(2) 58 59 #define AAL_EN BIT(0) 60 61 #define GAMMA_EN BIT(0) 62 #define GAMMA_LUT_EN BIT(1) 63 64 #define DISP_DITHERING BIT(2) 65 #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) 66 #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) 67 #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20) 68 #define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16) 69 #define DITHER_NEW_BIT_MODE BIT(0) 70 #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28) 71 #define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24) 72 #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20) 73 #define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16) 74 #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) 75 #define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8) 76 #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) 77 #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0) 78 79 void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, 80 unsigned int CFG) 81 { 82 /* If bpc equal to 0, the dithering function didn't be enabled */ 83 if (bpc == 0) 84 return; 85 86 if (bpc >= MTK_MIN_BPC) { 87 writel(0, comp->regs + DISP_DITHER_5); 88 writel(0, comp->regs + DISP_DITHER_7); 89 writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | 90 DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | 91 DITHER_NEW_BIT_MODE, 92 comp->regs + DISP_DITHER_15); 93 writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | 94 DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | 95 DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | 96 DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), 97 comp->regs + DISP_DITHER_16); 98 writel(DISP_DITHERING, comp->regs + CFG); 99 } 100 } 101 102 static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, 103 unsigned int h, unsigned int vrefresh, 104 unsigned int bpc) 105 { 106 writel(w << 16 | h, comp->regs + DISP_OD_SIZE); 107 writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG); 108 mtk_dither_set(comp, bpc, DISP_OD_CFG); 109 } 110 111 static void mtk_od_start(struct mtk_ddp_comp *comp) 112 { 113 writel(1, comp->regs + DISP_OD_EN); 114 } 115 116 static void mtk_ufoe_start(struct mtk_ddp_comp *comp) 117 { 118 writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START); 119 } 120 121 static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, 122 unsigned int h, unsigned int vrefresh, 123 unsigned int bpc) 124 { 125 writel(h << 16 | w, comp->regs + DISP_AAL_SIZE); 126 } 127 128 static void mtk_aal_start(struct mtk_ddp_comp *comp) 129 { 130 writel(AAL_EN, comp->regs + DISP_AAL_EN); 131 } 132 133 static void mtk_aal_stop(struct mtk_ddp_comp *comp) 134 { 135 writel_relaxed(0x0, comp->regs + DISP_AAL_EN); 136 } 137 138 static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, 139 unsigned int h, unsigned int vrefresh, 140 unsigned int bpc) 141 { 142 writel(h << 16 | w, comp->regs + DISP_CCORR_SIZE); 143 writel(CCORR_RELAY_MODE, comp->regs + DISP_CCORR_CFG); 144 } 145 146 static void mtk_ccorr_start(struct mtk_ddp_comp *comp) 147 { 148 writel(CCORR_EN, comp->regs + DISP_CCORR_EN); 149 } 150 151 static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) 152 { 153 writel_relaxed(0x0, comp->regs + DISP_CCORR_EN); 154 } 155 156 static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, 157 unsigned int h, unsigned int vrefresh, 158 unsigned int bpc) 159 { 160 writel(h << 16 | w, comp->regs + DISP_DITHER_SIZE); 161 writel(DITHER_RELAY_MODE, comp->regs + DISP_DITHER_CFG); 162 } 163 164 static void mtk_dither_start(struct mtk_ddp_comp *comp) 165 { 166 writel(DITHER_EN, comp->regs + DISP_DITHER_EN); 167 } 168 169 static void mtk_dither_stop(struct mtk_ddp_comp *comp) 170 { 171 writel_relaxed(0x0, comp->regs + DISP_DITHER_EN); 172 } 173 174 static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, 175 unsigned int h, unsigned int vrefresh, 176 unsigned int bpc) 177 { 178 writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE); 179 mtk_dither_set(comp, bpc, DISP_GAMMA_CFG); 180 } 181 182 static void mtk_gamma_start(struct mtk_ddp_comp *comp) 183 { 184 writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN); 185 } 186 187 static void mtk_gamma_stop(struct mtk_ddp_comp *comp) 188 { 189 writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN); 190 } 191 192 static void mtk_gamma_set(struct mtk_ddp_comp *comp, 193 struct drm_crtc_state *state) 194 { 195 unsigned int i, reg; 196 struct drm_color_lut *lut; 197 void __iomem *lut_base; 198 u32 word; 199 200 if (state->gamma_lut) { 201 reg = readl(comp->regs + DISP_GAMMA_CFG); 202 reg = reg | GAMMA_LUT_EN; 203 writel(reg, comp->regs + DISP_GAMMA_CFG); 204 lut_base = comp->regs + DISP_GAMMA_LUT; 205 lut = (struct drm_color_lut *)state->gamma_lut->data; 206 for (i = 0; i < MTK_LUT_SIZE; i++) { 207 word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + 208 (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + 209 ((lut[i].blue >> 6) & LUT_10BIT_MASK); 210 writel(word, (lut_base + i * 4)); 211 } 212 } 213 } 214 215 static const struct mtk_ddp_comp_funcs ddp_aal = { 216 .gamma_set = mtk_gamma_set, 217 .config = mtk_aal_config, 218 .start = mtk_aal_start, 219 .stop = mtk_aal_stop, 220 }; 221 222 static const struct mtk_ddp_comp_funcs ddp_ccorr = { 223 .config = mtk_ccorr_config, 224 .start = mtk_ccorr_start, 225 .stop = mtk_ccorr_stop, 226 }; 227 228 static const struct mtk_ddp_comp_funcs ddp_dither = { 229 .config = mtk_dither_config, 230 .start = mtk_dither_start, 231 .stop = mtk_dither_stop, 232 }; 233 234 static const struct mtk_ddp_comp_funcs ddp_gamma = { 235 .gamma_set = mtk_gamma_set, 236 .config = mtk_gamma_config, 237 .start = mtk_gamma_start, 238 .stop = mtk_gamma_stop, 239 }; 240 241 static const struct mtk_ddp_comp_funcs ddp_od = { 242 .config = mtk_od_config, 243 .start = mtk_od_start, 244 }; 245 246 static const struct mtk_ddp_comp_funcs ddp_ufoe = { 247 .start = mtk_ufoe_start, 248 }; 249 250 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { 251 [MTK_DISP_OVL] = "ovl", 252 [MTK_DISP_OVL_2L] = "ovl_2l", 253 [MTK_DISP_RDMA] = "rdma", 254 [MTK_DISP_WDMA] = "wdma", 255 [MTK_DISP_COLOR] = "color", 256 [MTK_DISP_CCORR] = "ccorr", 257 [MTK_DISP_AAL] = "aal", 258 [MTK_DISP_GAMMA] = "gamma", 259 [MTK_DISP_DITHER] = "dither", 260 [MTK_DISP_UFOE] = "ufoe", 261 [MTK_DSI] = "dsi", 262 [MTK_DPI] = "dpi", 263 [MTK_DISP_PWM] = "pwm", 264 [MTK_DISP_MUTEX] = "mutex", 265 [MTK_DISP_OD] = "od", 266 [MTK_DISP_BLS] = "bls", 267 }; 268 269 struct mtk_ddp_comp_match { 270 enum mtk_ddp_comp_type type; 271 int alias_id; 272 const struct mtk_ddp_comp_funcs *funcs; 273 }; 274 275 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { 276 [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, 277 [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, 278 [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, 279 [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, 280 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, 281 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, 282 [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, 283 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, 284 [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL }, 285 [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, 286 [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, 287 [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL }, 288 [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL }, 289 [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, 290 [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, 291 [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, 292 [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, 293 [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, 294 [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL }, 295 [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL }, 296 [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, 297 [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, 298 [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, 299 [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, 300 [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, 301 [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, 302 [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, 303 [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, 304 [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, 305 }; 306 307 int mtk_ddp_comp_get_id(struct device_node *node, 308 enum mtk_ddp_comp_type comp_type) 309 { 310 int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]); 311 int i; 312 313 for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) { 314 if (comp_type == mtk_ddp_matches[i].type && 315 (id < 0 || id == mtk_ddp_matches[i].alias_id)) 316 return i; 317 } 318 319 return -EINVAL; 320 } 321 322 int mtk_ddp_comp_init(struct device *dev, struct device_node *node, 323 struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, 324 const struct mtk_ddp_comp_funcs *funcs) 325 { 326 enum mtk_ddp_comp_type type; 327 struct device_node *larb_node; 328 struct platform_device *larb_pdev; 329 330 if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) 331 return -EINVAL; 332 333 type = mtk_ddp_matches[comp_id].type; 334 335 comp->id = comp_id; 336 comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs; 337 338 if (comp_id == DDP_COMPONENT_BLS || 339 comp_id == DDP_COMPONENT_DPI0 || 340 comp_id == DDP_COMPONENT_DPI1 || 341 comp_id == DDP_COMPONENT_DSI0 || 342 comp_id == DDP_COMPONENT_DSI1 || 343 comp_id == DDP_COMPONENT_DSI2 || 344 comp_id == DDP_COMPONENT_DSI3 || 345 comp_id == DDP_COMPONENT_PWM0) { 346 comp->regs = NULL; 347 comp->clk = NULL; 348 comp->irq = 0; 349 return 0; 350 } 351 352 comp->regs = of_iomap(node, 0); 353 comp->irq = of_irq_get(node, 0); 354 comp->clk = of_clk_get(node, 0); 355 if (IS_ERR(comp->clk)) 356 return PTR_ERR(comp->clk); 357 358 /* Only DMA capable components need the LARB property */ 359 comp->larb_dev = NULL; 360 if (type != MTK_DISP_OVL && 361 type != MTK_DISP_RDMA && 362 type != MTK_DISP_WDMA) 363 return 0; 364 365 larb_node = of_parse_phandle(node, "mediatek,larb", 0); 366 if (!larb_node) { 367 dev_err(dev, 368 "Missing mediadek,larb phandle in %pOF node\n", node); 369 return -EINVAL; 370 } 371 372 larb_pdev = of_find_device_by_node(larb_node); 373 if (!larb_pdev) { 374 dev_warn(dev, "Waiting for larb device %pOF\n", larb_node); 375 of_node_put(larb_node); 376 return -EPROBE_DEFER; 377 } 378 of_node_put(larb_node); 379 380 comp->larb_dev = &larb_pdev->dev; 381 382 return 0; 383 } 384 385 int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp) 386 { 387 struct mtk_drm_private *private = drm->dev_private; 388 389 if (private->ddp_comp[comp->id]) 390 return -EBUSY; 391 392 private->ddp_comp[comp->id] = comp; 393 return 0; 394 } 395 396 void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp) 397 { 398 struct mtk_drm_private *private = drm->dev_private; 399 400 private->ddp_comp[comp->id] = NULL; 401 } 402