1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  * Authors:
5  *	YT Shen <yt.shen@mediatek.com>
6  *	CK Hu <ck.hu@mediatek.com>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/soc/mediatek/mtk-cmdq.h>
15 #include <drm/drm_print.h>
16 
17 #include "mtk_disp_drv.h"
18 #include "mtk_drm_drv.h"
19 #include "mtk_drm_plane.h"
20 #include "mtk_drm_ddp_comp.h"
21 #include "mtk_drm_crtc.h"
22 
23 
24 #define DISP_REG_DITHER_EN			0x0000
25 #define DITHER_EN				BIT(0)
26 #define DISP_REG_DITHER_CFG			0x0020
27 #define DITHER_RELAY_MODE			BIT(0)
28 #define DITHER_ENGINE_EN			BIT(1)
29 #define DISP_DITHERING				BIT(2)
30 #define DISP_REG_DITHER_SIZE			0x0030
31 #define DISP_REG_DITHER_5			0x0114
32 #define DISP_REG_DITHER_7			0x011c
33 #define DISP_REG_DITHER_15			0x013c
34 #define DITHER_LSB_ERR_SHIFT_R(x)		(((x) & 0x7) << 28)
35 #define DITHER_ADD_LSHIFT_R(x)			(((x) & 0x7) << 20)
36 #define DITHER_NEW_BIT_MODE			BIT(0)
37 #define DISP_REG_DITHER_16			0x0140
38 #define DITHER_LSB_ERR_SHIFT_B(x)		(((x) & 0x7) << 28)
39 #define DITHER_ADD_LSHIFT_B(x)			(((x) & 0x7) << 20)
40 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
41 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
42 
43 #define DISP_REG_OD_EN				0x0000
44 #define DISP_REG_OD_CFG				0x0020
45 #define OD_RELAYMODE				BIT(0)
46 #define DISP_REG_OD_SIZE			0x0030
47 
48 #define DISP_REG_POSTMASK_EN			0x0000
49 #define POSTMASK_EN					BIT(0)
50 #define DISP_REG_POSTMASK_CFG			0x0020
51 #define POSTMASK_RELAY_MODE				BIT(0)
52 #define DISP_REG_POSTMASK_SIZE			0x0030
53 
54 #define DISP_REG_UFO_START			0x0000
55 #define UFO_BYPASS				BIT(2)
56 
57 struct mtk_ddp_comp_dev {
58 	struct clk *clk;
59 	void __iomem *regs;
60 	struct cmdq_client_reg cmdq_reg;
61 };
62 
63 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
64 		   struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
65 		   unsigned int offset)
66 {
67 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
68 	if (cmdq_pkt)
69 		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
70 			       cmdq_reg->offset + offset, value);
71 	else
72 #endif
73 		writel(value, regs + offset);
74 }
75 
76 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
77 			   struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
78 			   unsigned int offset)
79 {
80 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
81 	if (cmdq_pkt)
82 		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
83 			       cmdq_reg->offset + offset, value);
84 	else
85 #endif
86 		writel_relaxed(value, regs + offset);
87 }
88 
89 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
90 			struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
91 			unsigned int offset, unsigned int mask)
92 {
93 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
94 	if (cmdq_pkt) {
95 		cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
96 				    cmdq_reg->offset + offset, value, mask);
97 	} else {
98 #endif
99 		u32 tmp = readl(regs + offset);
100 
101 		tmp = (tmp & ~mask) | (value & mask);
102 		writel(tmp, regs + offset);
103 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
104 	}
105 #endif
106 }
107 
108 static int mtk_ddp_clk_enable(struct device *dev)
109 {
110 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
111 
112 	return clk_prepare_enable(priv->clk);
113 }
114 
115 static void mtk_ddp_clk_disable(struct device *dev)
116 {
117 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
118 
119 	clk_disable_unprepare(priv->clk);
120 }
121 
122 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
123 			   unsigned int bpc, unsigned int cfg,
124 			   unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
125 {
126 	/* If bpc equal to 0, the dithering function didn't be enabled */
127 	if (bpc == 0)
128 		return;
129 
130 	if (bpc >= MTK_MIN_BPC) {
131 		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
132 		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
133 		mtk_ddp_write(cmdq_pkt,
134 			      DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
135 			      DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
136 			      DITHER_NEW_BIT_MODE,
137 			      cmdq_reg, regs, DISP_REG_DITHER_15);
138 		mtk_ddp_write(cmdq_pkt,
139 			      DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
140 			      DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
141 			      DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
142 			      DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
143 			      cmdq_reg, regs, DISP_REG_DITHER_16);
144 		mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
145 	}
146 }
147 
148 static void mtk_dither_config(struct device *dev, unsigned int w,
149 			      unsigned int h, unsigned int vrefresh,
150 			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
151 {
152 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
153 
154 	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
155 	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
156 		      DISP_REG_DITHER_CFG);
157 	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
158 			      DITHER_ENGINE_EN, cmdq_pkt);
159 }
160 
161 static void mtk_dither_start(struct device *dev)
162 {
163 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
164 
165 	writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
166 }
167 
168 static void mtk_dither_stop(struct device *dev)
169 {
170 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
171 
172 	writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
173 }
174 
175 static void mtk_dither_set(struct device *dev, unsigned int bpc,
176 			   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
177 {
178 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
179 
180 	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
181 			      DISP_DITHERING, cmdq_pkt);
182 }
183 
184 static void mtk_od_config(struct device *dev, unsigned int w,
185 			  unsigned int h, unsigned int vrefresh,
186 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
187 {
188 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
189 
190 	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
191 	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
192 	mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
193 }
194 
195 static void mtk_od_start(struct device *dev)
196 {
197 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
198 
199 	writel(1, priv->regs + DISP_REG_OD_EN);
200 }
201 
202 static void mtk_postmask_config(struct device *dev, unsigned int w,
203 				unsigned int h, unsigned int vrefresh,
204 				unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
205 {
206 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
207 
208 	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
209 		      DISP_REG_POSTMASK_SIZE);
210 	mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
211 		      priv->regs, DISP_REG_POSTMASK_CFG);
212 }
213 
214 static void mtk_postmask_start(struct device *dev)
215 {
216 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
217 
218 	writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
219 }
220 
221 static void mtk_postmask_stop(struct device *dev)
222 {
223 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
224 
225 	writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
226 }
227 
228 static void mtk_ufoe_start(struct device *dev)
229 {
230 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
231 
232 	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
233 }
234 
235 static const struct mtk_ddp_comp_funcs ddp_aal = {
236 	.clk_enable = mtk_aal_clk_enable,
237 	.clk_disable = mtk_aal_clk_disable,
238 	.gamma_set = mtk_aal_gamma_set,
239 	.config = mtk_aal_config,
240 	.start = mtk_aal_start,
241 	.stop = mtk_aal_stop,
242 };
243 
244 static const struct mtk_ddp_comp_funcs ddp_ccorr = {
245 	.clk_enable = mtk_ccorr_clk_enable,
246 	.clk_disable = mtk_ccorr_clk_disable,
247 	.config = mtk_ccorr_config,
248 	.start = mtk_ccorr_start,
249 	.stop = mtk_ccorr_stop,
250 	.ctm_set = mtk_ccorr_ctm_set,
251 };
252 
253 static const struct mtk_ddp_comp_funcs ddp_color = {
254 	.clk_enable = mtk_color_clk_enable,
255 	.clk_disable = mtk_color_clk_disable,
256 	.config = mtk_color_config,
257 	.start = mtk_color_start,
258 };
259 
260 static const struct mtk_ddp_comp_funcs ddp_dither = {
261 	.clk_enable = mtk_ddp_clk_enable,
262 	.clk_disable = mtk_ddp_clk_disable,
263 	.config = mtk_dither_config,
264 	.start = mtk_dither_start,
265 	.stop = mtk_dither_stop,
266 };
267 
268 static const struct mtk_ddp_comp_funcs ddp_dpi = {
269 	.start = mtk_dpi_start,
270 	.stop = mtk_dpi_stop,
271 };
272 
273 static const struct mtk_ddp_comp_funcs ddp_dsi = {
274 	.start = mtk_dsi_ddp_start,
275 	.stop = mtk_dsi_ddp_stop,
276 };
277 
278 static const struct mtk_ddp_comp_funcs ddp_gamma = {
279 	.clk_enable = mtk_gamma_clk_enable,
280 	.clk_disable = mtk_gamma_clk_disable,
281 	.gamma_set = mtk_gamma_set,
282 	.config = mtk_gamma_config,
283 	.start = mtk_gamma_start,
284 	.stop = mtk_gamma_stop,
285 };
286 
287 static const struct mtk_ddp_comp_funcs ddp_od = {
288 	.clk_enable = mtk_ddp_clk_enable,
289 	.clk_disable = mtk_ddp_clk_disable,
290 	.config = mtk_od_config,
291 	.start = mtk_od_start,
292 };
293 
294 static const struct mtk_ddp_comp_funcs ddp_ovl = {
295 	.clk_enable = mtk_ovl_clk_enable,
296 	.clk_disable = mtk_ovl_clk_disable,
297 	.config = mtk_ovl_config,
298 	.start = mtk_ovl_start,
299 	.stop = mtk_ovl_stop,
300 	.register_vblank_cb = mtk_ovl_register_vblank_cb,
301 	.unregister_vblank_cb = mtk_ovl_unregister_vblank_cb,
302 	.enable_vblank = mtk_ovl_enable_vblank,
303 	.disable_vblank = mtk_ovl_disable_vblank,
304 	.supported_rotations = mtk_ovl_supported_rotations,
305 	.layer_nr = mtk_ovl_layer_nr,
306 	.layer_check = mtk_ovl_layer_check,
307 	.layer_config = mtk_ovl_layer_config,
308 	.bgclr_in_on = mtk_ovl_bgclr_in_on,
309 	.bgclr_in_off = mtk_ovl_bgclr_in_off,
310 };
311 
312 static const struct mtk_ddp_comp_funcs ddp_postmask = {
313 	.clk_enable = mtk_ddp_clk_enable,
314 	.clk_disable = mtk_ddp_clk_disable,
315 	.config = mtk_postmask_config,
316 	.start = mtk_postmask_start,
317 	.stop = mtk_postmask_stop,
318 };
319 
320 static const struct mtk_ddp_comp_funcs ddp_rdma = {
321 	.clk_enable = mtk_rdma_clk_enable,
322 	.clk_disable = mtk_rdma_clk_disable,
323 	.config = mtk_rdma_config,
324 	.start = mtk_rdma_start,
325 	.stop = mtk_rdma_stop,
326 	.register_vblank_cb = mtk_rdma_register_vblank_cb,
327 	.unregister_vblank_cb = mtk_rdma_unregister_vblank_cb,
328 	.enable_vblank = mtk_rdma_enable_vblank,
329 	.disable_vblank = mtk_rdma_disable_vblank,
330 	.layer_nr = mtk_rdma_layer_nr,
331 	.layer_config = mtk_rdma_layer_config,
332 };
333 
334 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
335 	.clk_enable = mtk_ddp_clk_enable,
336 	.clk_disable = mtk_ddp_clk_disable,
337 	.start = mtk_ufoe_start,
338 };
339 
340 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
341 	[MTK_DISP_AAL] = "aal",
342 	[MTK_DISP_BLS] = "bls",
343 	[MTK_DISP_CCORR] = "ccorr",
344 	[MTK_DISP_COLOR] = "color",
345 	[MTK_DISP_DITHER] = "dither",
346 	[MTK_DISP_GAMMA] = "gamma",
347 	[MTK_DISP_MUTEX] = "mutex",
348 	[MTK_DISP_OD] = "od",
349 	[MTK_DISP_OVL] = "ovl",
350 	[MTK_DISP_OVL_2L] = "ovl-2l",
351 	[MTK_DISP_POSTMASK] = "postmask",
352 	[MTK_DISP_PWM] = "pwm",
353 	[MTK_DISP_RDMA] = "rdma",
354 	[MTK_DISP_UFOE] = "ufoe",
355 	[MTK_DISP_WDMA] = "wdma",
356 	[MTK_DPI] = "dpi",
357 	[MTK_DSI] = "dsi",
358 };
359 
360 struct mtk_ddp_comp_match {
361 	enum mtk_ddp_comp_type type;
362 	int alias_id;
363 	const struct mtk_ddp_comp_funcs *funcs;
364 };
365 
366 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
367 	[DDP_COMPONENT_AAL0]		= { MTK_DISP_AAL,	0, &ddp_aal },
368 	[DDP_COMPONENT_AAL1]		= { MTK_DISP_AAL,	1, &ddp_aal },
369 	[DDP_COMPONENT_BLS]		= { MTK_DISP_BLS,	0, NULL },
370 	[DDP_COMPONENT_CCORR]		= { MTK_DISP_CCORR,	0, &ddp_ccorr },
371 	[DDP_COMPONENT_COLOR0]		= { MTK_DISP_COLOR,	0, &ddp_color },
372 	[DDP_COMPONENT_COLOR1]		= { MTK_DISP_COLOR,	1, &ddp_color },
373 	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
374 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
375 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
376 	[DDP_COMPONENT_DSI0]		= { MTK_DSI,		0, &ddp_dsi },
377 	[DDP_COMPONENT_DSI1]		= { MTK_DSI,		1, &ddp_dsi },
378 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
379 	[DDP_COMPONENT_DSI3]		= { MTK_DSI,		3, &ddp_dsi },
380 	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,	0, &ddp_gamma },
381 	[DDP_COMPONENT_OD0]		= { MTK_DISP_OD,	0, &ddp_od },
382 	[DDP_COMPONENT_OD1]		= { MTK_DISP_OD,	1, &ddp_od },
383 	[DDP_COMPONENT_OVL0]		= { MTK_DISP_OVL,	0, &ddp_ovl },
384 	[DDP_COMPONENT_OVL1]		= { MTK_DISP_OVL,	1, &ddp_ovl },
385 	[DDP_COMPONENT_OVL_2L0]		= { MTK_DISP_OVL_2L,	0, &ddp_ovl },
386 	[DDP_COMPONENT_OVL_2L1]		= { MTK_DISP_OVL_2L,	1, &ddp_ovl },
387 	[DDP_COMPONENT_OVL_2L2]		= { MTK_DISP_OVL_2L,    2, &ddp_ovl },
388 	[DDP_COMPONENT_POSTMASK0]	= { MTK_DISP_POSTMASK,	0, &ddp_postmask },
389 	[DDP_COMPONENT_PWM0]		= { MTK_DISP_PWM,	0, NULL },
390 	[DDP_COMPONENT_PWM1]		= { MTK_DISP_PWM,	1, NULL },
391 	[DDP_COMPONENT_PWM2]		= { MTK_DISP_PWM,	2, NULL },
392 	[DDP_COMPONENT_RDMA0]		= { MTK_DISP_RDMA,	0, &ddp_rdma },
393 	[DDP_COMPONENT_RDMA1]		= { MTK_DISP_RDMA,	1, &ddp_rdma },
394 	[DDP_COMPONENT_RDMA2]		= { MTK_DISP_RDMA,	2, &ddp_rdma },
395 	[DDP_COMPONENT_RDMA4]		= { MTK_DISP_RDMA,      4, &ddp_rdma },
396 	[DDP_COMPONENT_UFOE]		= { MTK_DISP_UFOE,	0, &ddp_ufoe },
397 	[DDP_COMPONENT_WDMA0]		= { MTK_DISP_WDMA,	0, NULL },
398 	[DDP_COMPONENT_WDMA1]		= { MTK_DISP_WDMA,	1, NULL },
399 };
400 
401 static bool mtk_drm_find_comp_in_ddp(struct device *dev,
402 				     const enum mtk_ddp_comp_id *path,
403 				     unsigned int path_len,
404 				     struct mtk_ddp_comp *ddp_comp)
405 {
406 	unsigned int i;
407 
408 	if (path == NULL)
409 		return false;
410 
411 	for (i = 0U; i < path_len; i++)
412 		if (dev == ddp_comp[path[i]].dev)
413 			return true;
414 
415 	return false;
416 }
417 
418 int mtk_ddp_comp_get_id(struct device_node *node,
419 			enum mtk_ddp_comp_type comp_type)
420 {
421 	int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
422 	int i;
423 
424 	for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
425 		if (comp_type == mtk_ddp_matches[i].type &&
426 		    (id < 0 || id == mtk_ddp_matches[i].alias_id))
427 			return i;
428 	}
429 
430 	return -EINVAL;
431 }
432 
433 unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
434 						struct device *dev)
435 {
436 	struct mtk_drm_private *private = drm->dev_private;
437 	unsigned int ret = 0;
438 
439 	if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len,
440 				     private->ddp_comp))
441 		ret = BIT(0);
442 	else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
443 					  private->data->ext_len, private->ddp_comp))
444 		ret = BIT(1);
445 	else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
446 					  private->data->third_len, private->ddp_comp))
447 		ret = BIT(2);
448 	else
449 		DRM_INFO("Failed to find comp in ddp table\n");
450 
451 	return ret;
452 }
453 
454 int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
455 		      enum mtk_ddp_comp_id comp_id)
456 {
457 	struct platform_device *comp_pdev;
458 	enum mtk_ddp_comp_type type;
459 	struct mtk_ddp_comp_dev *priv;
460 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
461 	int ret;
462 #endif
463 
464 	if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
465 		return -EINVAL;
466 
467 	type = mtk_ddp_matches[comp_id].type;
468 
469 	comp->id = comp_id;
470 	comp->funcs = mtk_ddp_matches[comp_id].funcs;
471 	comp_pdev = of_find_device_by_node(node);
472 	if (!comp_pdev) {
473 		DRM_INFO("Waiting for device %s\n", node->full_name);
474 		return -EPROBE_DEFER;
475 	}
476 	comp->dev = &comp_pdev->dev;
477 
478 	if (type == MTK_DISP_AAL ||
479 	    type == MTK_DISP_BLS ||
480 	    type == MTK_DISP_CCORR ||
481 	    type == MTK_DISP_COLOR ||
482 	    type == MTK_DISP_GAMMA ||
483 	    type == MTK_DISP_OVL ||
484 	    type == MTK_DISP_OVL_2L ||
485 	    type == MTK_DISP_PWM ||
486 	    type == MTK_DISP_RDMA ||
487 	    type == MTK_DPI ||
488 	    type == MTK_DSI)
489 		return 0;
490 
491 	priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
492 	if (!priv)
493 		return -ENOMEM;
494 
495 	priv->regs = of_iomap(node, 0);
496 	priv->clk = of_clk_get(node, 0);
497 	if (IS_ERR(priv->clk))
498 		return PTR_ERR(priv->clk);
499 
500 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
501 	ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
502 	if (ret)
503 		dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
504 #endif
505 
506 	platform_set_drvdata(comp_pdev, priv);
507 
508 	return 0;
509 }
510