1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Authors: 5 * YT Shen <yt.shen@mediatek.com> 6 * CK Hu <ck.hu@mediatek.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_irq.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 16 #include "mtk_drm_drv.h" 17 #include "mtk_drm_plane.h" 18 #include "mtk_drm_ddp_comp.h" 19 #include "mtk_drm_crtc.h" 20 21 #define DISP_OD_EN 0x0000 22 #define DISP_OD_INTEN 0x0008 23 #define DISP_OD_INTSTA 0x000c 24 #define DISP_OD_CFG 0x0020 25 #define DISP_OD_SIZE 0x0030 26 #define DISP_DITHER_5 0x0114 27 #define DISP_DITHER_7 0x011c 28 #define DISP_DITHER_15 0x013c 29 #define DISP_DITHER_16 0x0140 30 31 #define DISP_REG_UFO_START 0x0000 32 33 #define DISP_AAL_EN 0x0000 34 #define DISP_AAL_SIZE 0x0030 35 36 #define DISP_GAMMA_EN 0x0000 37 #define DISP_GAMMA_CFG 0x0020 38 #define DISP_GAMMA_SIZE 0x0030 39 #define DISP_GAMMA_LUT 0x0700 40 41 #define LUT_10BIT_MASK 0x03ff 42 43 #define OD_RELAYMODE BIT(0) 44 45 #define UFO_BYPASS BIT(2) 46 47 #define AAL_EN BIT(0) 48 49 #define GAMMA_EN BIT(0) 50 #define GAMMA_LUT_EN BIT(1) 51 52 #define DISP_DITHERING BIT(2) 53 #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) 54 #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) 55 #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20) 56 #define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16) 57 #define DITHER_NEW_BIT_MODE BIT(0) 58 #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28) 59 #define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24) 60 #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20) 61 #define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16) 62 #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) 63 #define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8) 64 #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) 65 #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0) 66 67 void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, 68 unsigned int CFG) 69 { 70 /* If bpc equal to 0, the dithering function didn't be enabled */ 71 if (bpc == 0) 72 return; 73 74 if (bpc >= MTK_MIN_BPC) { 75 writel(0, comp->regs + DISP_DITHER_5); 76 writel(0, comp->regs + DISP_DITHER_7); 77 writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | 78 DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | 79 DITHER_NEW_BIT_MODE, 80 comp->regs + DISP_DITHER_15); 81 writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | 82 DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | 83 DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | 84 DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), 85 comp->regs + DISP_DITHER_16); 86 writel(DISP_DITHERING, comp->regs + CFG); 87 } 88 } 89 90 static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, 91 unsigned int h, unsigned int vrefresh, 92 unsigned int bpc) 93 { 94 writel(w << 16 | h, comp->regs + DISP_OD_SIZE); 95 writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG); 96 mtk_dither_set(comp, bpc, DISP_OD_CFG); 97 } 98 99 static void mtk_od_start(struct mtk_ddp_comp *comp) 100 { 101 writel(1, comp->regs + DISP_OD_EN); 102 } 103 104 static void mtk_ufoe_start(struct mtk_ddp_comp *comp) 105 { 106 writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START); 107 } 108 109 static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, 110 unsigned int h, unsigned int vrefresh, 111 unsigned int bpc) 112 { 113 writel(h << 16 | w, comp->regs + DISP_AAL_SIZE); 114 } 115 116 static void mtk_aal_start(struct mtk_ddp_comp *comp) 117 { 118 writel(AAL_EN, comp->regs + DISP_AAL_EN); 119 } 120 121 static void mtk_aal_stop(struct mtk_ddp_comp *comp) 122 { 123 writel_relaxed(0x0, comp->regs + DISP_AAL_EN); 124 } 125 126 static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, 127 unsigned int h, unsigned int vrefresh, 128 unsigned int bpc) 129 { 130 writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE); 131 mtk_dither_set(comp, bpc, DISP_GAMMA_CFG); 132 } 133 134 static void mtk_gamma_start(struct mtk_ddp_comp *comp) 135 { 136 writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN); 137 } 138 139 static void mtk_gamma_stop(struct mtk_ddp_comp *comp) 140 { 141 writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN); 142 } 143 144 static void mtk_gamma_set(struct mtk_ddp_comp *comp, 145 struct drm_crtc_state *state) 146 { 147 unsigned int i, reg; 148 struct drm_color_lut *lut; 149 void __iomem *lut_base; 150 u32 word; 151 152 if (state->gamma_lut) { 153 reg = readl(comp->regs + DISP_GAMMA_CFG); 154 reg = reg | GAMMA_LUT_EN; 155 writel(reg, comp->regs + DISP_GAMMA_CFG); 156 lut_base = comp->regs + DISP_GAMMA_LUT; 157 lut = (struct drm_color_lut *)state->gamma_lut->data; 158 for (i = 0; i < MTK_LUT_SIZE; i++) { 159 word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + 160 (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + 161 ((lut[i].blue >> 6) & LUT_10BIT_MASK); 162 writel(word, (lut_base + i * 4)); 163 } 164 } 165 } 166 167 static const struct mtk_ddp_comp_funcs ddp_aal = { 168 .gamma_set = mtk_gamma_set, 169 .config = mtk_aal_config, 170 .start = mtk_aal_start, 171 .stop = mtk_aal_stop, 172 }; 173 174 static const struct mtk_ddp_comp_funcs ddp_gamma = { 175 .gamma_set = mtk_gamma_set, 176 .config = mtk_gamma_config, 177 .start = mtk_gamma_start, 178 .stop = mtk_gamma_stop, 179 }; 180 181 static const struct mtk_ddp_comp_funcs ddp_od = { 182 .config = mtk_od_config, 183 .start = mtk_od_start, 184 }; 185 186 static const struct mtk_ddp_comp_funcs ddp_ufoe = { 187 .start = mtk_ufoe_start, 188 }; 189 190 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { 191 [MTK_DISP_OVL] = "ovl", 192 [MTK_DISP_RDMA] = "rdma", 193 [MTK_DISP_WDMA] = "wdma", 194 [MTK_DISP_COLOR] = "color", 195 [MTK_DISP_AAL] = "aal", 196 [MTK_DISP_GAMMA] = "gamma", 197 [MTK_DISP_UFOE] = "ufoe", 198 [MTK_DSI] = "dsi", 199 [MTK_DPI] = "dpi", 200 [MTK_DISP_PWM] = "pwm", 201 [MTK_DISP_MUTEX] = "mutex", 202 [MTK_DISP_OD] = "od", 203 [MTK_DISP_BLS] = "bls", 204 }; 205 206 struct mtk_ddp_comp_match { 207 enum mtk_ddp_comp_type type; 208 int alias_id; 209 const struct mtk_ddp_comp_funcs *funcs; 210 }; 211 212 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { 213 [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, 214 [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, 215 [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, 216 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, 217 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, 218 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, 219 [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL }, 220 [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, 221 [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, 222 [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL }, 223 [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL }, 224 [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, 225 [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, 226 [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, 227 [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, 228 [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, 229 [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, 230 [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, 231 [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, 232 [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, 233 [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, 234 [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, 235 [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, 236 [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, 237 [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, 238 }; 239 240 int mtk_ddp_comp_get_id(struct device_node *node, 241 enum mtk_ddp_comp_type comp_type) 242 { 243 int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]); 244 int i; 245 246 for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) { 247 if (comp_type == mtk_ddp_matches[i].type && 248 (id < 0 || id == mtk_ddp_matches[i].alias_id)) 249 return i; 250 } 251 252 return -EINVAL; 253 } 254 255 int mtk_ddp_comp_init(struct device *dev, struct device_node *node, 256 struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, 257 const struct mtk_ddp_comp_funcs *funcs) 258 { 259 enum mtk_ddp_comp_type type; 260 struct device_node *larb_node; 261 struct platform_device *larb_pdev; 262 263 if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) 264 return -EINVAL; 265 266 type = mtk_ddp_matches[comp_id].type; 267 268 comp->id = comp_id; 269 comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs; 270 271 if (comp_id == DDP_COMPONENT_BLS || 272 comp_id == DDP_COMPONENT_DPI0 || 273 comp_id == DDP_COMPONENT_DPI1 || 274 comp_id == DDP_COMPONENT_DSI0 || 275 comp_id == DDP_COMPONENT_DSI1 || 276 comp_id == DDP_COMPONENT_DSI2 || 277 comp_id == DDP_COMPONENT_DSI3 || 278 comp_id == DDP_COMPONENT_PWM0) { 279 comp->regs = NULL; 280 comp->clk = NULL; 281 comp->irq = 0; 282 return 0; 283 } 284 285 comp->regs = of_iomap(node, 0); 286 comp->irq = of_irq_get(node, 0); 287 comp->clk = of_clk_get(node, 0); 288 if (IS_ERR(comp->clk)) 289 return PTR_ERR(comp->clk); 290 291 /* Only DMA capable components need the LARB property */ 292 comp->larb_dev = NULL; 293 if (type != MTK_DISP_OVL && 294 type != MTK_DISP_RDMA && 295 type != MTK_DISP_WDMA) 296 return 0; 297 298 larb_node = of_parse_phandle(node, "mediatek,larb", 0); 299 if (!larb_node) { 300 dev_err(dev, 301 "Missing mediadek,larb phandle in %pOF node\n", node); 302 return -EINVAL; 303 } 304 305 larb_pdev = of_find_device_by_node(larb_node); 306 if (!larb_pdev) { 307 dev_warn(dev, "Waiting for larb device %pOF\n", larb_node); 308 of_node_put(larb_node); 309 return -EPROBE_DEFER; 310 } 311 of_node_put(larb_node); 312 313 comp->larb_dev = &larb_pdev->dev; 314 315 return 0; 316 } 317 318 int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp) 319 { 320 struct mtk_drm_private *private = drm->dev_private; 321 322 if (private->ddp_comp[comp->id]) 323 return -EBUSY; 324 325 private->ddp_comp[comp->id] = comp; 326 return 0; 327 } 328 329 void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp) 330 { 331 struct mtk_drm_private *private = drm->dev_private; 332 333 private->ddp_comp[comp->id] = NULL; 334 } 335