1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Authors: 5 * YT Shen <yt.shen@mediatek.com> 6 * CK Hu <ck.hu@mediatek.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_irq.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/soc/mediatek/mtk-cmdq.h> 16 #include "mtk_drm_drv.h" 17 #include "mtk_drm_plane.h" 18 #include "mtk_drm_ddp_comp.h" 19 #include "mtk_drm_crtc.h" 20 21 #define DISP_OD_EN 0x0000 22 #define DISP_OD_INTEN 0x0008 23 #define DISP_OD_INTSTA 0x000c 24 #define DISP_OD_CFG 0x0020 25 #define DISP_OD_SIZE 0x0030 26 #define DISP_DITHER_5 0x0114 27 #define DISP_DITHER_7 0x011c 28 #define DISP_DITHER_15 0x013c 29 #define DISP_DITHER_16 0x0140 30 31 #define DISP_REG_UFO_START 0x0000 32 33 #define DISP_AAL_EN 0x0000 34 #define DISP_AAL_SIZE 0x0030 35 36 #define DISP_CCORR_EN 0x0000 37 #define CCORR_EN BIT(0) 38 #define DISP_CCORR_CFG 0x0020 39 #define CCORR_RELAY_MODE BIT(0) 40 #define CCORR_ENGINE_EN BIT(1) 41 #define CCORR_GAMMA_OFF BIT(2) 42 #define CCORR_WGAMUT_SRC_CLIP BIT(3) 43 #define DISP_CCORR_SIZE 0x0030 44 #define DISP_CCORR_COEF_0 0x0080 45 #define DISP_CCORR_COEF_1 0x0084 46 #define DISP_CCORR_COEF_2 0x0088 47 #define DISP_CCORR_COEF_3 0x008C 48 #define DISP_CCORR_COEF_4 0x0090 49 50 #define DISP_DITHER_EN 0x0000 51 #define DITHER_EN BIT(0) 52 #define DISP_DITHER_CFG 0x0020 53 #define DITHER_RELAY_MODE BIT(0) 54 #define DISP_DITHER_SIZE 0x0030 55 56 #define DISP_GAMMA_EN 0x0000 57 #define DISP_GAMMA_CFG 0x0020 58 #define DISP_GAMMA_SIZE 0x0030 59 #define DISP_GAMMA_LUT 0x0700 60 61 #define LUT_10BIT_MASK 0x03ff 62 63 #define OD_RELAYMODE BIT(0) 64 65 #define UFO_BYPASS BIT(2) 66 67 #define AAL_EN BIT(0) 68 69 #define GAMMA_EN BIT(0) 70 #define GAMMA_LUT_EN BIT(1) 71 72 #define DISP_DITHERING BIT(2) 73 #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) 74 #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) 75 #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20) 76 #define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16) 77 #define DITHER_NEW_BIT_MODE BIT(0) 78 #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28) 79 #define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24) 80 #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20) 81 #define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16) 82 #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) 83 #define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8) 84 #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) 85 #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0) 86 87 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, 88 struct mtk_ddp_comp *comp, unsigned int offset) 89 { 90 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 91 if (cmdq_pkt) 92 cmdq_pkt_write(cmdq_pkt, comp->subsys, 93 comp->regs_pa + offset, value); 94 else 95 #endif 96 writel(value, comp->regs + offset); 97 } 98 99 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, 100 struct mtk_ddp_comp *comp, 101 unsigned int offset) 102 { 103 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 104 if (cmdq_pkt) 105 cmdq_pkt_write(cmdq_pkt, comp->subsys, 106 comp->regs_pa + offset, value); 107 else 108 #endif 109 writel_relaxed(value, comp->regs + offset); 110 } 111 112 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, 113 unsigned int value, 114 struct mtk_ddp_comp *comp, 115 unsigned int offset, 116 unsigned int mask) 117 { 118 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 119 if (cmdq_pkt) { 120 cmdq_pkt_write_mask(cmdq_pkt, comp->subsys, 121 comp->regs_pa + offset, value, mask); 122 } else { 123 #endif 124 u32 tmp = readl(comp->regs + offset); 125 126 tmp = (tmp & ~mask) | (value & mask); 127 writel(tmp, comp->regs + offset); 128 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 129 } 130 #endif 131 } 132 133 void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, 134 unsigned int CFG, struct cmdq_pkt *cmdq_pkt) 135 { 136 /* If bpc equal to 0, the dithering function didn't be enabled */ 137 if (bpc == 0) 138 return; 139 140 if (bpc >= MTK_MIN_BPC) { 141 mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); 142 mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); 143 mtk_ddp_write(cmdq_pkt, 144 DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | 145 DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | 146 DITHER_NEW_BIT_MODE, 147 comp, DISP_DITHER_15); 148 mtk_ddp_write(cmdq_pkt, 149 DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | 150 DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | 151 DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | 152 DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), 153 comp, DISP_DITHER_16); 154 mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); 155 } 156 } 157 158 static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, 159 unsigned int h, unsigned int vrefresh, 160 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 161 { 162 mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE); 163 mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG); 164 mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt); 165 } 166 167 static void mtk_od_start(struct mtk_ddp_comp *comp) 168 { 169 writel(1, comp->regs + DISP_OD_EN); 170 } 171 172 static void mtk_ufoe_start(struct mtk_ddp_comp *comp) 173 { 174 writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START); 175 } 176 177 static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, 178 unsigned int h, unsigned int vrefresh, 179 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 180 { 181 mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE); 182 } 183 184 static void mtk_aal_start(struct mtk_ddp_comp *comp) 185 { 186 writel(AAL_EN, comp->regs + DISP_AAL_EN); 187 } 188 189 static void mtk_aal_stop(struct mtk_ddp_comp *comp) 190 { 191 writel_relaxed(0x0, comp->regs + DISP_AAL_EN); 192 } 193 194 static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, 195 unsigned int h, unsigned int vrefresh, 196 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 197 { 198 mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE); 199 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG); 200 } 201 202 static void mtk_ccorr_start(struct mtk_ddp_comp *comp) 203 { 204 writel(CCORR_EN, comp->regs + DISP_CCORR_EN); 205 } 206 207 static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) 208 { 209 writel_relaxed(0x0, comp->regs + DISP_CCORR_EN); 210 } 211 212 /* Converts a DRM S31.32 value to the HW S1.10 format. */ 213 static u16 mtk_ctm_s31_32_to_s1_10(u64 in) 214 { 215 u16 r; 216 217 /* Sign bit. */ 218 r = in & BIT_ULL(63) ? BIT(11) : 0; 219 220 if ((in & GENMASK_ULL(62, 33)) > 0) { 221 /* identity value 0x100000000 -> 0x400, */ 222 /* if bigger this, set it to max 0x7ff. */ 223 r |= GENMASK(10, 0); 224 } else { 225 /* take the 11 most important bits. */ 226 r |= (in >> 22) & GENMASK(10, 0); 227 } 228 229 return r; 230 } 231 232 static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, 233 struct drm_crtc_state *state) 234 { 235 struct drm_property_blob *blob = state->ctm; 236 struct drm_color_ctm *ctm; 237 const u64 *input; 238 uint16_t coeffs[9] = { 0 }; 239 int i; 240 struct cmdq_pkt *cmdq_pkt = NULL; 241 242 if (!blob) 243 return; 244 245 ctm = (struct drm_color_ctm *)blob->data; 246 input = ctm->matrix; 247 248 for (i = 0; i < ARRAY_SIZE(coeffs); i++) 249 coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); 250 251 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], 252 comp, DISP_CCORR_COEF_0); 253 mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], 254 comp, DISP_CCORR_COEF_1); 255 mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], 256 comp, DISP_CCORR_COEF_2); 257 mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], 258 comp, DISP_CCORR_COEF_3); 259 mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, 260 comp, DISP_CCORR_COEF_4); 261 } 262 263 static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, 264 unsigned int h, unsigned int vrefresh, 265 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 266 { 267 mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE); 268 mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG); 269 } 270 271 static void mtk_dither_start(struct mtk_ddp_comp *comp) 272 { 273 writel(DITHER_EN, comp->regs + DISP_DITHER_EN); 274 } 275 276 static void mtk_dither_stop(struct mtk_ddp_comp *comp) 277 { 278 writel_relaxed(0x0, comp->regs + DISP_DITHER_EN); 279 } 280 281 static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, 282 unsigned int h, unsigned int vrefresh, 283 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 284 { 285 mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE); 286 mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt); 287 } 288 289 static void mtk_gamma_start(struct mtk_ddp_comp *comp) 290 { 291 writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN); 292 } 293 294 static void mtk_gamma_stop(struct mtk_ddp_comp *comp) 295 { 296 writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN); 297 } 298 299 static void mtk_gamma_set(struct mtk_ddp_comp *comp, 300 struct drm_crtc_state *state) 301 { 302 unsigned int i, reg; 303 struct drm_color_lut *lut; 304 void __iomem *lut_base; 305 u32 word; 306 307 if (state->gamma_lut) { 308 reg = readl(comp->regs + DISP_GAMMA_CFG); 309 reg = reg | GAMMA_LUT_EN; 310 writel(reg, comp->regs + DISP_GAMMA_CFG); 311 lut_base = comp->regs + DISP_GAMMA_LUT; 312 lut = (struct drm_color_lut *)state->gamma_lut->data; 313 for (i = 0; i < MTK_LUT_SIZE; i++) { 314 word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + 315 (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + 316 ((lut[i].blue >> 6) & LUT_10BIT_MASK); 317 writel(word, (lut_base + i * 4)); 318 } 319 } 320 } 321 322 static const struct mtk_ddp_comp_funcs ddp_aal = { 323 .gamma_set = mtk_gamma_set, 324 .config = mtk_aal_config, 325 .start = mtk_aal_start, 326 .stop = mtk_aal_stop, 327 }; 328 329 static const struct mtk_ddp_comp_funcs ddp_ccorr = { 330 .config = mtk_ccorr_config, 331 .start = mtk_ccorr_start, 332 .stop = mtk_ccorr_stop, 333 .ctm_set = mtk_ccorr_ctm_set, 334 }; 335 336 static const struct mtk_ddp_comp_funcs ddp_dither = { 337 .config = mtk_dither_config, 338 .start = mtk_dither_start, 339 .stop = mtk_dither_stop, 340 }; 341 342 static const struct mtk_ddp_comp_funcs ddp_gamma = { 343 .gamma_set = mtk_gamma_set, 344 .config = mtk_gamma_config, 345 .start = mtk_gamma_start, 346 .stop = mtk_gamma_stop, 347 }; 348 349 static const struct mtk_ddp_comp_funcs ddp_od = { 350 .config = mtk_od_config, 351 .start = mtk_od_start, 352 }; 353 354 static const struct mtk_ddp_comp_funcs ddp_ufoe = { 355 .start = mtk_ufoe_start, 356 }; 357 358 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { 359 [MTK_DISP_OVL] = "ovl", 360 [MTK_DISP_OVL_2L] = "ovl_2l", 361 [MTK_DISP_RDMA] = "rdma", 362 [MTK_DISP_WDMA] = "wdma", 363 [MTK_DISP_COLOR] = "color", 364 [MTK_DISP_CCORR] = "ccorr", 365 [MTK_DISP_AAL] = "aal", 366 [MTK_DISP_GAMMA] = "gamma", 367 [MTK_DISP_DITHER] = "dither", 368 [MTK_DISP_UFOE] = "ufoe", 369 [MTK_DSI] = "dsi", 370 [MTK_DPI] = "dpi", 371 [MTK_DISP_PWM] = "pwm", 372 [MTK_DISP_MUTEX] = "mutex", 373 [MTK_DISP_OD] = "od", 374 [MTK_DISP_BLS] = "bls", 375 }; 376 377 struct mtk_ddp_comp_match { 378 enum mtk_ddp_comp_type type; 379 int alias_id; 380 const struct mtk_ddp_comp_funcs *funcs; 381 }; 382 383 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { 384 [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, 385 [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, 386 [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, 387 [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, 388 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, 389 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, 390 [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, 391 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, 392 [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL }, 393 [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, 394 [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, 395 [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL }, 396 [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL }, 397 [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, 398 [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, 399 [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, 400 [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, 401 [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, 402 [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL }, 403 [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL }, 404 [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, 405 [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, 406 [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, 407 [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, 408 [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, 409 [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, 410 [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, 411 [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, 412 [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, 413 }; 414 415 int mtk_ddp_comp_get_id(struct device_node *node, 416 enum mtk_ddp_comp_type comp_type) 417 { 418 int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]); 419 int i; 420 421 for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) { 422 if (comp_type == mtk_ddp_matches[i].type && 423 (id < 0 || id == mtk_ddp_matches[i].alias_id)) 424 return i; 425 } 426 427 return -EINVAL; 428 } 429 430 int mtk_ddp_comp_init(struct device *dev, struct device_node *node, 431 struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, 432 const struct mtk_ddp_comp_funcs *funcs) 433 { 434 enum mtk_ddp_comp_type type; 435 struct device_node *larb_node; 436 struct platform_device *larb_pdev; 437 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 438 struct resource res; 439 struct cmdq_client_reg cmdq_reg; 440 int ret; 441 #endif 442 443 if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) 444 return -EINVAL; 445 446 type = mtk_ddp_matches[comp_id].type; 447 448 comp->id = comp_id; 449 comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs; 450 451 if (comp_id == DDP_COMPONENT_BLS || 452 comp_id == DDP_COMPONENT_DPI0 || 453 comp_id == DDP_COMPONENT_DPI1 || 454 comp_id == DDP_COMPONENT_DSI0 || 455 comp_id == DDP_COMPONENT_DSI1 || 456 comp_id == DDP_COMPONENT_DSI2 || 457 comp_id == DDP_COMPONENT_DSI3 || 458 comp_id == DDP_COMPONENT_PWM0) { 459 comp->regs = NULL; 460 comp->clk = NULL; 461 comp->irq = 0; 462 return 0; 463 } 464 465 comp->regs = of_iomap(node, 0); 466 comp->irq = of_irq_get(node, 0); 467 comp->clk = of_clk_get(node, 0); 468 if (IS_ERR(comp->clk)) 469 return PTR_ERR(comp->clk); 470 471 /* Only DMA capable components need the LARB property */ 472 comp->larb_dev = NULL; 473 if (type != MTK_DISP_OVL && 474 type != MTK_DISP_RDMA && 475 type != MTK_DISP_WDMA) 476 return 0; 477 478 larb_node = of_parse_phandle(node, "mediatek,larb", 0); 479 if (!larb_node) { 480 dev_err(dev, 481 "Missing mediadek,larb phandle in %pOF node\n", node); 482 return -EINVAL; 483 } 484 485 larb_pdev = of_find_device_by_node(larb_node); 486 if (!larb_pdev) { 487 dev_warn(dev, "Waiting for larb device %pOF\n", larb_node); 488 of_node_put(larb_node); 489 return -EPROBE_DEFER; 490 } 491 of_node_put(larb_node); 492 493 comp->larb_dev = &larb_pdev->dev; 494 495 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 496 if (of_address_to_resource(node, 0, &res) != 0) { 497 dev_err(dev, "Missing reg in %s node\n", node->full_name); 498 return -EINVAL; 499 } 500 comp->regs_pa = res.start; 501 502 ret = cmdq_dev_get_client_reg(dev, &cmdq_reg, 0); 503 if (ret) 504 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); 505 else 506 comp->subsys = cmdq_reg.subsys; 507 #endif 508 return 0; 509 } 510 511 int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp) 512 { 513 struct mtk_drm_private *private = drm->dev_private; 514 515 if (private->ddp_comp[comp->id]) 516 return -EBUSY; 517 518 private->ddp_comp[comp->id] = comp; 519 return 0; 520 } 521 522 void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp) 523 { 524 struct mtk_drm_private *private = drm->dev_private; 525 526 private->ddp_comp[comp->id] = NULL; 527 } 528