1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Authors: 5 * YT Shen <yt.shen@mediatek.com> 6 * CK Hu <ck.hu@mediatek.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/soc/mediatek/mtk-cmdq.h> 15 #include <drm/drm_print.h> 16 17 #include "mtk_disp_drv.h" 18 #include "mtk_drm_drv.h" 19 #include "mtk_drm_plane.h" 20 #include "mtk_drm_ddp_comp.h" 21 #include "mtk_drm_crtc.h" 22 23 24 #define DISP_REG_DITHER_EN 0x0000 25 #define DITHER_EN BIT(0) 26 #define DISP_REG_DITHER_CFG 0x0020 27 #define DITHER_RELAY_MODE BIT(0) 28 #define DITHER_ENGINE_EN BIT(1) 29 #define DISP_DITHERING BIT(2) 30 #define DISP_REG_DITHER_SIZE 0x0030 31 #define DISP_REG_DITHER_5 0x0114 32 #define DISP_REG_DITHER_7 0x011c 33 #define DISP_REG_DITHER_15 0x013c 34 #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) 35 #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20) 36 #define DITHER_NEW_BIT_MODE BIT(0) 37 #define DISP_REG_DITHER_16 0x0140 38 #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28) 39 #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20) 40 #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) 41 #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) 42 43 #define DISP_REG_DSC_CON 0x0000 44 #define DSC_EN BIT(0) 45 #define DSC_DUAL_INOUT BIT(2) 46 #define DSC_BYPASS BIT(4) 47 #define DSC_UFOE_SEL BIT(16) 48 49 #define DISP_REG_OD_EN 0x0000 50 #define DISP_REG_OD_CFG 0x0020 51 #define OD_RELAYMODE BIT(0) 52 #define DISP_REG_OD_SIZE 0x0030 53 54 #define DISP_REG_POSTMASK_EN 0x0000 55 #define POSTMASK_EN BIT(0) 56 #define DISP_REG_POSTMASK_CFG 0x0020 57 #define POSTMASK_RELAY_MODE BIT(0) 58 #define DISP_REG_POSTMASK_SIZE 0x0030 59 60 #define DISP_REG_UFO_START 0x0000 61 #define UFO_BYPASS BIT(2) 62 63 struct mtk_ddp_comp_dev { 64 struct clk *clk; 65 void __iomem *regs; 66 struct cmdq_client_reg cmdq_reg; 67 }; 68 69 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, 70 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, 71 unsigned int offset) 72 { 73 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 74 if (cmdq_pkt) 75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, 76 cmdq_reg->offset + offset, value); 77 else 78 #endif 79 writel(value, regs + offset); 80 } 81 82 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, 83 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, 84 unsigned int offset) 85 { 86 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 87 if (cmdq_pkt) 88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, 89 cmdq_reg->offset + offset, value); 90 else 91 #endif 92 writel_relaxed(value, regs + offset); 93 } 94 95 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, 96 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, 97 unsigned int offset, unsigned int mask) 98 { 99 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 100 if (cmdq_pkt) { 101 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, 102 cmdq_reg->offset + offset, value, mask); 103 } else { 104 #endif 105 u32 tmp = readl(regs + offset); 106 107 tmp = (tmp & ~mask) | (value & mask); 108 writel(tmp, regs + offset); 109 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 110 } 111 #endif 112 } 113 114 static int mtk_ddp_clk_enable(struct device *dev) 115 { 116 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 117 118 return clk_prepare_enable(priv->clk); 119 } 120 121 static void mtk_ddp_clk_disable(struct device *dev) 122 { 123 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 124 125 clk_disable_unprepare(priv->clk); 126 } 127 128 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, 129 unsigned int bpc, unsigned int cfg, 130 unsigned int dither_en, struct cmdq_pkt *cmdq_pkt) 131 { 132 /* If bpc equal to 0, the dithering function didn't be enabled */ 133 if (bpc == 0) 134 return; 135 136 if (bpc >= MTK_MIN_BPC) { 137 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5); 138 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7); 139 mtk_ddp_write(cmdq_pkt, 140 DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | 141 DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | 142 DITHER_NEW_BIT_MODE, 143 cmdq_reg, regs, DISP_REG_DITHER_15); 144 mtk_ddp_write(cmdq_pkt, 145 DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | 146 DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | 147 DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | 148 DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), 149 cmdq_reg, regs, DISP_REG_DITHER_16); 150 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg); 151 } 152 } 153 154 static void mtk_dither_config(struct device *dev, unsigned int w, 155 unsigned int h, unsigned int vrefresh, 156 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 157 { 158 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 159 160 mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE); 161 mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, 162 DISP_REG_DITHER_CFG); 163 mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG, 164 DITHER_ENGINE_EN, cmdq_pkt); 165 } 166 167 static void mtk_dither_start(struct device *dev) 168 { 169 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 170 171 writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN); 172 } 173 174 static void mtk_dither_stop(struct device *dev) 175 { 176 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 177 178 writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN); 179 } 180 181 static void mtk_dither_set(struct device *dev, unsigned int bpc, 182 unsigned int cfg, struct cmdq_pkt *cmdq_pkt) 183 { 184 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 185 186 mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg, 187 DISP_DITHERING, cmdq_pkt); 188 } 189 190 static void mtk_dsc_config(struct device *dev, unsigned int w, 191 unsigned int h, unsigned int vrefresh, 192 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 193 { 194 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 195 196 /* dsc bypass mode */ 197 mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs, 198 DISP_REG_DSC_CON, DSC_BYPASS); 199 mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs, 200 DISP_REG_DSC_CON, DSC_UFOE_SEL); 201 mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs, 202 DISP_REG_DSC_CON, DSC_DUAL_INOUT); 203 } 204 205 static void mtk_dsc_start(struct device *dev) 206 { 207 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 208 209 /* write with mask to reserve the value set in mtk_dsc_config */ 210 mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN); 211 } 212 213 static void mtk_dsc_stop(struct device *dev) 214 { 215 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 216 217 writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON); 218 } 219 220 static void mtk_od_config(struct device *dev, unsigned int w, 221 unsigned int h, unsigned int vrefresh, 222 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 223 { 224 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 225 226 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE); 227 mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG); 228 mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt); 229 } 230 231 static void mtk_od_start(struct device *dev) 232 { 233 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 234 235 writel(1, priv->regs + DISP_REG_OD_EN); 236 } 237 238 static void mtk_postmask_config(struct device *dev, unsigned int w, 239 unsigned int h, unsigned int vrefresh, 240 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 241 { 242 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 243 244 mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, 245 DISP_REG_POSTMASK_SIZE); 246 mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, 247 priv->regs, DISP_REG_POSTMASK_CFG); 248 } 249 250 static void mtk_postmask_start(struct device *dev) 251 { 252 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 253 254 writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN); 255 } 256 257 static void mtk_postmask_stop(struct device *dev) 258 { 259 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 260 261 writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN); 262 } 263 264 static void mtk_ufoe_start(struct device *dev) 265 { 266 struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); 267 268 writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); 269 } 270 271 static const struct mtk_ddp_comp_funcs ddp_aal = { 272 .clk_enable = mtk_aal_clk_enable, 273 .clk_disable = mtk_aal_clk_disable, 274 .gamma_set = mtk_aal_gamma_set, 275 .config = mtk_aal_config, 276 .start = mtk_aal_start, 277 .stop = mtk_aal_stop, 278 }; 279 280 static const struct mtk_ddp_comp_funcs ddp_ccorr = { 281 .clk_enable = mtk_ccorr_clk_enable, 282 .clk_disable = mtk_ccorr_clk_disable, 283 .config = mtk_ccorr_config, 284 .start = mtk_ccorr_start, 285 .stop = mtk_ccorr_stop, 286 .ctm_set = mtk_ccorr_ctm_set, 287 }; 288 289 static const struct mtk_ddp_comp_funcs ddp_color = { 290 .clk_enable = mtk_color_clk_enable, 291 .clk_disable = mtk_color_clk_disable, 292 .config = mtk_color_config, 293 .start = mtk_color_start, 294 }; 295 296 static const struct mtk_ddp_comp_funcs ddp_dither = { 297 .clk_enable = mtk_ddp_clk_enable, 298 .clk_disable = mtk_ddp_clk_disable, 299 .config = mtk_dither_config, 300 .start = mtk_dither_start, 301 .stop = mtk_dither_stop, 302 }; 303 304 static const struct mtk_ddp_comp_funcs ddp_dpi = { 305 .start = mtk_dpi_start, 306 .stop = mtk_dpi_stop, 307 }; 308 309 static const struct mtk_ddp_comp_funcs ddp_dsc = { 310 .clk_enable = mtk_ddp_clk_enable, 311 .clk_disable = mtk_ddp_clk_disable, 312 .config = mtk_dsc_config, 313 .start = mtk_dsc_start, 314 .stop = mtk_dsc_stop, 315 }; 316 317 static const struct mtk_ddp_comp_funcs ddp_dsi = { 318 .start = mtk_dsi_ddp_start, 319 .stop = mtk_dsi_ddp_stop, 320 }; 321 322 static const struct mtk_ddp_comp_funcs ddp_gamma = { 323 .clk_enable = mtk_gamma_clk_enable, 324 .clk_disable = mtk_gamma_clk_disable, 325 .gamma_set = mtk_gamma_set, 326 .config = mtk_gamma_config, 327 .start = mtk_gamma_start, 328 .stop = mtk_gamma_stop, 329 }; 330 331 static const struct mtk_ddp_comp_funcs ddp_merge = { 332 .clk_enable = mtk_merge_clk_enable, 333 .clk_disable = mtk_merge_clk_disable, 334 .start = mtk_merge_start, 335 .stop = mtk_merge_stop, 336 .config = mtk_merge_config, 337 }; 338 339 static const struct mtk_ddp_comp_funcs ddp_od = { 340 .clk_enable = mtk_ddp_clk_enable, 341 .clk_disable = mtk_ddp_clk_disable, 342 .config = mtk_od_config, 343 .start = mtk_od_start, 344 }; 345 346 static const struct mtk_ddp_comp_funcs ddp_ovl = { 347 .clk_enable = mtk_ovl_clk_enable, 348 .clk_disable = mtk_ovl_clk_disable, 349 .config = mtk_ovl_config, 350 .start = mtk_ovl_start, 351 .stop = mtk_ovl_stop, 352 .register_vblank_cb = mtk_ovl_register_vblank_cb, 353 .unregister_vblank_cb = mtk_ovl_unregister_vblank_cb, 354 .enable_vblank = mtk_ovl_enable_vblank, 355 .disable_vblank = mtk_ovl_disable_vblank, 356 .supported_rotations = mtk_ovl_supported_rotations, 357 .layer_nr = mtk_ovl_layer_nr, 358 .layer_check = mtk_ovl_layer_check, 359 .layer_config = mtk_ovl_layer_config, 360 .bgclr_in_on = mtk_ovl_bgclr_in_on, 361 .bgclr_in_off = mtk_ovl_bgclr_in_off, 362 }; 363 364 static const struct mtk_ddp_comp_funcs ddp_postmask = { 365 .clk_enable = mtk_ddp_clk_enable, 366 .clk_disable = mtk_ddp_clk_disable, 367 .config = mtk_postmask_config, 368 .start = mtk_postmask_start, 369 .stop = mtk_postmask_stop, 370 }; 371 372 static const struct mtk_ddp_comp_funcs ddp_rdma = { 373 .clk_enable = mtk_rdma_clk_enable, 374 .clk_disable = mtk_rdma_clk_disable, 375 .config = mtk_rdma_config, 376 .start = mtk_rdma_start, 377 .stop = mtk_rdma_stop, 378 .register_vblank_cb = mtk_rdma_register_vblank_cb, 379 .unregister_vblank_cb = mtk_rdma_unregister_vblank_cb, 380 .enable_vblank = mtk_rdma_enable_vblank, 381 .disable_vblank = mtk_rdma_disable_vblank, 382 .layer_nr = mtk_rdma_layer_nr, 383 .layer_config = mtk_rdma_layer_config, 384 }; 385 386 static const struct mtk_ddp_comp_funcs ddp_ufoe = { 387 .clk_enable = mtk_ddp_clk_enable, 388 .clk_disable = mtk_ddp_clk_disable, 389 .start = mtk_ufoe_start, 390 }; 391 392 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { 393 [MTK_DISP_AAL] = "aal", 394 [MTK_DISP_BLS] = "bls", 395 [MTK_DISP_CCORR] = "ccorr", 396 [MTK_DISP_COLOR] = "color", 397 [MTK_DISP_DITHER] = "dither", 398 [MTK_DISP_DSC] = "dsc", 399 [MTK_DISP_GAMMA] = "gamma", 400 [MTK_DISP_MERGE] = "merge", 401 [MTK_DISP_MUTEX] = "mutex", 402 [MTK_DISP_OD] = "od", 403 [MTK_DISP_OVL] = "ovl", 404 [MTK_DISP_OVL_2L] = "ovl-2l", 405 [MTK_DISP_POSTMASK] = "postmask", 406 [MTK_DISP_PWM] = "pwm", 407 [MTK_DISP_RDMA] = "rdma", 408 [MTK_DISP_UFOE] = "ufoe", 409 [MTK_DISP_WDMA] = "wdma", 410 [MTK_DP_INTF] = "dp-intf", 411 [MTK_DPI] = "dpi", 412 [MTK_DSI] = "dsi", 413 }; 414 415 struct mtk_ddp_comp_match { 416 enum mtk_ddp_comp_type type; 417 int alias_id; 418 const struct mtk_ddp_comp_funcs *funcs; 419 }; 420 421 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { 422 [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, 423 [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, 424 [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, 425 [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, 426 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, 427 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, 428 [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither }, 429 [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi }, 430 [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi }, 431 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, 432 [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, 433 [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc }, 434 [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc }, 435 [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, 436 [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, 437 [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, 438 [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, 439 [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, 440 [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge }, 441 [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge }, 442 [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge }, 443 [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge }, 444 [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge }, 445 [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge }, 446 [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, 447 [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, 448 [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, 449 [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, 450 [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, 451 [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, 452 [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, 453 [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, 454 [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, 455 [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, 456 [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, 457 [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, 458 [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, 459 [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, 460 [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma }, 461 [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, 462 [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, 463 [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, 464 }; 465 466 static bool mtk_drm_find_comp_in_ddp(struct device *dev, 467 const enum mtk_ddp_comp_id *path, 468 unsigned int path_len, 469 struct mtk_ddp_comp *ddp_comp) 470 { 471 unsigned int i; 472 473 if (path == NULL) 474 return false; 475 476 for (i = 0U; i < path_len; i++) 477 if (dev == ddp_comp[path[i]].dev) 478 return true; 479 480 return false; 481 } 482 483 int mtk_ddp_comp_get_id(struct device_node *node, 484 enum mtk_ddp_comp_type comp_type) 485 { 486 int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]); 487 int i; 488 489 for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) { 490 if (comp_type == mtk_ddp_matches[i].type && 491 (id < 0 || id == mtk_ddp_matches[i].alias_id)) 492 return i; 493 } 494 495 return -EINVAL; 496 } 497 498 unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, 499 struct device *dev) 500 { 501 struct mtk_drm_private *private = drm->dev_private; 502 unsigned int ret = 0; 503 504 if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len, 505 private->ddp_comp)) 506 ret = BIT(0); 507 else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path, 508 private->data->ext_len, private->ddp_comp)) 509 ret = BIT(1); 510 else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path, 511 private->data->third_len, private->ddp_comp)) 512 ret = BIT(2); 513 else 514 DRM_INFO("Failed to find comp in ddp table\n"); 515 516 return ret; 517 } 518 519 int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, 520 enum mtk_ddp_comp_id comp_id) 521 { 522 struct platform_device *comp_pdev; 523 enum mtk_ddp_comp_type type; 524 struct mtk_ddp_comp_dev *priv; 525 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 526 int ret; 527 #endif 528 529 if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) 530 return -EINVAL; 531 532 type = mtk_ddp_matches[comp_id].type; 533 534 comp->id = comp_id; 535 comp->funcs = mtk_ddp_matches[comp_id].funcs; 536 comp_pdev = of_find_device_by_node(node); 537 if (!comp_pdev) { 538 DRM_INFO("Waiting for device %s\n", node->full_name); 539 return -EPROBE_DEFER; 540 } 541 comp->dev = &comp_pdev->dev; 542 543 if (type == MTK_DISP_AAL || 544 type == MTK_DISP_BLS || 545 type == MTK_DISP_CCORR || 546 type == MTK_DISP_COLOR || 547 type == MTK_DISP_GAMMA || 548 type == MTK_DISP_MERGE || 549 type == MTK_DISP_OVL || 550 type == MTK_DISP_OVL_2L || 551 type == MTK_DISP_PWM || 552 type == MTK_DISP_RDMA || 553 type == MTK_DPI || 554 type == MTK_DP_INTF || 555 type == MTK_DSI) 556 return 0; 557 558 priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL); 559 if (!priv) 560 return -ENOMEM; 561 562 priv->regs = of_iomap(node, 0); 563 priv->clk = of_clk_get(node, 0); 564 if (IS_ERR(priv->clk)) 565 return PTR_ERR(priv->clk); 566 567 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 568 ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0); 569 if (ret) 570 dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n"); 571 #endif 572 573 platform_set_drvdata(comp_pdev, priv); 574 575 return 0; 576 } 577