1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 9 #include <asm/barrier.h> 10 #include <soc/mediatek/smi.h> 11 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_plane_helper.h> 14 #include <drm/drm_probe_helper.h> 15 #include <drm/drm_vblank.h> 16 17 #include "mtk_drm_drv.h" 18 #include "mtk_drm_crtc.h" 19 #include "mtk_drm_ddp.h" 20 #include "mtk_drm_ddp_comp.h" 21 #include "mtk_drm_gem.h" 22 #include "mtk_drm_plane.h" 23 24 /** 25 * struct mtk_drm_crtc - MediaTek specific crtc structure. 26 * @base: crtc object. 27 * @enabled: records whether crtc_enable succeeded 28 * @planes: array of 4 drm_plane structures, one for each overlay plane 29 * @pending_planes: whether any plane has pending changes to be applied 30 * @config_regs: memory mapped mmsys configuration register space 31 * @mutex: handle to one of the ten disp_mutex streams 32 * @ddp_comp_nr: number of components in ddp_comp 33 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 34 */ 35 struct mtk_drm_crtc { 36 struct drm_crtc base; 37 bool enabled; 38 39 bool pending_needs_vblank; 40 struct drm_pending_vblank_event *event; 41 42 struct drm_plane *planes; 43 unsigned int layer_nr; 44 bool pending_planes; 45 46 void __iomem *config_regs; 47 struct mtk_disp_mutex *mutex; 48 unsigned int ddp_comp_nr; 49 struct mtk_ddp_comp **ddp_comp; 50 }; 51 52 struct mtk_crtc_state { 53 struct drm_crtc_state base; 54 55 bool pending_config; 56 unsigned int pending_width; 57 unsigned int pending_height; 58 unsigned int pending_vrefresh; 59 }; 60 61 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 62 { 63 return container_of(c, struct mtk_drm_crtc, base); 64 } 65 66 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 67 { 68 return container_of(s, struct mtk_crtc_state, base); 69 } 70 71 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 72 { 73 struct drm_crtc *crtc = &mtk_crtc->base; 74 unsigned long flags; 75 76 spin_lock_irqsave(&crtc->dev->event_lock, flags); 77 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 78 drm_crtc_vblank_put(crtc); 79 mtk_crtc->event = NULL; 80 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 81 } 82 83 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 84 { 85 drm_crtc_handle_vblank(&mtk_crtc->base); 86 if (mtk_crtc->pending_needs_vblank) { 87 mtk_drm_crtc_finish_page_flip(mtk_crtc); 88 mtk_crtc->pending_needs_vblank = false; 89 } 90 } 91 92 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 93 { 94 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 95 96 mtk_disp_mutex_put(mtk_crtc->mutex); 97 98 drm_crtc_cleanup(crtc); 99 } 100 101 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 102 { 103 struct mtk_crtc_state *state; 104 105 if (crtc->state) { 106 __drm_atomic_helper_crtc_destroy_state(crtc->state); 107 108 state = to_mtk_crtc_state(crtc->state); 109 memset(state, 0, sizeof(*state)); 110 } else { 111 state = kzalloc(sizeof(*state), GFP_KERNEL); 112 if (!state) 113 return; 114 crtc->state = &state->base; 115 } 116 117 state->base.crtc = crtc; 118 } 119 120 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 121 { 122 struct mtk_crtc_state *state; 123 124 state = kzalloc(sizeof(*state), GFP_KERNEL); 125 if (!state) 126 return NULL; 127 128 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 129 130 WARN_ON(state->base.crtc != crtc); 131 state->base.crtc = crtc; 132 133 return &state->base; 134 } 135 136 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 137 struct drm_crtc_state *state) 138 { 139 __drm_atomic_helper_crtc_destroy_state(state); 140 kfree(to_mtk_crtc_state(state)); 141 } 142 143 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 144 const struct drm_display_mode *mode, 145 struct drm_display_mode *adjusted_mode) 146 { 147 /* Nothing to do here, but this callback is mandatory. */ 148 return true; 149 } 150 151 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 152 { 153 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 154 155 state->pending_width = crtc->mode.hdisplay; 156 state->pending_height = crtc->mode.vdisplay; 157 state->pending_vrefresh = crtc->mode.vrefresh; 158 wmb(); /* Make sure the above parameters are set before update */ 159 state->pending_config = true; 160 } 161 162 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 163 { 164 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 165 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 166 167 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 168 169 return 0; 170 } 171 172 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 173 { 174 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 175 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 176 177 mtk_ddp_comp_disable_vblank(comp); 178 } 179 180 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 181 { 182 int ret; 183 int i; 184 185 DRM_DEBUG_DRIVER("%s\n", __func__); 186 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 187 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 188 if (ret) { 189 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 190 goto err; 191 } 192 } 193 194 return 0; 195 err: 196 while (--i >= 0) 197 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 198 return ret; 199 } 200 201 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 202 { 203 int i; 204 205 DRM_DEBUG_DRIVER("%s\n", __func__); 206 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 207 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 208 } 209 210 static 211 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 212 struct drm_plane *plane, 213 unsigned int *local_layer) 214 { 215 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 216 struct mtk_ddp_comp *comp; 217 int i, count = 0; 218 unsigned int local_index = plane - mtk_crtc->planes; 219 220 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 221 comp = mtk_crtc->ddp_comp[i]; 222 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 223 *local_layer = local_index - count; 224 return comp; 225 } 226 count += mtk_ddp_comp_layer_nr(comp); 227 } 228 229 WARN(1, "Failed to find component for plane %d\n", plane->index); 230 return NULL; 231 } 232 233 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 234 { 235 struct drm_crtc *crtc = &mtk_crtc->base; 236 struct drm_connector *connector; 237 struct drm_encoder *encoder; 238 struct drm_connector_list_iter conn_iter; 239 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 240 int ret; 241 int i; 242 243 DRM_DEBUG_DRIVER("%s\n", __func__); 244 if (WARN_ON(!crtc->state)) 245 return -EINVAL; 246 247 width = crtc->state->adjusted_mode.hdisplay; 248 height = crtc->state->adjusted_mode.vdisplay; 249 vrefresh = crtc->state->adjusted_mode.vrefresh; 250 251 drm_for_each_encoder(encoder, crtc->dev) { 252 if (encoder->crtc != crtc) 253 continue; 254 255 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 256 drm_for_each_connector_iter(connector, &conn_iter) { 257 if (connector->encoder != encoder) 258 continue; 259 if (connector->display_info.bpc != 0 && 260 bpc > connector->display_info.bpc) 261 bpc = connector->display_info.bpc; 262 } 263 drm_connector_list_iter_end(&conn_iter); 264 } 265 266 ret = pm_runtime_get_sync(crtc->dev->dev); 267 if (ret < 0) { 268 DRM_ERROR("Failed to enable power domain: %d\n", ret); 269 return ret; 270 } 271 272 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 273 if (ret < 0) { 274 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 275 goto err_pm_runtime_put; 276 } 277 278 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 279 if (ret < 0) { 280 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 281 goto err_mutex_unprepare; 282 } 283 284 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); 285 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 286 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, 287 mtk_crtc->ddp_comp[i]->id, 288 mtk_crtc->ddp_comp[i + 1]->id); 289 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 290 mtk_crtc->ddp_comp[i]->id); 291 } 292 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 293 mtk_disp_mutex_enable(mtk_crtc->mutex); 294 295 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 296 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 297 298 if (i == 1) 299 mtk_ddp_comp_bgclr_in_on(comp); 300 301 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc); 302 mtk_ddp_comp_start(comp); 303 } 304 305 /* Initially configure all planes */ 306 for (i = 0; i < mtk_crtc->layer_nr; i++) { 307 struct drm_plane *plane = &mtk_crtc->planes[i]; 308 struct mtk_plane_state *plane_state; 309 struct mtk_ddp_comp *comp; 310 unsigned int local_layer; 311 312 plane_state = to_mtk_plane_state(plane->state); 313 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 314 if (comp) 315 mtk_ddp_comp_layer_config(comp, local_layer, 316 plane_state); 317 } 318 319 return 0; 320 321 err_mutex_unprepare: 322 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 323 err_pm_runtime_put: 324 pm_runtime_put(crtc->dev->dev); 325 return ret; 326 } 327 328 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 329 { 330 struct drm_device *drm = mtk_crtc->base.dev; 331 int i; 332 333 DRM_DEBUG_DRIVER("%s\n", __func__); 334 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 335 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 336 if (i == 1) 337 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 338 } 339 340 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 341 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 342 mtk_crtc->ddp_comp[i]->id); 343 mtk_disp_mutex_disable(mtk_crtc->mutex); 344 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 345 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, 346 mtk_crtc->ddp_comp[i]->id, 347 mtk_crtc->ddp_comp[i + 1]->id); 348 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 349 mtk_crtc->ddp_comp[i]->id); 350 } 351 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 352 mtk_crtc_ddp_clk_disable(mtk_crtc); 353 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 354 355 pm_runtime_put(drm->dev); 356 } 357 358 static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 359 { 360 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 361 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 362 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 363 unsigned int i; 364 unsigned int local_layer; 365 366 /* 367 * TODO: instead of updating the registers here, we should prepare 368 * working registers in atomic_commit and let the hardware command 369 * queue update module registers on vblank. 370 */ 371 if (state->pending_config) { 372 mtk_ddp_comp_config(comp, state->pending_width, 373 state->pending_height, 374 state->pending_vrefresh, 0); 375 376 state->pending_config = false; 377 } 378 379 if (mtk_crtc->pending_planes) { 380 for (i = 0; i < mtk_crtc->layer_nr; i++) { 381 struct drm_plane *plane = &mtk_crtc->planes[i]; 382 struct mtk_plane_state *plane_state; 383 384 plane_state = to_mtk_plane_state(plane->state); 385 386 if (!plane_state->pending.config) 387 continue; 388 389 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 390 &local_layer); 391 392 if (comp) 393 mtk_ddp_comp_layer_config(comp, local_layer, 394 plane_state); 395 plane_state->pending.config = false; 396 } 397 mtk_crtc->pending_planes = false; 398 } 399 } 400 401 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 402 struct mtk_plane_state *state) 403 { 404 unsigned int local_layer; 405 struct mtk_ddp_comp *comp; 406 407 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 408 if (comp) 409 return mtk_ddp_comp_layer_check(comp, local_layer, state); 410 return 0; 411 } 412 413 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 414 struct drm_crtc_state *old_state) 415 { 416 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 417 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 418 int ret; 419 420 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 421 422 ret = mtk_smi_larb_get(comp->larb_dev); 423 if (ret) { 424 DRM_ERROR("Failed to get larb: %d\n", ret); 425 return; 426 } 427 428 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 429 if (ret) { 430 mtk_smi_larb_put(comp->larb_dev); 431 return; 432 } 433 434 drm_crtc_vblank_on(crtc); 435 mtk_crtc->enabled = true; 436 } 437 438 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 439 struct drm_crtc_state *old_state) 440 { 441 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 442 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 443 int i; 444 445 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 446 if (!mtk_crtc->enabled) 447 return; 448 449 /* Set all pending plane state to disabled */ 450 for (i = 0; i < mtk_crtc->layer_nr; i++) { 451 struct drm_plane *plane = &mtk_crtc->planes[i]; 452 struct mtk_plane_state *plane_state; 453 454 plane_state = to_mtk_plane_state(plane->state); 455 plane_state->pending.enable = false; 456 plane_state->pending.config = true; 457 } 458 mtk_crtc->pending_planes = true; 459 460 /* Wait for planes to be disabled */ 461 drm_crtc_wait_one_vblank(crtc); 462 463 drm_crtc_vblank_off(crtc); 464 mtk_crtc_ddp_hw_fini(mtk_crtc); 465 mtk_smi_larb_put(comp->larb_dev); 466 467 mtk_crtc->enabled = false; 468 } 469 470 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 471 struct drm_crtc_state *old_crtc_state) 472 { 473 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 474 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 475 476 if (mtk_crtc->event && state->base.event) 477 DRM_ERROR("new event while there is still a pending event\n"); 478 479 if (state->base.event) { 480 state->base.event->pipe = drm_crtc_index(crtc); 481 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 482 mtk_crtc->event = state->base.event; 483 state->base.event = NULL; 484 } 485 } 486 487 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 488 struct drm_crtc_state *old_crtc_state) 489 { 490 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 491 struct mtk_drm_private *priv = crtc->dev->dev_private; 492 unsigned int pending_planes = 0; 493 int i; 494 495 if (mtk_crtc->event) 496 mtk_crtc->pending_needs_vblank = true; 497 for (i = 0; i < mtk_crtc->layer_nr; i++) { 498 struct drm_plane *plane = &mtk_crtc->planes[i]; 499 struct mtk_plane_state *plane_state; 500 501 plane_state = to_mtk_plane_state(plane->state); 502 if (plane_state->pending.dirty) { 503 plane_state->pending.config = true; 504 plane_state->pending.dirty = false; 505 pending_planes |= BIT(i); 506 } 507 } 508 if (pending_planes) 509 mtk_crtc->pending_planes = true; 510 if (crtc->state->color_mgmt_changed) 511 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 512 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 513 514 if (priv->data->shadow_register) { 515 mtk_disp_mutex_acquire(mtk_crtc->mutex); 516 mtk_crtc_ddp_config(crtc); 517 mtk_disp_mutex_release(mtk_crtc->mutex); 518 } 519 } 520 521 static const struct drm_crtc_funcs mtk_crtc_funcs = { 522 .set_config = drm_atomic_helper_set_config, 523 .page_flip = drm_atomic_helper_page_flip, 524 .destroy = mtk_drm_crtc_destroy, 525 .reset = mtk_drm_crtc_reset, 526 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 527 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 528 .gamma_set = drm_atomic_helper_legacy_gamma_set, 529 .enable_vblank = mtk_drm_crtc_enable_vblank, 530 .disable_vblank = mtk_drm_crtc_disable_vblank, 531 }; 532 533 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 534 .mode_fixup = mtk_drm_crtc_mode_fixup, 535 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 536 .atomic_begin = mtk_drm_crtc_atomic_begin, 537 .atomic_flush = mtk_drm_crtc_atomic_flush, 538 .atomic_enable = mtk_drm_crtc_atomic_enable, 539 .atomic_disable = mtk_drm_crtc_atomic_disable, 540 }; 541 542 static int mtk_drm_crtc_init(struct drm_device *drm, 543 struct mtk_drm_crtc *mtk_crtc, 544 struct drm_plane *primary, 545 struct drm_plane *cursor, unsigned int pipe) 546 { 547 int ret; 548 549 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 550 &mtk_crtc_funcs, NULL); 551 if (ret) 552 goto err_cleanup_crtc; 553 554 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 555 556 return 0; 557 558 err_cleanup_crtc: 559 drm_crtc_cleanup(&mtk_crtc->base); 560 return ret; 561 } 562 563 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 564 { 565 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 566 struct mtk_drm_private *priv = crtc->dev->dev_private; 567 568 if (!priv->data->shadow_register) 569 mtk_crtc_ddp_config(crtc); 570 571 mtk_drm_finish_page_flip(mtk_crtc); 572 } 573 574 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 575 int comp_idx) 576 { 577 struct mtk_ddp_comp *comp; 578 579 if (comp_idx > 1) 580 return 0; 581 582 comp = mtk_crtc->ddp_comp[comp_idx]; 583 if (!comp->funcs) 584 return 0; 585 586 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 587 return 0; 588 589 return mtk_ddp_comp_layer_nr(comp); 590 } 591 592 static inline 593 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx) 594 { 595 if (plane_idx == 0) 596 return DRM_PLANE_TYPE_PRIMARY; 597 else if (plane_idx == 1) 598 return DRM_PLANE_TYPE_CURSOR; 599 else 600 return DRM_PLANE_TYPE_OVERLAY; 601 602 } 603 604 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 605 struct mtk_drm_crtc *mtk_crtc, 606 int comp_idx, int pipe) 607 { 608 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 609 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 610 int i, ret; 611 612 for (i = 0; i < num_planes; i++) { 613 ret = mtk_plane_init(drm_dev, 614 &mtk_crtc->planes[mtk_crtc->layer_nr], 615 BIT(pipe), 616 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr), 617 mtk_ddp_comp_supported_rotations(comp)); 618 if (ret) 619 return ret; 620 621 mtk_crtc->layer_nr++; 622 } 623 return 0; 624 } 625 626 int mtk_drm_crtc_create(struct drm_device *drm_dev, 627 const enum mtk_ddp_comp_id *path, unsigned int path_len) 628 { 629 struct mtk_drm_private *priv = drm_dev->dev_private; 630 struct device *dev = drm_dev->dev; 631 struct mtk_drm_crtc *mtk_crtc; 632 unsigned int num_comp_planes = 0; 633 int pipe = priv->num_pipes; 634 int ret; 635 int i; 636 637 if (!path) 638 return 0; 639 640 for (i = 0; i < path_len; i++) { 641 enum mtk_ddp_comp_id comp_id = path[i]; 642 struct device_node *node; 643 644 node = priv->comp_node[comp_id]; 645 if (!node) { 646 dev_info(dev, 647 "Not creating crtc %d because component %d is disabled or missing\n", 648 pipe, comp_id); 649 return 0; 650 } 651 } 652 653 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 654 if (!mtk_crtc) 655 return -ENOMEM; 656 657 mtk_crtc->config_regs = priv->config_regs; 658 mtk_crtc->ddp_comp_nr = path_len; 659 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 660 sizeof(*mtk_crtc->ddp_comp), 661 GFP_KERNEL); 662 if (!mtk_crtc->ddp_comp) 663 return -ENOMEM; 664 665 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 666 if (IS_ERR(mtk_crtc->mutex)) { 667 ret = PTR_ERR(mtk_crtc->mutex); 668 dev_err(dev, "Failed to get mutex: %d\n", ret); 669 return ret; 670 } 671 672 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 673 enum mtk_ddp_comp_id comp_id = path[i]; 674 struct mtk_ddp_comp *comp; 675 struct device_node *node; 676 677 node = priv->comp_node[comp_id]; 678 comp = priv->ddp_comp[comp_id]; 679 if (!comp) { 680 dev_err(dev, "Component %pOF not initialized\n", node); 681 ret = -ENODEV; 682 return ret; 683 } 684 685 mtk_crtc->ddp_comp[i] = comp; 686 } 687 688 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 689 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 690 691 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 692 sizeof(struct drm_plane), GFP_KERNEL); 693 694 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 695 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 696 pipe); 697 if (ret) 698 return ret; 699 } 700 701 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0], 702 mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] : 703 NULL, pipe); 704 if (ret < 0) 705 return ret; 706 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); 707 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); 708 priv->num_pipes++; 709 710 return 0; 711 } 712