1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 9 #include <asm/barrier.h> 10 #include <soc/mediatek/smi.h> 11 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_plane_helper.h> 14 #include <drm/drm_probe_helper.h> 15 #include <drm/drm_vblank.h> 16 17 #include "mtk_drm_drv.h" 18 #include "mtk_drm_crtc.h" 19 #include "mtk_drm_ddp.h" 20 #include "mtk_drm_ddp_comp.h" 21 #include "mtk_drm_gem.h" 22 #include "mtk_drm_plane.h" 23 24 /** 25 * struct mtk_drm_crtc - MediaTek specific crtc structure. 26 * @base: crtc object. 27 * @enabled: records whether crtc_enable succeeded 28 * @planes: array of 4 drm_plane structures, one for each overlay plane 29 * @pending_planes: whether any plane has pending changes to be applied 30 * @config_regs: memory mapped mmsys configuration register space 31 * @mutex: handle to one of the ten disp_mutex streams 32 * @ddp_comp_nr: number of components in ddp_comp 33 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 34 */ 35 struct mtk_drm_crtc { 36 struct drm_crtc base; 37 bool enabled; 38 39 bool pending_needs_vblank; 40 struct drm_pending_vblank_event *event; 41 42 struct drm_plane *planes; 43 unsigned int layer_nr; 44 bool pending_planes; 45 46 void __iomem *config_regs; 47 struct mtk_disp_mutex *mutex; 48 unsigned int ddp_comp_nr; 49 struct mtk_ddp_comp **ddp_comp; 50 }; 51 52 struct mtk_crtc_state { 53 struct drm_crtc_state base; 54 55 bool pending_config; 56 unsigned int pending_width; 57 unsigned int pending_height; 58 unsigned int pending_vrefresh; 59 }; 60 61 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 62 { 63 return container_of(c, struct mtk_drm_crtc, base); 64 } 65 66 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 67 { 68 return container_of(s, struct mtk_crtc_state, base); 69 } 70 71 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 72 { 73 struct drm_crtc *crtc = &mtk_crtc->base; 74 unsigned long flags; 75 76 spin_lock_irqsave(&crtc->dev->event_lock, flags); 77 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 78 drm_crtc_vblank_put(crtc); 79 mtk_crtc->event = NULL; 80 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 81 } 82 83 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 84 { 85 drm_crtc_handle_vblank(&mtk_crtc->base); 86 if (mtk_crtc->pending_needs_vblank) { 87 mtk_drm_crtc_finish_page_flip(mtk_crtc); 88 mtk_crtc->pending_needs_vblank = false; 89 } 90 } 91 92 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 93 { 94 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 95 96 mtk_disp_mutex_put(mtk_crtc->mutex); 97 98 drm_crtc_cleanup(crtc); 99 } 100 101 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 102 { 103 struct mtk_crtc_state *state; 104 105 if (crtc->state) { 106 __drm_atomic_helper_crtc_destroy_state(crtc->state); 107 108 state = to_mtk_crtc_state(crtc->state); 109 memset(state, 0, sizeof(*state)); 110 } else { 111 state = kzalloc(sizeof(*state), GFP_KERNEL); 112 if (!state) 113 return; 114 crtc->state = &state->base; 115 } 116 117 state->base.crtc = crtc; 118 } 119 120 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 121 { 122 struct mtk_crtc_state *state; 123 124 state = kzalloc(sizeof(*state), GFP_KERNEL); 125 if (!state) 126 return NULL; 127 128 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 129 130 WARN_ON(state->base.crtc != crtc); 131 state->base.crtc = crtc; 132 133 return &state->base; 134 } 135 136 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 137 struct drm_crtc_state *state) 138 { 139 __drm_atomic_helper_crtc_destroy_state(state); 140 kfree(to_mtk_crtc_state(state)); 141 } 142 143 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 144 const struct drm_display_mode *mode, 145 struct drm_display_mode *adjusted_mode) 146 { 147 /* Nothing to do here, but this callback is mandatory. */ 148 return true; 149 } 150 151 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 152 { 153 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 154 155 state->pending_width = crtc->mode.hdisplay; 156 state->pending_height = crtc->mode.vdisplay; 157 state->pending_vrefresh = crtc->mode.vrefresh; 158 wmb(); /* Make sure the above parameters are set before update */ 159 state->pending_config = true; 160 } 161 162 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 163 { 164 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 165 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 166 167 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 168 169 return 0; 170 } 171 172 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 173 { 174 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 175 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 176 177 mtk_ddp_comp_disable_vblank(comp); 178 } 179 180 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 181 { 182 int ret; 183 int i; 184 185 DRM_DEBUG_DRIVER("%s\n", __func__); 186 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 187 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 188 if (ret) { 189 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 190 goto err; 191 } 192 } 193 194 return 0; 195 err: 196 while (--i >= 0) 197 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 198 return ret; 199 } 200 201 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 202 { 203 int i; 204 205 DRM_DEBUG_DRIVER("%s\n", __func__); 206 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 207 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 208 } 209 210 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 211 { 212 struct drm_crtc *crtc = &mtk_crtc->base; 213 struct drm_connector *connector; 214 struct drm_encoder *encoder; 215 struct drm_connector_list_iter conn_iter; 216 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 217 int ret; 218 int i; 219 220 DRM_DEBUG_DRIVER("%s\n", __func__); 221 if (WARN_ON(!crtc->state)) 222 return -EINVAL; 223 224 width = crtc->state->adjusted_mode.hdisplay; 225 height = crtc->state->adjusted_mode.vdisplay; 226 vrefresh = crtc->state->adjusted_mode.vrefresh; 227 228 drm_for_each_encoder(encoder, crtc->dev) { 229 if (encoder->crtc != crtc) 230 continue; 231 232 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 233 drm_for_each_connector_iter(connector, &conn_iter) { 234 if (connector->encoder != encoder) 235 continue; 236 if (connector->display_info.bpc != 0 && 237 bpc > connector->display_info.bpc) 238 bpc = connector->display_info.bpc; 239 } 240 drm_connector_list_iter_end(&conn_iter); 241 } 242 243 ret = pm_runtime_get_sync(crtc->dev->dev); 244 if (ret < 0) { 245 DRM_ERROR("Failed to enable power domain: %d\n", ret); 246 return ret; 247 } 248 249 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 250 if (ret < 0) { 251 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 252 goto err_pm_runtime_put; 253 } 254 255 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 256 if (ret < 0) { 257 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 258 goto err_mutex_unprepare; 259 } 260 261 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); 262 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 263 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, 264 mtk_crtc->ddp_comp[i]->id, 265 mtk_crtc->ddp_comp[i + 1]->id); 266 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 267 mtk_crtc->ddp_comp[i]->id); 268 } 269 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 270 mtk_disp_mutex_enable(mtk_crtc->mutex); 271 272 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 273 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 274 275 if (i == 1) 276 mtk_ddp_comp_bgclr_in_on(comp); 277 278 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc); 279 mtk_ddp_comp_start(comp); 280 } 281 282 /* Initially configure all planes */ 283 for (i = 0; i < mtk_crtc->layer_nr; i++) { 284 struct drm_plane *plane = &mtk_crtc->planes[i]; 285 struct mtk_plane_state *plane_state; 286 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 287 unsigned int comp_layer_nr = mtk_ddp_comp_layer_nr(comp); 288 unsigned int local_layer; 289 290 plane_state = to_mtk_plane_state(plane->state); 291 292 if (i >= comp_layer_nr) { 293 comp = mtk_crtc->ddp_comp[1]; 294 local_layer = i - comp_layer_nr; 295 } else 296 local_layer = i; 297 mtk_ddp_comp_layer_config(comp, local_layer, 298 plane_state); 299 } 300 301 return 0; 302 303 err_mutex_unprepare: 304 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 305 err_pm_runtime_put: 306 pm_runtime_put(crtc->dev->dev); 307 return ret; 308 } 309 310 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 311 { 312 struct drm_device *drm = mtk_crtc->base.dev; 313 int i; 314 315 DRM_DEBUG_DRIVER("%s\n", __func__); 316 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 317 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 318 if (i == 1) 319 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 320 } 321 322 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 323 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 324 mtk_crtc->ddp_comp[i]->id); 325 mtk_disp_mutex_disable(mtk_crtc->mutex); 326 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 327 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, 328 mtk_crtc->ddp_comp[i]->id, 329 mtk_crtc->ddp_comp[i + 1]->id); 330 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 331 mtk_crtc->ddp_comp[i]->id); 332 } 333 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 334 mtk_crtc_ddp_clk_disable(mtk_crtc); 335 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 336 337 pm_runtime_put(drm->dev); 338 } 339 340 static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 341 { 342 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 343 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 344 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 345 unsigned int i; 346 unsigned int comp_layer_nr = mtk_ddp_comp_layer_nr(comp); 347 unsigned int local_layer; 348 349 /* 350 * TODO: instead of updating the registers here, we should prepare 351 * working registers in atomic_commit and let the hardware command 352 * queue update module registers on vblank. 353 */ 354 if (state->pending_config) { 355 mtk_ddp_comp_config(comp, state->pending_width, 356 state->pending_height, 357 state->pending_vrefresh, 0); 358 359 state->pending_config = false; 360 } 361 362 if (mtk_crtc->pending_planes) { 363 for (i = 0; i < mtk_crtc->layer_nr; i++) { 364 struct drm_plane *plane = &mtk_crtc->planes[i]; 365 struct mtk_plane_state *plane_state; 366 367 plane_state = to_mtk_plane_state(plane->state); 368 369 if (plane_state->pending.config) { 370 if (i >= comp_layer_nr) { 371 comp = mtk_crtc->ddp_comp[1]; 372 local_layer = i - comp_layer_nr; 373 } else 374 local_layer = i; 375 376 mtk_ddp_comp_layer_config(comp, local_layer, 377 plane_state); 378 plane_state->pending.config = false; 379 } 380 } 381 mtk_crtc->pending_planes = false; 382 } 383 } 384 385 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 386 struct drm_crtc_state *old_state) 387 { 388 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 389 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 390 int ret; 391 392 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 393 394 ret = mtk_smi_larb_get(comp->larb_dev); 395 if (ret) { 396 DRM_ERROR("Failed to get larb: %d\n", ret); 397 return; 398 } 399 400 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 401 if (ret) { 402 mtk_smi_larb_put(comp->larb_dev); 403 return; 404 } 405 406 drm_crtc_vblank_on(crtc); 407 mtk_crtc->enabled = true; 408 } 409 410 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 411 struct drm_crtc_state *old_state) 412 { 413 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 414 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 415 int i; 416 417 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 418 if (!mtk_crtc->enabled) 419 return; 420 421 /* Set all pending plane state to disabled */ 422 for (i = 0; i < mtk_crtc->layer_nr; i++) { 423 struct drm_plane *plane = &mtk_crtc->planes[i]; 424 struct mtk_plane_state *plane_state; 425 426 plane_state = to_mtk_plane_state(plane->state); 427 plane_state->pending.enable = false; 428 plane_state->pending.config = true; 429 } 430 mtk_crtc->pending_planes = true; 431 432 /* Wait for planes to be disabled */ 433 drm_crtc_wait_one_vblank(crtc); 434 435 drm_crtc_vblank_off(crtc); 436 mtk_crtc_ddp_hw_fini(mtk_crtc); 437 mtk_smi_larb_put(comp->larb_dev); 438 439 mtk_crtc->enabled = false; 440 } 441 442 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 443 struct drm_crtc_state *old_crtc_state) 444 { 445 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 446 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 447 448 if (mtk_crtc->event && state->base.event) 449 DRM_ERROR("new event while there is still a pending event\n"); 450 451 if (state->base.event) { 452 state->base.event->pipe = drm_crtc_index(crtc); 453 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 454 mtk_crtc->event = state->base.event; 455 state->base.event = NULL; 456 } 457 } 458 459 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 460 struct drm_crtc_state *old_crtc_state) 461 { 462 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 463 struct mtk_drm_private *priv = crtc->dev->dev_private; 464 unsigned int pending_planes = 0; 465 int i; 466 467 if (mtk_crtc->event) 468 mtk_crtc->pending_needs_vblank = true; 469 for (i = 0; i < mtk_crtc->layer_nr; i++) { 470 struct drm_plane *plane = &mtk_crtc->planes[i]; 471 struct mtk_plane_state *plane_state; 472 473 plane_state = to_mtk_plane_state(plane->state); 474 if (plane_state->pending.dirty) { 475 plane_state->pending.config = true; 476 plane_state->pending.dirty = false; 477 pending_planes |= BIT(i); 478 } 479 } 480 if (pending_planes) 481 mtk_crtc->pending_planes = true; 482 if (crtc->state->color_mgmt_changed) 483 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 484 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 485 486 if (priv->data->shadow_register) { 487 mtk_disp_mutex_acquire(mtk_crtc->mutex); 488 mtk_crtc_ddp_config(crtc); 489 mtk_disp_mutex_release(mtk_crtc->mutex); 490 } 491 } 492 493 static const struct drm_crtc_funcs mtk_crtc_funcs = { 494 .set_config = drm_atomic_helper_set_config, 495 .page_flip = drm_atomic_helper_page_flip, 496 .destroy = mtk_drm_crtc_destroy, 497 .reset = mtk_drm_crtc_reset, 498 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 499 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 500 .gamma_set = drm_atomic_helper_legacy_gamma_set, 501 .enable_vblank = mtk_drm_crtc_enable_vblank, 502 .disable_vblank = mtk_drm_crtc_disable_vblank, 503 }; 504 505 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 506 .mode_fixup = mtk_drm_crtc_mode_fixup, 507 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 508 .atomic_begin = mtk_drm_crtc_atomic_begin, 509 .atomic_flush = mtk_drm_crtc_atomic_flush, 510 .atomic_enable = mtk_drm_crtc_atomic_enable, 511 .atomic_disable = mtk_drm_crtc_atomic_disable, 512 }; 513 514 static int mtk_drm_crtc_init(struct drm_device *drm, 515 struct mtk_drm_crtc *mtk_crtc, 516 struct drm_plane *primary, 517 struct drm_plane *cursor, unsigned int pipe) 518 { 519 int ret; 520 521 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 522 &mtk_crtc_funcs, NULL); 523 if (ret) 524 goto err_cleanup_crtc; 525 526 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 527 528 return 0; 529 530 err_cleanup_crtc: 531 drm_crtc_cleanup(&mtk_crtc->base); 532 return ret; 533 } 534 535 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 536 { 537 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 538 struct mtk_drm_private *priv = crtc->dev->dev_private; 539 540 if (!priv->data->shadow_register) 541 mtk_crtc_ddp_config(crtc); 542 543 mtk_drm_finish_page_flip(mtk_crtc); 544 } 545 546 int mtk_drm_crtc_create(struct drm_device *drm_dev, 547 const enum mtk_ddp_comp_id *path, unsigned int path_len) 548 { 549 struct mtk_drm_private *priv = drm_dev->dev_private; 550 struct device *dev = drm_dev->dev; 551 struct mtk_drm_crtc *mtk_crtc; 552 enum drm_plane_type type; 553 unsigned int zpos; 554 int pipe = priv->num_pipes; 555 int ret; 556 int i; 557 558 if (!path) 559 return 0; 560 561 for (i = 0; i < path_len; i++) { 562 enum mtk_ddp_comp_id comp_id = path[i]; 563 struct device_node *node; 564 565 node = priv->comp_node[comp_id]; 566 if (!node) { 567 dev_info(dev, 568 "Not creating crtc %d because component %d is disabled or missing\n", 569 pipe, comp_id); 570 return 0; 571 } 572 } 573 574 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 575 if (!mtk_crtc) 576 return -ENOMEM; 577 578 mtk_crtc->config_regs = priv->config_regs; 579 mtk_crtc->ddp_comp_nr = path_len; 580 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 581 sizeof(*mtk_crtc->ddp_comp), 582 GFP_KERNEL); 583 if (!mtk_crtc->ddp_comp) 584 return -ENOMEM; 585 586 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 587 if (IS_ERR(mtk_crtc->mutex)) { 588 ret = PTR_ERR(mtk_crtc->mutex); 589 dev_err(dev, "Failed to get mutex: %d\n", ret); 590 return ret; 591 } 592 593 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 594 enum mtk_ddp_comp_id comp_id = path[i]; 595 struct mtk_ddp_comp *comp; 596 struct device_node *node; 597 598 node = priv->comp_node[comp_id]; 599 comp = priv->ddp_comp[comp_id]; 600 if (!comp) { 601 dev_err(dev, "Component %pOF not initialized\n", node); 602 ret = -ENODEV; 603 return ret; 604 } 605 606 mtk_crtc->ddp_comp[i] = comp; 607 } 608 609 mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]); 610 if (mtk_crtc->ddp_comp_nr > 1) { 611 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[1]; 612 613 if (comp->funcs->bgclr_in_on) 614 mtk_crtc->layer_nr += mtk_ddp_comp_layer_nr(comp); 615 } 616 mtk_crtc->planes = devm_kcalloc(dev, mtk_crtc->layer_nr, 617 sizeof(struct drm_plane), 618 GFP_KERNEL); 619 620 for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) { 621 type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY : 622 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR : 623 DRM_PLANE_TYPE_OVERLAY; 624 ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos], 625 BIT(pipe), type); 626 if (ret) 627 return ret; 628 } 629 630 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0], 631 mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] : 632 NULL, pipe); 633 if (ret < 0) 634 return ret; 635 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); 636 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); 637 priv->num_pipes++; 638 639 return 0; 640 } 641