1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 #include <linux/soc/mediatek/mtk-cmdq.h> 9 #include <linux/soc/mediatek/mtk-mmsys.h> 10 11 #include <asm/barrier.h> 12 #include <soc/mediatek/smi.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_plane_helper.h> 16 #include <drm/drm_probe_helper.h> 17 #include <drm/drm_vblank.h> 18 19 #include "mtk_drm_drv.h" 20 #include "mtk_drm_crtc.h" 21 #include "mtk_drm_ddp.h" 22 #include "mtk_drm_ddp_comp.h" 23 #include "mtk_drm_gem.h" 24 #include "mtk_drm_plane.h" 25 26 /** 27 * struct mtk_drm_crtc - MediaTek specific crtc structure. 28 * @base: crtc object. 29 * @enabled: records whether crtc_enable succeeded 30 * @planes: array of 4 drm_plane structures, one for each overlay plane 31 * @pending_planes: whether any plane has pending changes to be applied 32 * @mmsys_dev: pointer to the mmsys device for configuration registers 33 * @mutex: handle to one of the ten disp_mutex streams 34 * @ddp_comp_nr: number of components in ddp_comp 35 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 36 */ 37 struct mtk_drm_crtc { 38 struct drm_crtc base; 39 bool enabled; 40 41 bool pending_needs_vblank; 42 struct drm_pending_vblank_event *event; 43 44 struct drm_plane *planes; 45 unsigned int layer_nr; 46 bool pending_planes; 47 bool pending_async_planes; 48 49 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 50 struct cmdq_client *cmdq_client; 51 u32 cmdq_event; 52 #endif 53 54 struct device *mmsys_dev; 55 struct mtk_disp_mutex *mutex; 56 unsigned int ddp_comp_nr; 57 struct mtk_ddp_comp **ddp_comp; 58 59 /* lock for display hardware access */ 60 struct mutex hw_lock; 61 }; 62 63 struct mtk_crtc_state { 64 struct drm_crtc_state base; 65 66 bool pending_config; 67 unsigned int pending_width; 68 unsigned int pending_height; 69 unsigned int pending_vrefresh; 70 }; 71 72 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 73 { 74 return container_of(c, struct mtk_drm_crtc, base); 75 } 76 77 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 78 { 79 return container_of(s, struct mtk_crtc_state, base); 80 } 81 82 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 83 { 84 struct drm_crtc *crtc = &mtk_crtc->base; 85 unsigned long flags; 86 87 spin_lock_irqsave(&crtc->dev->event_lock, flags); 88 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 89 drm_crtc_vblank_put(crtc); 90 mtk_crtc->event = NULL; 91 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 92 } 93 94 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 95 { 96 drm_crtc_handle_vblank(&mtk_crtc->base); 97 if (mtk_crtc->pending_needs_vblank) { 98 mtk_drm_crtc_finish_page_flip(mtk_crtc); 99 mtk_crtc->pending_needs_vblank = false; 100 } 101 } 102 103 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 104 { 105 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 106 107 mtk_disp_mutex_put(mtk_crtc->mutex); 108 109 drm_crtc_cleanup(crtc); 110 } 111 112 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 113 { 114 struct mtk_crtc_state *state; 115 116 if (crtc->state) { 117 __drm_atomic_helper_crtc_destroy_state(crtc->state); 118 119 state = to_mtk_crtc_state(crtc->state); 120 memset(state, 0, sizeof(*state)); 121 } else { 122 state = kzalloc(sizeof(*state), GFP_KERNEL); 123 if (!state) 124 return; 125 crtc->state = &state->base; 126 } 127 128 state->base.crtc = crtc; 129 } 130 131 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 132 { 133 struct mtk_crtc_state *state; 134 135 state = kzalloc(sizeof(*state), GFP_KERNEL); 136 if (!state) 137 return NULL; 138 139 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 140 141 WARN_ON(state->base.crtc != crtc); 142 state->base.crtc = crtc; 143 144 return &state->base; 145 } 146 147 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 148 struct drm_crtc_state *state) 149 { 150 __drm_atomic_helper_crtc_destroy_state(state); 151 kfree(to_mtk_crtc_state(state)); 152 } 153 154 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 155 const struct drm_display_mode *mode, 156 struct drm_display_mode *adjusted_mode) 157 { 158 /* Nothing to do here, but this callback is mandatory. */ 159 return true; 160 } 161 162 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 163 { 164 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 165 166 state->pending_width = crtc->mode.hdisplay; 167 state->pending_height = crtc->mode.vdisplay; 168 state->pending_vrefresh = crtc->mode.vrefresh; 169 wmb(); /* Make sure the above parameters are set before update */ 170 state->pending_config = true; 171 } 172 173 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 174 { 175 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 176 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 177 178 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 179 180 return 0; 181 } 182 183 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 184 { 185 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 186 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 187 188 mtk_ddp_comp_disable_vblank(comp); 189 } 190 191 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 192 { 193 int ret; 194 int i; 195 196 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 197 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 198 if (ret) { 199 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 200 goto err; 201 } 202 } 203 204 return 0; 205 err: 206 while (--i >= 0) 207 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 208 return ret; 209 } 210 211 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 212 { 213 int i; 214 215 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 216 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 217 } 218 219 static 220 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 221 struct drm_plane *plane, 222 unsigned int *local_layer) 223 { 224 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 225 struct mtk_ddp_comp *comp; 226 int i, count = 0; 227 unsigned int local_index = plane - mtk_crtc->planes; 228 229 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 230 comp = mtk_crtc->ddp_comp[i]; 231 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 232 *local_layer = local_index - count; 233 return comp; 234 } 235 count += mtk_ddp_comp_layer_nr(comp); 236 } 237 238 WARN(1, "Failed to find component for plane %d\n", plane->index); 239 return NULL; 240 } 241 242 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 243 static void ddp_cmdq_cb(struct cmdq_cb_data data) 244 { 245 cmdq_pkt_destroy(data.data); 246 } 247 #endif 248 249 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 250 { 251 struct drm_crtc *crtc = &mtk_crtc->base; 252 struct drm_connector *connector; 253 struct drm_encoder *encoder; 254 struct drm_connector_list_iter conn_iter; 255 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 256 int ret; 257 int i; 258 259 if (WARN_ON(!crtc->state)) 260 return -EINVAL; 261 262 width = crtc->state->adjusted_mode.hdisplay; 263 height = crtc->state->adjusted_mode.vdisplay; 264 vrefresh = crtc->state->adjusted_mode.vrefresh; 265 266 drm_for_each_encoder(encoder, crtc->dev) { 267 if (encoder->crtc != crtc) 268 continue; 269 270 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 271 drm_for_each_connector_iter(connector, &conn_iter) { 272 if (connector->encoder != encoder) 273 continue; 274 if (connector->display_info.bpc != 0 && 275 bpc > connector->display_info.bpc) 276 bpc = connector->display_info.bpc; 277 } 278 drm_connector_list_iter_end(&conn_iter); 279 } 280 281 ret = pm_runtime_get_sync(crtc->dev->dev); 282 if (ret < 0) { 283 DRM_ERROR("Failed to enable power domain: %d\n", ret); 284 return ret; 285 } 286 287 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 288 if (ret < 0) { 289 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 290 goto err_pm_runtime_put; 291 } 292 293 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 294 if (ret < 0) { 295 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 296 goto err_mutex_unprepare; 297 } 298 299 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 300 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 301 mtk_crtc->ddp_comp[i]->id, 302 mtk_crtc->ddp_comp[i + 1]->id); 303 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 304 mtk_crtc->ddp_comp[i]->id); 305 } 306 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 307 mtk_disp_mutex_enable(mtk_crtc->mutex); 308 309 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 310 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 311 312 if (i == 1) 313 mtk_ddp_comp_bgclr_in_on(comp); 314 315 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 316 mtk_ddp_comp_start(comp); 317 } 318 319 /* Initially configure all planes */ 320 for (i = 0; i < mtk_crtc->layer_nr; i++) { 321 struct drm_plane *plane = &mtk_crtc->planes[i]; 322 struct mtk_plane_state *plane_state; 323 struct mtk_ddp_comp *comp; 324 unsigned int local_layer; 325 326 plane_state = to_mtk_plane_state(plane->state); 327 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 328 if (comp) 329 mtk_ddp_comp_layer_config(comp, local_layer, 330 plane_state, NULL); 331 } 332 333 return 0; 334 335 err_mutex_unprepare: 336 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 337 err_pm_runtime_put: 338 pm_runtime_put(crtc->dev->dev); 339 return ret; 340 } 341 342 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 343 { 344 struct drm_device *drm = mtk_crtc->base.dev; 345 struct drm_crtc *crtc = &mtk_crtc->base; 346 int i; 347 348 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 349 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 350 if (i == 1) 351 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 352 } 353 354 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 355 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 356 mtk_crtc->ddp_comp[i]->id); 357 mtk_disp_mutex_disable(mtk_crtc->mutex); 358 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 359 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 360 mtk_crtc->ddp_comp[i]->id, 361 mtk_crtc->ddp_comp[i + 1]->id); 362 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 363 mtk_crtc->ddp_comp[i]->id); 364 } 365 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 366 mtk_crtc_ddp_clk_disable(mtk_crtc); 367 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 368 369 pm_runtime_put(drm->dev); 370 371 if (crtc->state->event && !crtc->state->active) { 372 spin_lock_irq(&crtc->dev->event_lock); 373 drm_crtc_send_vblank_event(crtc, crtc->state->event); 374 crtc->state->event = NULL; 375 spin_unlock_irq(&crtc->dev->event_lock); 376 } 377 } 378 379 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 380 struct cmdq_pkt *cmdq_handle) 381 { 382 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 383 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 384 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 385 unsigned int i; 386 unsigned int local_layer; 387 388 /* 389 * TODO: instead of updating the registers here, we should prepare 390 * working registers in atomic_commit and let the hardware command 391 * queue update module registers on vblank. 392 */ 393 if (state->pending_config) { 394 mtk_ddp_comp_config(comp, state->pending_width, 395 state->pending_height, 396 state->pending_vrefresh, 0, 397 cmdq_handle); 398 399 state->pending_config = false; 400 } 401 402 if (mtk_crtc->pending_planes) { 403 for (i = 0; i < mtk_crtc->layer_nr; i++) { 404 struct drm_plane *plane = &mtk_crtc->planes[i]; 405 struct mtk_plane_state *plane_state; 406 407 plane_state = to_mtk_plane_state(plane->state); 408 409 if (!plane_state->pending.config) 410 continue; 411 412 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 413 &local_layer); 414 415 if (comp) 416 mtk_ddp_comp_layer_config(comp, local_layer, 417 plane_state, 418 cmdq_handle); 419 plane_state->pending.config = false; 420 } 421 mtk_crtc->pending_planes = false; 422 } 423 424 if (mtk_crtc->pending_async_planes) { 425 for (i = 0; i < mtk_crtc->layer_nr; i++) { 426 struct drm_plane *plane = &mtk_crtc->planes[i]; 427 struct mtk_plane_state *plane_state; 428 429 plane_state = to_mtk_plane_state(plane->state); 430 431 if (!plane_state->pending.async_config) 432 continue; 433 434 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 435 &local_layer); 436 437 if (comp) 438 mtk_ddp_comp_layer_config(comp, local_layer, 439 plane_state, 440 cmdq_handle); 441 plane_state->pending.async_config = false; 442 } 443 mtk_crtc->pending_async_planes = false; 444 } 445 } 446 447 static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) 448 { 449 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 450 struct cmdq_pkt *cmdq_handle; 451 #endif 452 struct drm_crtc *crtc = &mtk_crtc->base; 453 struct mtk_drm_private *priv = crtc->dev->dev_private; 454 unsigned int pending_planes = 0, pending_async_planes = 0; 455 int i; 456 457 mutex_lock(&mtk_crtc->hw_lock); 458 for (i = 0; i < mtk_crtc->layer_nr; i++) { 459 struct drm_plane *plane = &mtk_crtc->planes[i]; 460 struct mtk_plane_state *plane_state; 461 462 plane_state = to_mtk_plane_state(plane->state); 463 if (plane_state->pending.dirty) { 464 plane_state->pending.config = true; 465 plane_state->pending.dirty = false; 466 pending_planes |= BIT(i); 467 } else if (plane_state->pending.async_dirty) { 468 plane_state->pending.async_config = true; 469 plane_state->pending.async_dirty = false; 470 pending_async_planes |= BIT(i); 471 } 472 } 473 if (pending_planes) 474 mtk_crtc->pending_planes = true; 475 if (pending_async_planes) 476 mtk_crtc->pending_async_planes = true; 477 478 if (priv->data->shadow_register) { 479 mtk_disp_mutex_acquire(mtk_crtc->mutex); 480 mtk_crtc_ddp_config(crtc, NULL); 481 mtk_disp_mutex_release(mtk_crtc->mutex); 482 } 483 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 484 if (mtk_crtc->cmdq_client) { 485 mbox_flush(mtk_crtc->cmdq_client->chan, 2000); 486 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); 487 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 488 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event); 489 mtk_crtc_ddp_config(crtc, cmdq_handle); 490 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); 491 } 492 #endif 493 mutex_unlock(&mtk_crtc->hw_lock); 494 } 495 496 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 497 struct mtk_plane_state *state) 498 { 499 unsigned int local_layer; 500 struct mtk_ddp_comp *comp; 501 502 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 503 if (comp) 504 return mtk_ddp_comp_layer_check(comp, local_layer, state); 505 return 0; 506 } 507 508 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 509 struct drm_plane_state *new_state) 510 { 511 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 512 const struct drm_plane_helper_funcs *plane_helper_funcs = 513 plane->helper_private; 514 515 if (!mtk_crtc->enabled) 516 return; 517 518 plane_helper_funcs->atomic_update(plane, new_state); 519 mtk_drm_crtc_hw_config(mtk_crtc); 520 } 521 522 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 523 struct drm_crtc_state *old_state) 524 { 525 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 526 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 527 int ret; 528 529 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 530 531 ret = mtk_smi_larb_get(comp->larb_dev); 532 if (ret) { 533 DRM_ERROR("Failed to get larb: %d\n", ret); 534 return; 535 } 536 537 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 538 if (ret) { 539 mtk_smi_larb_put(comp->larb_dev); 540 return; 541 } 542 543 drm_crtc_vblank_on(crtc); 544 mtk_crtc->enabled = true; 545 } 546 547 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 548 struct drm_crtc_state *old_state) 549 { 550 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 551 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 552 int i; 553 554 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 555 if (!mtk_crtc->enabled) 556 return; 557 558 /* Set all pending plane state to disabled */ 559 for (i = 0; i < mtk_crtc->layer_nr; i++) { 560 struct drm_plane *plane = &mtk_crtc->planes[i]; 561 struct mtk_plane_state *plane_state; 562 563 plane_state = to_mtk_plane_state(plane->state); 564 plane_state->pending.enable = false; 565 plane_state->pending.config = true; 566 } 567 mtk_crtc->pending_planes = true; 568 569 mtk_drm_crtc_hw_config(mtk_crtc); 570 /* Wait for planes to be disabled */ 571 drm_crtc_wait_one_vblank(crtc); 572 573 drm_crtc_vblank_off(crtc); 574 mtk_crtc_ddp_hw_fini(mtk_crtc); 575 mtk_smi_larb_put(comp->larb_dev); 576 577 mtk_crtc->enabled = false; 578 } 579 580 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 581 struct drm_crtc_state *old_crtc_state) 582 { 583 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 584 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 585 586 if (mtk_crtc->event && state->base.event) 587 DRM_ERROR("new event while there is still a pending event\n"); 588 589 if (state->base.event) { 590 state->base.event->pipe = drm_crtc_index(crtc); 591 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 592 mtk_crtc->event = state->base.event; 593 state->base.event = NULL; 594 } 595 } 596 597 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 598 struct drm_crtc_state *old_crtc_state) 599 { 600 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 601 int i; 602 603 if (mtk_crtc->event) 604 mtk_crtc->pending_needs_vblank = true; 605 if (crtc->state->color_mgmt_changed) 606 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 607 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 608 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 609 } 610 mtk_drm_crtc_hw_config(mtk_crtc); 611 } 612 613 static const struct drm_crtc_funcs mtk_crtc_funcs = { 614 .set_config = drm_atomic_helper_set_config, 615 .page_flip = drm_atomic_helper_page_flip, 616 .destroy = mtk_drm_crtc_destroy, 617 .reset = mtk_drm_crtc_reset, 618 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 619 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 620 .gamma_set = drm_atomic_helper_legacy_gamma_set, 621 .enable_vblank = mtk_drm_crtc_enable_vblank, 622 .disable_vblank = mtk_drm_crtc_disable_vblank, 623 }; 624 625 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 626 .mode_fixup = mtk_drm_crtc_mode_fixup, 627 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 628 .atomic_begin = mtk_drm_crtc_atomic_begin, 629 .atomic_flush = mtk_drm_crtc_atomic_flush, 630 .atomic_enable = mtk_drm_crtc_atomic_enable, 631 .atomic_disable = mtk_drm_crtc_atomic_disable, 632 }; 633 634 static int mtk_drm_crtc_init(struct drm_device *drm, 635 struct mtk_drm_crtc *mtk_crtc, 636 unsigned int pipe) 637 { 638 struct drm_plane *primary = NULL; 639 struct drm_plane *cursor = NULL; 640 int i, ret; 641 642 for (i = 0; i < mtk_crtc->layer_nr; i++) { 643 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 644 primary = &mtk_crtc->planes[i]; 645 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 646 cursor = &mtk_crtc->planes[i]; 647 } 648 649 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 650 &mtk_crtc_funcs, NULL); 651 if (ret) 652 goto err_cleanup_crtc; 653 654 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 655 656 return 0; 657 658 err_cleanup_crtc: 659 drm_crtc_cleanup(&mtk_crtc->base); 660 return ret; 661 } 662 663 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 664 { 665 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 666 struct mtk_drm_private *priv = crtc->dev->dev_private; 667 668 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 669 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) 670 #else 671 if (!priv->data->shadow_register) 672 #endif 673 mtk_crtc_ddp_config(crtc, NULL); 674 675 mtk_drm_finish_page_flip(mtk_crtc); 676 } 677 678 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 679 int comp_idx) 680 { 681 struct mtk_ddp_comp *comp; 682 683 if (comp_idx > 1) 684 return 0; 685 686 comp = mtk_crtc->ddp_comp[comp_idx]; 687 if (!comp->funcs) 688 return 0; 689 690 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 691 return 0; 692 693 return mtk_ddp_comp_layer_nr(comp); 694 } 695 696 static inline 697 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 698 unsigned int num_planes) 699 { 700 if (plane_idx == 0) 701 return DRM_PLANE_TYPE_PRIMARY; 702 else if (plane_idx == (num_planes - 1)) 703 return DRM_PLANE_TYPE_CURSOR; 704 else 705 return DRM_PLANE_TYPE_OVERLAY; 706 707 } 708 709 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 710 struct mtk_drm_crtc *mtk_crtc, 711 int comp_idx, int pipe) 712 { 713 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 714 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 715 int i, ret; 716 717 for (i = 0; i < num_planes; i++) { 718 ret = mtk_plane_init(drm_dev, 719 &mtk_crtc->planes[mtk_crtc->layer_nr], 720 BIT(pipe), 721 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 722 num_planes), 723 mtk_ddp_comp_supported_rotations(comp)); 724 if (ret) 725 return ret; 726 727 mtk_crtc->layer_nr++; 728 } 729 return 0; 730 } 731 732 int mtk_drm_crtc_create(struct drm_device *drm_dev, 733 const enum mtk_ddp_comp_id *path, unsigned int path_len) 734 { 735 struct mtk_drm_private *priv = drm_dev->dev_private; 736 struct device *dev = drm_dev->dev; 737 struct mtk_drm_crtc *mtk_crtc; 738 unsigned int num_comp_planes = 0; 739 int pipe = priv->num_pipes; 740 int ret; 741 int i; 742 bool has_ctm = false; 743 uint gamma_lut_size = 0; 744 745 if (!path) 746 return 0; 747 748 for (i = 0; i < path_len; i++) { 749 enum mtk_ddp_comp_id comp_id = path[i]; 750 struct device_node *node; 751 752 node = priv->comp_node[comp_id]; 753 if (!node) { 754 dev_info(dev, 755 "Not creating crtc %d because component %d is disabled or missing\n", 756 pipe, comp_id); 757 return 0; 758 } 759 } 760 761 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 762 if (!mtk_crtc) 763 return -ENOMEM; 764 765 mtk_crtc->mmsys_dev = priv->mmsys_dev; 766 mtk_crtc->ddp_comp_nr = path_len; 767 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 768 sizeof(*mtk_crtc->ddp_comp), 769 GFP_KERNEL); 770 if (!mtk_crtc->ddp_comp) 771 return -ENOMEM; 772 773 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 774 if (IS_ERR(mtk_crtc->mutex)) { 775 ret = PTR_ERR(mtk_crtc->mutex); 776 dev_err(dev, "Failed to get mutex: %d\n", ret); 777 return ret; 778 } 779 780 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 781 enum mtk_ddp_comp_id comp_id = path[i]; 782 struct mtk_ddp_comp *comp; 783 struct device_node *node; 784 785 node = priv->comp_node[comp_id]; 786 comp = priv->ddp_comp[comp_id]; 787 if (!comp) { 788 dev_err(dev, "Component %pOF not initialized\n", node); 789 ret = -ENODEV; 790 return ret; 791 } 792 793 mtk_crtc->ddp_comp[i] = comp; 794 795 if (comp->funcs) { 796 if (comp->funcs->gamma_set) 797 gamma_lut_size = MTK_LUT_SIZE; 798 799 if (comp->funcs->ctm_set) 800 has_ctm = true; 801 } 802 } 803 804 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 805 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 806 807 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 808 sizeof(struct drm_plane), GFP_KERNEL); 809 810 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 811 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 812 pipe); 813 if (ret) 814 return ret; 815 } 816 817 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe); 818 if (ret < 0) 819 return ret; 820 821 if (gamma_lut_size) 822 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 823 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 824 priv->num_pipes++; 825 mutex_init(&mtk_crtc->hw_lock); 826 827 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 828 mtk_crtc->cmdq_client = 829 cmdq_mbox_create(mtk_crtc->mmsys_dev, 830 drm_crtc_index(&mtk_crtc->base), 831 2000); 832 if (IS_ERR(mtk_crtc->cmdq_client)) { 833 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 834 drm_crtc_index(&mtk_crtc->base)); 835 mtk_crtc->cmdq_client = NULL; 836 } 837 ret = of_property_read_u32_index(priv->mutex_node, 838 "mediatek,gce-events", 839 drm_crtc_index(&mtk_crtc->base), 840 &mtk_crtc->cmdq_event); 841 if (ret) 842 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 843 drm_crtc_index(&mtk_crtc->base)); 844 #endif 845 return 0; 846 } 847