1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/mailbox_controller.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/soc/mediatek/mtk-cmdq.h> 11 #include <linux/soc/mediatek/mtk-mmsys.h> 12 #include <linux/soc/mediatek/mtk-mutex.h> 13 14 #include <asm/barrier.h> 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_vblank.h> 20 21 #include "mtk_drm_drv.h" 22 #include "mtk_drm_crtc.h" 23 #include "mtk_drm_ddp_comp.h" 24 #include "mtk_drm_gem.h" 25 #include "mtk_drm_plane.h" 26 27 /* 28 * struct mtk_drm_crtc - MediaTek specific crtc structure. 29 * @base: crtc object. 30 * @enabled: records whether crtc_enable succeeded 31 * @planes: array of 4 drm_plane structures, one for each overlay plane 32 * @pending_planes: whether any plane has pending changes to be applied 33 * @mmsys_dev: pointer to the mmsys device for configuration registers 34 * @mutex: handle to one of the ten disp_mutex streams 35 * @ddp_comp_nr: number of components in ddp_comp 36 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 37 * 38 * TODO: Needs update: this header is missing a bunch of member descriptions. 39 */ 40 struct mtk_drm_crtc { 41 struct drm_crtc base; 42 bool enabled; 43 44 bool pending_needs_vblank; 45 struct drm_pending_vblank_event *event; 46 47 struct drm_plane *planes; 48 unsigned int layer_nr; 49 bool pending_planes; 50 bool pending_async_planes; 51 52 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 53 struct cmdq_client cmdq_client; 54 struct cmdq_pkt cmdq_handle; 55 u32 cmdq_event; 56 u32 cmdq_vblank_cnt; 57 wait_queue_head_t cb_blocking_queue; 58 #endif 59 60 struct device *mmsys_dev; 61 struct device *dma_dev; 62 struct mtk_mutex *mutex; 63 unsigned int ddp_comp_nr; 64 struct mtk_ddp_comp **ddp_comp; 65 66 /* lock for display hardware access */ 67 struct mutex hw_lock; 68 bool config_updating; 69 }; 70 71 struct mtk_crtc_state { 72 struct drm_crtc_state base; 73 74 bool pending_config; 75 unsigned int pending_width; 76 unsigned int pending_height; 77 unsigned int pending_vrefresh; 78 }; 79 80 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 81 { 82 return container_of(c, struct mtk_drm_crtc, base); 83 } 84 85 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 86 { 87 return container_of(s, struct mtk_crtc_state, base); 88 } 89 90 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 91 { 92 struct drm_crtc *crtc = &mtk_crtc->base; 93 unsigned long flags; 94 95 spin_lock_irqsave(&crtc->dev->event_lock, flags); 96 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 97 drm_crtc_vblank_put(crtc); 98 mtk_crtc->event = NULL; 99 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 100 } 101 102 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 103 { 104 drm_crtc_handle_vblank(&mtk_crtc->base); 105 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) { 106 mtk_drm_crtc_finish_page_flip(mtk_crtc); 107 mtk_crtc->pending_needs_vblank = false; 108 } 109 } 110 111 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 112 static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, 113 size_t size) 114 { 115 struct device *dev; 116 dma_addr_t dma_addr; 117 118 pkt->va_base = kzalloc(size, GFP_KERNEL); 119 if (!pkt->va_base) { 120 kfree(pkt); 121 return -ENOMEM; 122 } 123 pkt->buf_size = size; 124 pkt->cl = (void *)client; 125 126 dev = client->chan->mbox->dev; 127 dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size, 128 DMA_TO_DEVICE); 129 if (dma_mapping_error(dev, dma_addr)) { 130 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size); 131 kfree(pkt->va_base); 132 kfree(pkt); 133 return -ENOMEM; 134 } 135 136 pkt->pa_base = dma_addr; 137 138 return 0; 139 } 140 141 static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt) 142 { 143 struct cmdq_client *client = (struct cmdq_client *)pkt->cl; 144 145 dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size, 146 DMA_TO_DEVICE); 147 kfree(pkt->va_base); 148 kfree(pkt); 149 } 150 #endif 151 152 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 153 { 154 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 155 int i; 156 157 mtk_mutex_put(mtk_crtc->mutex); 158 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 159 mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle); 160 161 if (mtk_crtc->cmdq_client.chan) { 162 mbox_free_channel(mtk_crtc->cmdq_client.chan); 163 mtk_crtc->cmdq_client.chan = NULL; 164 } 165 #endif 166 167 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 168 struct mtk_ddp_comp *comp; 169 170 comp = mtk_crtc->ddp_comp[i]; 171 mtk_ddp_comp_unregister_vblank_cb(comp); 172 } 173 174 drm_crtc_cleanup(crtc); 175 } 176 177 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 178 { 179 struct mtk_crtc_state *state; 180 181 if (crtc->state) 182 __drm_atomic_helper_crtc_destroy_state(crtc->state); 183 184 kfree(to_mtk_crtc_state(crtc->state)); 185 crtc->state = NULL; 186 187 state = kzalloc(sizeof(*state), GFP_KERNEL); 188 if (state) 189 __drm_atomic_helper_crtc_reset(crtc, &state->base); 190 } 191 192 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 193 { 194 struct mtk_crtc_state *state; 195 196 state = kmalloc(sizeof(*state), GFP_KERNEL); 197 if (!state) 198 return NULL; 199 200 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 201 202 WARN_ON(state->base.crtc != crtc); 203 state->base.crtc = crtc; 204 state->pending_config = false; 205 206 return &state->base; 207 } 208 209 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 210 struct drm_crtc_state *state) 211 { 212 __drm_atomic_helper_crtc_destroy_state(state); 213 kfree(to_mtk_crtc_state(state)); 214 } 215 216 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 217 const struct drm_display_mode *mode, 218 struct drm_display_mode *adjusted_mode) 219 { 220 /* Nothing to do here, but this callback is mandatory. */ 221 return true; 222 } 223 224 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 225 { 226 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 227 228 state->pending_width = crtc->mode.hdisplay; 229 state->pending_height = crtc->mode.vdisplay; 230 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode); 231 wmb(); /* Make sure the above parameters are set before update */ 232 state->pending_config = true; 233 } 234 235 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 236 { 237 int ret; 238 int i; 239 240 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 241 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); 242 if (ret) { 243 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 244 goto err; 245 } 246 } 247 248 return 0; 249 err: 250 while (--i >= 0) 251 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 252 return ret; 253 } 254 255 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 256 { 257 int i; 258 259 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 260 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 261 } 262 263 static 264 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 265 struct drm_plane *plane, 266 unsigned int *local_layer) 267 { 268 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 269 struct mtk_ddp_comp *comp; 270 int i, count = 0; 271 unsigned int local_index = plane - mtk_crtc->planes; 272 273 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 274 comp = mtk_crtc->ddp_comp[i]; 275 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 276 *local_layer = local_index - count; 277 return comp; 278 } 279 count += mtk_ddp_comp_layer_nr(comp); 280 } 281 282 WARN(1, "Failed to find component for plane %d\n", plane->index); 283 return NULL; 284 } 285 286 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 287 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) 288 { 289 struct cmdq_cb_data *data = mssg; 290 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client); 291 struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client); 292 struct mtk_crtc_state *state; 293 unsigned int i; 294 295 if (data->sta < 0) 296 return; 297 298 state = to_mtk_crtc_state(mtk_crtc->base.state); 299 300 state->pending_config = false; 301 302 if (mtk_crtc->pending_planes) { 303 for (i = 0; i < mtk_crtc->layer_nr; i++) { 304 struct drm_plane *plane = &mtk_crtc->planes[i]; 305 struct mtk_plane_state *plane_state; 306 307 plane_state = to_mtk_plane_state(plane->state); 308 309 plane_state->pending.config = false; 310 } 311 mtk_crtc->pending_planes = false; 312 } 313 314 if (mtk_crtc->pending_async_planes) { 315 for (i = 0; i < mtk_crtc->layer_nr; i++) { 316 struct drm_plane *plane = &mtk_crtc->planes[i]; 317 struct mtk_plane_state *plane_state; 318 319 plane_state = to_mtk_plane_state(plane->state); 320 321 plane_state->pending.async_config = false; 322 } 323 mtk_crtc->pending_async_planes = false; 324 } 325 326 mtk_crtc->cmdq_vblank_cnt = 0; 327 wake_up(&mtk_crtc->cb_blocking_queue); 328 } 329 #endif 330 331 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 332 { 333 struct drm_crtc *crtc = &mtk_crtc->base; 334 struct drm_connector *connector; 335 struct drm_encoder *encoder; 336 struct drm_connector_list_iter conn_iter; 337 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 338 int ret; 339 int i; 340 341 if (WARN_ON(!crtc->state)) 342 return -EINVAL; 343 344 width = crtc->state->adjusted_mode.hdisplay; 345 height = crtc->state->adjusted_mode.vdisplay; 346 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode); 347 348 drm_for_each_encoder(encoder, crtc->dev) { 349 if (encoder->crtc != crtc) 350 continue; 351 352 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 353 drm_for_each_connector_iter(connector, &conn_iter) { 354 if (connector->encoder != encoder) 355 continue; 356 if (connector->display_info.bpc != 0 && 357 bpc > connector->display_info.bpc) 358 bpc = connector->display_info.bpc; 359 } 360 drm_connector_list_iter_end(&conn_iter); 361 } 362 363 ret = pm_runtime_resume_and_get(crtc->dev->dev); 364 if (ret < 0) { 365 DRM_ERROR("Failed to enable power domain: %d\n", ret); 366 return ret; 367 } 368 369 ret = mtk_mutex_prepare(mtk_crtc->mutex); 370 if (ret < 0) { 371 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 372 goto err_pm_runtime_put; 373 } 374 375 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 376 if (ret < 0) { 377 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 378 goto err_mutex_unprepare; 379 } 380 381 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 382 if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 383 mtk_crtc->ddp_comp[i + 1]->id)) 384 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 385 mtk_crtc->ddp_comp[i]->id, 386 mtk_crtc->ddp_comp[i + 1]->id); 387 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 388 mtk_mutex_add_comp(mtk_crtc->mutex, 389 mtk_crtc->ddp_comp[i]->id); 390 } 391 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 392 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 393 mtk_mutex_enable(mtk_crtc->mutex); 394 395 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 396 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 397 398 if (i == 1) 399 mtk_ddp_comp_bgclr_in_on(comp); 400 401 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 402 mtk_ddp_comp_start(comp); 403 } 404 405 /* Initially configure all planes */ 406 for (i = 0; i < mtk_crtc->layer_nr; i++) { 407 struct drm_plane *plane = &mtk_crtc->planes[i]; 408 struct mtk_plane_state *plane_state; 409 struct mtk_ddp_comp *comp; 410 unsigned int local_layer; 411 412 plane_state = to_mtk_plane_state(plane->state); 413 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 414 if (comp) 415 mtk_ddp_comp_layer_config(comp, local_layer, 416 plane_state, NULL); 417 } 418 419 return 0; 420 421 err_mutex_unprepare: 422 mtk_mutex_unprepare(mtk_crtc->mutex); 423 err_pm_runtime_put: 424 pm_runtime_put(crtc->dev->dev); 425 return ret; 426 } 427 428 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 429 { 430 struct drm_device *drm = mtk_crtc->base.dev; 431 struct drm_crtc *crtc = &mtk_crtc->base; 432 int i; 433 434 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 435 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 436 if (i == 1) 437 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 438 } 439 440 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 441 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 442 mtk_mutex_remove_comp(mtk_crtc->mutex, 443 mtk_crtc->ddp_comp[i]->id); 444 mtk_mutex_disable(mtk_crtc->mutex); 445 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 446 if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 447 mtk_crtc->ddp_comp[i + 1]->id)) 448 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 449 mtk_crtc->ddp_comp[i]->id, 450 mtk_crtc->ddp_comp[i + 1]->id); 451 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 452 mtk_mutex_remove_comp(mtk_crtc->mutex, 453 mtk_crtc->ddp_comp[i]->id); 454 } 455 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 456 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 457 mtk_crtc_ddp_clk_disable(mtk_crtc); 458 mtk_mutex_unprepare(mtk_crtc->mutex); 459 460 pm_runtime_put(drm->dev); 461 462 if (crtc->state->event && !crtc->state->active) { 463 spin_lock_irq(&crtc->dev->event_lock); 464 drm_crtc_send_vblank_event(crtc, crtc->state->event); 465 crtc->state->event = NULL; 466 spin_unlock_irq(&crtc->dev->event_lock); 467 } 468 } 469 470 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 471 struct cmdq_pkt *cmdq_handle) 472 { 473 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 474 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 475 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 476 unsigned int i; 477 unsigned int local_layer; 478 479 /* 480 * TODO: instead of updating the registers here, we should prepare 481 * working registers in atomic_commit and let the hardware command 482 * queue update module registers on vblank. 483 */ 484 if (state->pending_config) { 485 mtk_ddp_comp_config(comp, state->pending_width, 486 state->pending_height, 487 state->pending_vrefresh, 0, 488 cmdq_handle); 489 490 if (!cmdq_handle) 491 state->pending_config = false; 492 } 493 494 if (mtk_crtc->pending_planes) { 495 for (i = 0; i < mtk_crtc->layer_nr; i++) { 496 struct drm_plane *plane = &mtk_crtc->planes[i]; 497 struct mtk_plane_state *plane_state; 498 499 plane_state = to_mtk_plane_state(plane->state); 500 501 if (!plane_state->pending.config) 502 continue; 503 504 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 505 &local_layer); 506 507 if (comp) 508 mtk_ddp_comp_layer_config(comp, local_layer, 509 plane_state, 510 cmdq_handle); 511 if (!cmdq_handle) 512 plane_state->pending.config = false; 513 } 514 515 if (!cmdq_handle) 516 mtk_crtc->pending_planes = false; 517 } 518 519 if (mtk_crtc->pending_async_planes) { 520 for (i = 0; i < mtk_crtc->layer_nr; i++) { 521 struct drm_plane *plane = &mtk_crtc->planes[i]; 522 struct mtk_plane_state *plane_state; 523 524 plane_state = to_mtk_plane_state(plane->state); 525 526 if (!plane_state->pending.async_config) 527 continue; 528 529 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 530 &local_layer); 531 532 if (comp) 533 mtk_ddp_comp_layer_config(comp, local_layer, 534 plane_state, 535 cmdq_handle); 536 if (!cmdq_handle) 537 plane_state->pending.async_config = false; 538 } 539 540 if (!cmdq_handle) 541 mtk_crtc->pending_async_planes = false; 542 } 543 } 544 545 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc, 546 bool needs_vblank) 547 { 548 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 549 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle; 550 #endif 551 struct drm_crtc *crtc = &mtk_crtc->base; 552 struct mtk_drm_private *priv = crtc->dev->dev_private; 553 unsigned int pending_planes = 0, pending_async_planes = 0; 554 int i; 555 556 mutex_lock(&mtk_crtc->hw_lock); 557 mtk_crtc->config_updating = true; 558 if (needs_vblank) 559 mtk_crtc->pending_needs_vblank = true; 560 561 for (i = 0; i < mtk_crtc->layer_nr; i++) { 562 struct drm_plane *plane = &mtk_crtc->planes[i]; 563 struct mtk_plane_state *plane_state; 564 565 plane_state = to_mtk_plane_state(plane->state); 566 if (plane_state->pending.dirty) { 567 plane_state->pending.config = true; 568 plane_state->pending.dirty = false; 569 pending_planes |= BIT(i); 570 } else if (plane_state->pending.async_dirty) { 571 plane_state->pending.async_config = true; 572 plane_state->pending.async_dirty = false; 573 pending_async_planes |= BIT(i); 574 } 575 } 576 if (pending_planes) 577 mtk_crtc->pending_planes = true; 578 if (pending_async_planes) 579 mtk_crtc->pending_async_planes = true; 580 581 if (priv->data->shadow_register) { 582 mtk_mutex_acquire(mtk_crtc->mutex); 583 mtk_crtc_ddp_config(crtc, NULL); 584 mtk_mutex_release(mtk_crtc->mutex); 585 } 586 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 587 if (mtk_crtc->cmdq_client.chan) { 588 mbox_flush(mtk_crtc->cmdq_client.chan, 2000); 589 cmdq_handle->cmd_buf_size = 0; 590 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 591 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); 592 mtk_crtc_ddp_config(crtc, cmdq_handle); 593 cmdq_pkt_finalize(cmdq_handle); 594 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev, 595 cmdq_handle->pa_base, 596 cmdq_handle->cmd_buf_size, 597 DMA_TO_DEVICE); 598 /* 599 * CMDQ command should execute in next 3 vblank. 600 * One vblank interrupt before send message (occasionally) 601 * and one vblank interrupt after cmdq done, 602 * so it's timeout after 3 vblank interrupt. 603 * If it fail to execute in next 3 vblank, timeout happen. 604 */ 605 mtk_crtc->cmdq_vblank_cnt = 3; 606 607 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); 608 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); 609 } 610 #endif 611 mtk_crtc->config_updating = false; 612 mutex_unlock(&mtk_crtc->hw_lock); 613 } 614 615 static void mtk_crtc_ddp_irq(void *data) 616 { 617 struct drm_crtc *crtc = data; 618 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 619 struct mtk_drm_private *priv = crtc->dev->dev_private; 620 621 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 622 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) 623 mtk_crtc_ddp_config(crtc, NULL); 624 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0) 625 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n", 626 drm_crtc_index(&mtk_crtc->base)); 627 #else 628 if (!priv->data->shadow_register) 629 mtk_crtc_ddp_config(crtc, NULL); 630 #endif 631 mtk_drm_finish_page_flip(mtk_crtc); 632 } 633 634 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 635 { 636 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 637 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 638 639 mtk_ddp_comp_enable_vblank(comp); 640 641 return 0; 642 } 643 644 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 645 { 646 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 647 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 648 649 mtk_ddp_comp_disable_vblank(comp); 650 } 651 652 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 653 struct mtk_plane_state *state) 654 { 655 unsigned int local_layer; 656 struct mtk_ddp_comp *comp; 657 658 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 659 if (comp) 660 return mtk_ddp_comp_layer_check(comp, local_layer, state); 661 return 0; 662 } 663 664 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 665 struct drm_atomic_state *state) 666 { 667 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 668 669 if (!mtk_crtc->enabled) 670 return; 671 672 mtk_drm_crtc_update_config(mtk_crtc, false); 673 } 674 675 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 676 struct drm_atomic_state *state) 677 { 678 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 679 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 680 int ret; 681 682 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 683 684 ret = pm_runtime_resume_and_get(comp->dev); 685 if (ret < 0) { 686 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret); 687 return; 688 } 689 690 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 691 if (ret) { 692 pm_runtime_put(comp->dev); 693 return; 694 } 695 696 drm_crtc_vblank_on(crtc); 697 mtk_crtc->enabled = true; 698 } 699 700 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 701 struct drm_atomic_state *state) 702 { 703 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 704 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 705 int i, ret; 706 707 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 708 if (!mtk_crtc->enabled) 709 return; 710 711 /* Set all pending plane state to disabled */ 712 for (i = 0; i < mtk_crtc->layer_nr; i++) { 713 struct drm_plane *plane = &mtk_crtc->planes[i]; 714 struct mtk_plane_state *plane_state; 715 716 plane_state = to_mtk_plane_state(plane->state); 717 plane_state->pending.enable = false; 718 plane_state->pending.config = true; 719 } 720 mtk_crtc->pending_planes = true; 721 722 mtk_drm_crtc_update_config(mtk_crtc, false); 723 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 724 /* Wait for planes to be disabled by cmdq */ 725 if (mtk_crtc->cmdq_client.chan) 726 wait_event_timeout(mtk_crtc->cb_blocking_queue, 727 mtk_crtc->cmdq_vblank_cnt == 0, 728 msecs_to_jiffies(500)); 729 #endif 730 /* Wait for planes to be disabled */ 731 drm_crtc_wait_one_vblank(crtc); 732 733 drm_crtc_vblank_off(crtc); 734 mtk_crtc_ddp_hw_fini(mtk_crtc); 735 ret = pm_runtime_put(comp->dev); 736 if (ret < 0) 737 DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret); 738 739 mtk_crtc->enabled = false; 740 } 741 742 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 743 struct drm_atomic_state *state) 744 { 745 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 746 crtc); 747 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); 748 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 749 750 if (mtk_crtc->event && mtk_crtc_state->base.event) 751 DRM_ERROR("new event while there is still a pending event\n"); 752 753 if (mtk_crtc_state->base.event) { 754 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc); 755 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 756 mtk_crtc->event = mtk_crtc_state->base.event; 757 mtk_crtc_state->base.event = NULL; 758 } 759 } 760 761 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 762 struct drm_atomic_state *state) 763 { 764 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 765 int i; 766 767 if (crtc->state->color_mgmt_changed) 768 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 769 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 770 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 771 } 772 mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event); 773 } 774 775 static const struct drm_crtc_funcs mtk_crtc_funcs = { 776 .set_config = drm_atomic_helper_set_config, 777 .page_flip = drm_atomic_helper_page_flip, 778 .destroy = mtk_drm_crtc_destroy, 779 .reset = mtk_drm_crtc_reset, 780 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 781 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 782 .enable_vblank = mtk_drm_crtc_enable_vblank, 783 .disable_vblank = mtk_drm_crtc_disable_vblank, 784 }; 785 786 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 787 .mode_fixup = mtk_drm_crtc_mode_fixup, 788 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 789 .atomic_begin = mtk_drm_crtc_atomic_begin, 790 .atomic_flush = mtk_drm_crtc_atomic_flush, 791 .atomic_enable = mtk_drm_crtc_atomic_enable, 792 .atomic_disable = mtk_drm_crtc_atomic_disable, 793 }; 794 795 static int mtk_drm_crtc_init(struct drm_device *drm, 796 struct mtk_drm_crtc *mtk_crtc, 797 unsigned int pipe) 798 { 799 struct drm_plane *primary = NULL; 800 struct drm_plane *cursor = NULL; 801 int i, ret; 802 803 for (i = 0; i < mtk_crtc->layer_nr; i++) { 804 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 805 primary = &mtk_crtc->planes[i]; 806 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 807 cursor = &mtk_crtc->planes[i]; 808 } 809 810 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 811 &mtk_crtc_funcs, NULL); 812 if (ret) 813 goto err_cleanup_crtc; 814 815 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 816 817 return 0; 818 819 err_cleanup_crtc: 820 drm_crtc_cleanup(&mtk_crtc->base); 821 return ret; 822 } 823 824 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 825 int comp_idx) 826 { 827 struct mtk_ddp_comp *comp; 828 829 if (comp_idx > 1) 830 return 0; 831 832 comp = mtk_crtc->ddp_comp[comp_idx]; 833 if (!comp->funcs) 834 return 0; 835 836 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 837 return 0; 838 839 return mtk_ddp_comp_layer_nr(comp); 840 } 841 842 static inline 843 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 844 unsigned int num_planes) 845 { 846 if (plane_idx == 0) 847 return DRM_PLANE_TYPE_PRIMARY; 848 else if (plane_idx == (num_planes - 1)) 849 return DRM_PLANE_TYPE_CURSOR; 850 else 851 return DRM_PLANE_TYPE_OVERLAY; 852 853 } 854 855 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 856 struct mtk_drm_crtc *mtk_crtc, 857 int comp_idx, int pipe) 858 { 859 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 860 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 861 int i, ret; 862 863 for (i = 0; i < num_planes; i++) { 864 ret = mtk_plane_init(drm_dev, 865 &mtk_crtc->planes[mtk_crtc->layer_nr], 866 BIT(pipe), 867 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 868 num_planes), 869 mtk_ddp_comp_supported_rotations(comp), 870 mtk_ddp_comp_get_formats(comp), 871 mtk_ddp_comp_get_num_formats(comp)); 872 if (ret) 873 return ret; 874 875 mtk_crtc->layer_nr++; 876 } 877 return 0; 878 } 879 880 struct device *mtk_drm_crtc_dma_dev_get(struct drm_crtc *crtc) 881 { 882 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 883 884 return mtk_crtc->dma_dev; 885 } 886 887 int mtk_drm_crtc_create(struct drm_device *drm_dev, 888 const unsigned int *path, unsigned int path_len, 889 int priv_data_index) 890 { 891 struct mtk_drm_private *priv = drm_dev->dev_private; 892 struct device *dev = drm_dev->dev; 893 struct mtk_drm_crtc *mtk_crtc; 894 unsigned int num_comp_planes = 0; 895 int ret; 896 int i; 897 bool has_ctm = false; 898 uint gamma_lut_size = 0; 899 struct drm_crtc *tmp; 900 int crtc_i = 0; 901 902 if (!path) 903 return 0; 904 905 priv = priv->all_drm_private[priv_data_index]; 906 907 drm_for_each_crtc(tmp, drm_dev) 908 crtc_i++; 909 910 for (i = 0; i < path_len; i++) { 911 enum mtk_ddp_comp_id comp_id = path[i]; 912 struct device_node *node; 913 struct mtk_ddp_comp *comp; 914 915 node = priv->comp_node[comp_id]; 916 comp = &priv->ddp_comp[comp_id]; 917 918 /* Not all drm components have a DTS device node, such as ovl_adaptor, 919 * which is the drm bring up sub driver 920 */ 921 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) { 922 dev_info(dev, 923 "Not creating crtc %d because component %d is disabled or missing\n", 924 crtc_i, comp_id); 925 return 0; 926 } 927 928 if (!comp->dev) { 929 dev_err(dev, "Component %pOF not initialized\n", node); 930 return -ENODEV; 931 } 932 } 933 934 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 935 if (!mtk_crtc) 936 return -ENOMEM; 937 938 mtk_crtc->mmsys_dev = priv->mmsys_dev; 939 mtk_crtc->ddp_comp_nr = path_len; 940 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 941 sizeof(*mtk_crtc->ddp_comp), 942 GFP_KERNEL); 943 if (!mtk_crtc->ddp_comp) 944 return -ENOMEM; 945 946 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev); 947 if (IS_ERR(mtk_crtc->mutex)) { 948 ret = PTR_ERR(mtk_crtc->mutex); 949 dev_err(dev, "Failed to get mutex: %d\n", ret); 950 return ret; 951 } 952 953 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 954 unsigned int comp_id = path[i]; 955 struct mtk_ddp_comp *comp; 956 957 comp = &priv->ddp_comp[comp_id]; 958 mtk_crtc->ddp_comp[i] = comp; 959 960 if (comp->funcs) { 961 if (comp->funcs->gamma_set) 962 gamma_lut_size = MTK_LUT_SIZE; 963 964 if (comp->funcs->ctm_set) 965 has_ctm = true; 966 } 967 968 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, 969 &mtk_crtc->base); 970 } 971 972 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 973 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 974 975 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 976 sizeof(struct drm_plane), GFP_KERNEL); 977 if (!mtk_crtc->planes) 978 return -ENOMEM; 979 980 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 981 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 982 crtc_i); 983 if (ret) 984 return ret; 985 } 986 987 /* 988 * Default to use the first component as the dma dev. 989 * In the case of ovl_adaptor sub driver, it needs to use the 990 * dma_dev_get function to get representative dma dev. 991 */ 992 mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]); 993 994 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i); 995 if (ret < 0) 996 return ret; 997 998 if (gamma_lut_size) 999 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 1000 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 1001 mutex_init(&mtk_crtc->hw_lock); 1002 1003 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 1004 i = priv->mbox_index++; 1005 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev; 1006 mtk_crtc->cmdq_client.client.tx_block = false; 1007 mtk_crtc->cmdq_client.client.knows_txdone = true; 1008 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb; 1009 mtk_crtc->cmdq_client.chan = 1010 mbox_request_channel(&mtk_crtc->cmdq_client.client, i); 1011 if (IS_ERR(mtk_crtc->cmdq_client.chan)) { 1012 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 1013 drm_crtc_index(&mtk_crtc->base)); 1014 mtk_crtc->cmdq_client.chan = NULL; 1015 } 1016 1017 if (mtk_crtc->cmdq_client.chan) { 1018 ret = of_property_read_u32_index(priv->mutex_node, 1019 "mediatek,gce-events", 1020 i, 1021 &mtk_crtc->cmdq_event); 1022 if (ret) { 1023 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 1024 drm_crtc_index(&mtk_crtc->base)); 1025 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1026 mtk_crtc->cmdq_client.chan = NULL; 1027 } else { 1028 ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client, 1029 &mtk_crtc->cmdq_handle, 1030 PAGE_SIZE); 1031 if (ret) { 1032 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n", 1033 drm_crtc_index(&mtk_crtc->base)); 1034 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1035 mtk_crtc->cmdq_client.chan = NULL; 1036 } 1037 } 1038 1039 /* for sending blocking cmd in crtc disable */ 1040 init_waitqueue_head(&mtk_crtc->cb_blocking_queue); 1041 } 1042 #endif 1043 return 0; 1044 } 1045